mimxrt595s/flexspi0/
ahbcr.rs

1#[doc = "Register `AHBCR` reader"]
2pub struct R(crate::R<AHBCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<AHBCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<AHBCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<AHBCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `AHBCR` writer"]
17pub struct W(crate::W<AHBCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<AHBCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<AHBCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<AHBCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `APAREN` reader - Parallel mode enabled for AHB triggered Command (both read and write)."]
38pub type APAREN_R = crate::BitReader<APAREN_A>;
39#[doc = "Parallel mode enabled for AHB triggered Command (both read and write).\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum APAREN_A {
42    #[doc = "0: Flash will be accessed in Individual mode."]
43    INDIVIDUAL = 0,
44    #[doc = "1: Flash will be accessed in Parallel mode."]
45    ENABLE = 1,
46}
47impl From<APAREN_A> for bool {
48    #[inline(always)]
49    fn from(variant: APAREN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl APAREN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> APAREN_A {
57        match self.bits {
58            false => APAREN_A::INDIVIDUAL,
59            true => APAREN_A::ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `INDIVIDUAL`"]
63    #[inline(always)]
64    pub fn is_individual(&self) -> bool {
65        *self == APAREN_A::INDIVIDUAL
66    }
67    #[doc = "Checks if the value of the field is `ENABLE`"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == APAREN_A::ENABLE
71    }
72}
73#[doc = "Field `APAREN` writer - Parallel mode enabled for AHB triggered Command (both read and write)."]
74pub type APAREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, APAREN_A, O>;
75impl<'a, const O: u8> APAREN_W<'a, O> {
76    #[doc = "Flash will be accessed in Individual mode."]
77    #[inline(always)]
78    pub fn individual(self) -> &'a mut W {
79        self.variant(APAREN_A::INDIVIDUAL)
80    }
81    #[doc = "Flash will be accessed in Parallel mode."]
82    #[inline(always)]
83    pub fn enable(self) -> &'a mut W {
84        self.variant(APAREN_A::ENABLE)
85    }
86}
87#[doc = "Field `CLRAHBTXBUF` reader - Clear the status/pointers of AHB TX Buffer. Auto-cleared."]
88pub type CLRAHBTXBUF_R = crate::BitReader<CLRAHBTXBUF_A>;
89#[doc = "Clear the status/pointers of AHB TX Buffer. Auto-cleared.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CLRAHBTXBUF_A {
92    #[doc = "0: No function."]
93    VAL0 = 0,
94    #[doc = "1: Clear operation enable."]
95    VAL1 = 1,
96}
97impl From<CLRAHBTXBUF_A> for bool {
98    #[inline(always)]
99    fn from(variant: CLRAHBTXBUF_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CLRAHBTXBUF_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CLRAHBTXBUF_A {
107        match self.bits {
108            false => CLRAHBTXBUF_A::VAL0,
109            true => CLRAHBTXBUF_A::VAL1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `VAL0`"]
113    #[inline(always)]
114    pub fn is_val0(&self) -> bool {
115        *self == CLRAHBTXBUF_A::VAL0
116    }
117    #[doc = "Checks if the value of the field is `VAL1`"]
118    #[inline(always)]
119    pub fn is_val1(&self) -> bool {
120        *self == CLRAHBTXBUF_A::VAL1
121    }
122}
123#[doc = "Field `CLRAHBTXBUF` writer - Clear the status/pointers of AHB TX Buffer. Auto-cleared."]
124pub type CLRAHBTXBUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, CLRAHBTXBUF_A, O>;
125impl<'a, const O: u8> CLRAHBTXBUF_W<'a, O> {
126    #[doc = "No function."]
127    #[inline(always)]
128    pub fn val0(self) -> &'a mut W {
129        self.variant(CLRAHBTXBUF_A::VAL0)
130    }
131    #[doc = "Clear operation enable."]
132    #[inline(always)]
133    pub fn val1(self) -> &'a mut W {
134        self.variant(CLRAHBTXBUF_A::VAL1)
135    }
136}
137#[doc = "Field `CACHABLEEN` reader - Enable AHB bus cachable read access support."]
138pub type CACHABLEEN_R = crate::BitReader<CACHABLEEN_A>;
139#[doc = "Enable AHB bus cachable read access support.\n\nValue on reset: 1"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum CACHABLEEN_A {
142    #[doc = "0: Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer."]
143    VAL0 = 0,
144    #[doc = "1: Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first."]
145    VAL1 = 1,
146}
147impl From<CACHABLEEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: CACHABLEEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl CACHABLEEN_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> CACHABLEEN_A {
157        match self.bits {
158            false => CACHABLEEN_A::VAL0,
159            true => CACHABLEEN_A::VAL1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `VAL0`"]
163    #[inline(always)]
164    pub fn is_val0(&self) -> bool {
165        *self == CACHABLEEN_A::VAL0
166    }
167    #[doc = "Checks if the value of the field is `VAL1`"]
168    #[inline(always)]
169    pub fn is_val1(&self) -> bool {
170        *self == CACHABLEEN_A::VAL1
171    }
172}
173#[doc = "Field `CACHABLEEN` writer - Enable AHB bus cachable read access support."]
174pub type CACHABLEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, CACHABLEEN_A, O>;
175impl<'a, const O: u8> CACHABLEEN_W<'a, O> {
176    #[doc = "Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer."]
177    #[inline(always)]
178    pub fn val0(self) -> &'a mut W {
179        self.variant(CACHABLEEN_A::VAL0)
180    }
181    #[doc = "Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first."]
182    #[inline(always)]
183    pub fn val1(self) -> &'a mut W {
184        self.variant(CACHABLEEN_A::VAL1)
185    }
186}
187#[doc = "Field `BUFFERABLEEN` reader - Enable AHB bus bufferable write access support."]
188pub type BUFFERABLEEN_R = crate::BitReader<BUFFERABLEEN_A>;
189#[doc = "Enable AHB bus bufferable write access support.\n\nValue on reset: 1"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum BUFFERABLEEN_A {
192    #[doc = "0: Disabled. For all AHB write accesses (bufferable or non-bufferable), FlexSPI will return AHB Bus ready after all data is transmitted to external device and AHB command finished."]
193    VAL0 = 0,
194    #[doc = "1: Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished."]
195    VAL1 = 1,
196}
197impl From<BUFFERABLEEN_A> for bool {
198    #[inline(always)]
199    fn from(variant: BUFFERABLEEN_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl BUFFERABLEEN_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> BUFFERABLEEN_A {
207        match self.bits {
208            false => BUFFERABLEEN_A::VAL0,
209            true => BUFFERABLEEN_A::VAL1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `VAL0`"]
213    #[inline(always)]
214    pub fn is_val0(&self) -> bool {
215        *self == BUFFERABLEEN_A::VAL0
216    }
217    #[doc = "Checks if the value of the field is `VAL1`"]
218    #[inline(always)]
219    pub fn is_val1(&self) -> bool {
220        *self == BUFFERABLEEN_A::VAL1
221    }
222}
223#[doc = "Field `BUFFERABLEEN` writer - Enable AHB bus bufferable write access support."]
224pub type BUFFERABLEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, BUFFERABLEEN_A, O>;
225impl<'a, const O: u8> BUFFERABLEEN_W<'a, O> {
226    #[doc = "Disabled. For all AHB write accesses (bufferable or non-bufferable), FlexSPI will return AHB Bus ready after all data is transmitted to external device and AHB command finished."]
227    #[inline(always)]
228    pub fn val0(self) -> &'a mut W {
229        self.variant(BUFFERABLEEN_A::VAL0)
230    }
231    #[doc = "Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished."]
232    #[inline(always)]
233    pub fn val1(self) -> &'a mut W {
234        self.variant(BUFFERABLEEN_A::VAL1)
235    }
236}
237#[doc = "Field `PREFETCHEN` reader - AHB Read Prefetch Enable."]
238pub type PREFETCHEN_R = crate::BitReader<bool>;
239#[doc = "Field `PREFETCHEN` writer - AHB Read Prefetch Enable."]
240pub type PREFETCHEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, bool, O>;
241#[doc = "Field `READADDROPT` reader - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation."]
242pub type READADDROPT_R = crate::BitReader<READADDROPT_A>;
243#[doc = "AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation.\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum READADDROPT_A {
246    #[doc = "0: There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable."]
247    VAL0 = 0,
248    #[doc = "1: There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement."]
249    VAL1 = 1,
250}
251impl From<READADDROPT_A> for bool {
252    #[inline(always)]
253    fn from(variant: READADDROPT_A) -> Self {
254        variant as u8 != 0
255    }
256}
257impl READADDROPT_R {
258    #[doc = "Get enumerated values variant"]
259    #[inline(always)]
260    pub fn variant(&self) -> READADDROPT_A {
261        match self.bits {
262            false => READADDROPT_A::VAL0,
263            true => READADDROPT_A::VAL1,
264        }
265    }
266    #[doc = "Checks if the value of the field is `VAL0`"]
267    #[inline(always)]
268    pub fn is_val0(&self) -> bool {
269        *self == READADDROPT_A::VAL0
270    }
271    #[doc = "Checks if the value of the field is `VAL1`"]
272    #[inline(always)]
273    pub fn is_val1(&self) -> bool {
274        *self == READADDROPT_A::VAL1
275    }
276}
277#[doc = "Field `READADDROPT` writer - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation."]
278pub type READADDROPT_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, READADDROPT_A, O>;
279impl<'a, const O: u8> READADDROPT_W<'a, O> {
280    #[doc = "There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable."]
281    #[inline(always)]
282    pub fn val0(self) -> &'a mut W {
283        self.variant(READADDROPT_A::VAL0)
284    }
285    #[doc = "There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement."]
286    #[inline(always)]
287    pub fn val1(self) -> &'a mut W {
288        self.variant(READADDROPT_A::VAL1)
289    }
290}
291#[doc = "Field `RESUMEDISABLE` reader - AHB Read Resume Disable"]
292pub type RESUMEDISABLE_R = crate::BitReader<RESUMEDISABLE_A>;
293#[doc = "AHB Read Resume Disable\n\nValue on reset: 0"]
294#[derive(Clone, Copy, Debug, PartialEq, Eq)]
295pub enum RESUMEDISABLE_A {
296    #[doc = "0: Suspended AHB read prefetch will start to resume when AHB is IDLE"]
297    VAL0 = 0,
298    #[doc = "1: Suspended AHB read prefetch will not resume once it is aborted"]
299    VAL1 = 1,
300}
301impl From<RESUMEDISABLE_A> for bool {
302    #[inline(always)]
303    fn from(variant: RESUMEDISABLE_A) -> Self {
304        variant as u8 != 0
305    }
306}
307impl RESUMEDISABLE_R {
308    #[doc = "Get enumerated values variant"]
309    #[inline(always)]
310    pub fn variant(&self) -> RESUMEDISABLE_A {
311        match self.bits {
312            false => RESUMEDISABLE_A::VAL0,
313            true => RESUMEDISABLE_A::VAL1,
314        }
315    }
316    #[doc = "Checks if the value of the field is `VAL0`"]
317    #[inline(always)]
318    pub fn is_val0(&self) -> bool {
319        *self == RESUMEDISABLE_A::VAL0
320    }
321    #[doc = "Checks if the value of the field is `VAL1`"]
322    #[inline(always)]
323    pub fn is_val1(&self) -> bool {
324        *self == RESUMEDISABLE_A::VAL1
325    }
326}
327#[doc = "Field `RESUMEDISABLE` writer - AHB Read Resume Disable"]
328pub type RESUMEDISABLE_W<'a, const O: u8> =
329    crate::BitWriter<'a, u32, AHBCR_SPEC, RESUMEDISABLE_A, O>;
330impl<'a, const O: u8> RESUMEDISABLE_W<'a, O> {
331    #[doc = "Suspended AHB read prefetch will start to resume when AHB is IDLE"]
332    #[inline(always)]
333    pub fn val0(self) -> &'a mut W {
334        self.variant(RESUMEDISABLE_A::VAL0)
335    }
336    #[doc = "Suspended AHB read prefetch will not resume once it is aborted"]
337    #[inline(always)]
338    pub fn val1(self) -> &'a mut W {
339        self.variant(RESUMEDISABLE_A::VAL1)
340    }
341}
342#[doc = "Field `READSZALIGN` reader - AHB Read Size Alignment"]
343pub type READSZALIGN_R = crate::BitReader<READSZALIGN_A>;
344#[doc = "AHB Read Size Alignment\n\nValue on reset: 0"]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum READSZALIGN_A {
347    #[doc = "0: AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN..."]
348    VAL0 = 0,
349    #[doc = "1: AHB read size to up size to 8 bytes aligned, no prefetching"]
350    VAL1 = 1,
351}
352impl From<READSZALIGN_A> for bool {
353    #[inline(always)]
354    fn from(variant: READSZALIGN_A) -> Self {
355        variant as u8 != 0
356    }
357}
358impl READSZALIGN_R {
359    #[doc = "Get enumerated values variant"]
360    #[inline(always)]
361    pub fn variant(&self) -> READSZALIGN_A {
362        match self.bits {
363            false => READSZALIGN_A::VAL0,
364            true => READSZALIGN_A::VAL1,
365        }
366    }
367    #[doc = "Checks if the value of the field is `VAL0`"]
368    #[inline(always)]
369    pub fn is_val0(&self) -> bool {
370        *self == READSZALIGN_A::VAL0
371    }
372    #[doc = "Checks if the value of the field is `VAL1`"]
373    #[inline(always)]
374    pub fn is_val1(&self) -> bool {
375        *self == READSZALIGN_A::VAL1
376    }
377}
378#[doc = "Field `READSZALIGN` writer - AHB Read Size Alignment"]
379pub type READSZALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBCR_SPEC, READSZALIGN_A, O>;
380impl<'a, const O: u8> READSZALIGN_W<'a, O> {
381    #[doc = "AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN..."]
382    #[inline(always)]
383    pub fn val0(self) -> &'a mut W {
384        self.variant(READSZALIGN_A::VAL0)
385    }
386    #[doc = "AHB read size to up size to 8 bytes aligned, no prefetching"]
387    #[inline(always)]
388    pub fn val1(self) -> &'a mut W {
389        self.variant(READSZALIGN_A::VAL1)
390    }
391}
392impl R {
393    #[doc = "Bit 0 - Parallel mode enabled for AHB triggered Command (both read and write)."]
394    #[inline(always)]
395    pub fn aparen(&self) -> APAREN_R {
396        APAREN_R::new((self.bits & 1) != 0)
397    }
398    #[doc = "Bit 2 - Clear the status/pointers of AHB TX Buffer. Auto-cleared."]
399    #[inline(always)]
400    pub fn clrahbtxbuf(&self) -> CLRAHBTXBUF_R {
401        CLRAHBTXBUF_R::new(((self.bits >> 2) & 1) != 0)
402    }
403    #[doc = "Bit 3 - Enable AHB bus cachable read access support."]
404    #[inline(always)]
405    pub fn cachableen(&self) -> CACHABLEEN_R {
406        CACHABLEEN_R::new(((self.bits >> 3) & 1) != 0)
407    }
408    #[doc = "Bit 4 - Enable AHB bus bufferable write access support."]
409    #[inline(always)]
410    pub fn bufferableen(&self) -> BUFFERABLEEN_R {
411        BUFFERABLEEN_R::new(((self.bits >> 4) & 1) != 0)
412    }
413    #[doc = "Bit 5 - AHB Read Prefetch Enable."]
414    #[inline(always)]
415    pub fn prefetchen(&self) -> PREFETCHEN_R {
416        PREFETCHEN_R::new(((self.bits >> 5) & 1) != 0)
417    }
418    #[doc = "Bit 6 - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation."]
419    #[inline(always)]
420    pub fn readaddropt(&self) -> READADDROPT_R {
421        READADDROPT_R::new(((self.bits >> 6) & 1) != 0)
422    }
423    #[doc = "Bit 7 - AHB Read Resume Disable"]
424    #[inline(always)]
425    pub fn resumedisable(&self) -> RESUMEDISABLE_R {
426        RESUMEDISABLE_R::new(((self.bits >> 7) & 1) != 0)
427    }
428    #[doc = "Bit 10 - AHB Read Size Alignment"]
429    #[inline(always)]
430    pub fn readszalign(&self) -> READSZALIGN_R {
431        READSZALIGN_R::new(((self.bits >> 10) & 1) != 0)
432    }
433}
434impl W {
435    #[doc = "Bit 0 - Parallel mode enabled for AHB triggered Command (both read and write)."]
436    #[inline(always)]
437    #[must_use]
438    pub fn aparen(&mut self) -> APAREN_W<0> {
439        APAREN_W::new(self)
440    }
441    #[doc = "Bit 2 - Clear the status/pointers of AHB TX Buffer. Auto-cleared."]
442    #[inline(always)]
443    #[must_use]
444    pub fn clrahbtxbuf(&mut self) -> CLRAHBTXBUF_W<2> {
445        CLRAHBTXBUF_W::new(self)
446    }
447    #[doc = "Bit 3 - Enable AHB bus cachable read access support."]
448    #[inline(always)]
449    #[must_use]
450    pub fn cachableen(&mut self) -> CACHABLEEN_W<3> {
451        CACHABLEEN_W::new(self)
452    }
453    #[doc = "Bit 4 - Enable AHB bus bufferable write access support."]
454    #[inline(always)]
455    #[must_use]
456    pub fn bufferableen(&mut self) -> BUFFERABLEEN_W<4> {
457        BUFFERABLEEN_W::new(self)
458    }
459    #[doc = "Bit 5 - AHB Read Prefetch Enable."]
460    #[inline(always)]
461    #[must_use]
462    pub fn prefetchen(&mut self) -> PREFETCHEN_W<5> {
463        PREFETCHEN_W::new(self)
464    }
465    #[doc = "Bit 6 - AHB Read Address option bit. This option bit is intended to remove AHB burst start address alignment limitation."]
466    #[inline(always)]
467    #[must_use]
468    pub fn readaddropt(&mut self) -> READADDROPT_W<6> {
469        READADDROPT_W::new(self)
470    }
471    #[doc = "Bit 7 - AHB Read Resume Disable"]
472    #[inline(always)]
473    #[must_use]
474    pub fn resumedisable(&mut self) -> RESUMEDISABLE_W<7> {
475        RESUMEDISABLE_W::new(self)
476    }
477    #[doc = "Bit 10 - AHB Read Size Alignment"]
478    #[inline(always)]
479    #[must_use]
480    pub fn readszalign(&mut self) -> READSZALIGN_W<10> {
481        READSZALIGN_W::new(self)
482    }
483    #[doc = "Writes raw bits to the register."]
484    #[inline(always)]
485    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
486        self.0.bits(bits);
487        self
488    }
489}
490#[doc = "AHB Bus Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbcr](index.html) module"]
491pub struct AHBCR_SPEC;
492impl crate::RegisterSpec for AHBCR_SPEC {
493    type Ux = u32;
494}
495#[doc = "`read()` method returns [ahbcr::R](R) reader structure"]
496impl crate::Readable for AHBCR_SPEC {
497    type Reader = R;
498}
499#[doc = "`write(|w| ..)` method takes [ahbcr::W](W) writer structure"]
500impl crate::Writable for AHBCR_SPEC {
501    type Writer = W;
502    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
503    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
504}
505#[doc = "`reset()` method sets AHBCR to value 0x18"]
506impl crate::Resettable for AHBCR_SPEC {
507    const RESET_VALUE: Self::Ux = 0x18;
508}
mimxrt595s/flexspi0/ahbcr.rs

mimxrt595s/flexspi0/
ahbcr.rs
