1#[doc = "Register `DMAC1_REQ_ENA0_CLR` reader"]
2pub struct R(crate::R<DMAC1_REQ_ENA0_CLR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DMAC1_REQ_ENA0_CLR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DMAC1_REQ_ENA0_CLR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DMAC1_REQ_ENA0_CLR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DMAC1_REQ_ENA0_CLR` writer"]
17pub struct W(crate::W<DMAC1_REQ_ENA0_CLR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DMAC1_REQ_ENA0_CLR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DMAC1_REQ_ENA0_CLR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DMAC1_REQ_ENA0_CLR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `FLEXCOMM0_RX` reader - FLEXCOMM0 RX enable clear"]
38pub type FLEXCOMM0_RX_R = crate::BitReader<FLEXCOMM0_RX_A>;
39#[doc = "FLEXCOMM0 RX enable clear\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum FLEXCOMM0_RX_A {
42 #[doc = "0: No effect"]
43 FLEXCOMM0_RX_0 = 0,
44 #[doc = "1: Clears the ENA0 Bit"]
45 FLEXCOMM0_RX_1 = 1,
46}
47impl From<FLEXCOMM0_RX_A> for bool {
48 #[inline(always)]
49 fn from(variant: FLEXCOMM0_RX_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl FLEXCOMM0_RX_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> FLEXCOMM0_RX_A {
57 match self.bits {
58 false => FLEXCOMM0_RX_A::FLEXCOMM0_RX_0,
59 true => FLEXCOMM0_RX_A::FLEXCOMM0_RX_1,
60 }
61 }
62 #[doc = "Checks if the value of the field is `FLEXCOMM0_RX_0`"]
63 #[inline(always)]
64 pub fn is_flexcomm0_rx_0(&self) -> bool {
65 *self == FLEXCOMM0_RX_A::FLEXCOMM0_RX_0
66 }
67 #[doc = "Checks if the value of the field is `FLEXCOMM0_RX_1`"]
68 #[inline(always)]
69 pub fn is_flexcomm0_rx_1(&self) -> bool {
70 *self == FLEXCOMM0_RX_A::FLEXCOMM0_RX_1
71 }
72}
73#[doc = "Field `FLEXCOMM0_RX` writer - FLEXCOMM0 RX enable clear"]
74pub type FLEXCOMM0_RX_W<'a, const O: u8> =
75 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM0_RX_A, O>;
76impl<'a, const O: u8> FLEXCOMM0_RX_W<'a, O> {
77 #[doc = "No effect"]
78 #[inline(always)]
79 pub fn flexcomm0_rx_0(self) -> &'a mut W {
80 self.variant(FLEXCOMM0_RX_A::FLEXCOMM0_RX_0)
81 }
82 #[doc = "Clears the ENA0 Bit"]
83 #[inline(always)]
84 pub fn flexcomm0_rx_1(self) -> &'a mut W {
85 self.variant(FLEXCOMM0_RX_A::FLEXCOMM0_RX_1)
86 }
87}
88#[doc = "Field `FLEXCOMM0_TX` reader - FLEXCOMM0 TX enable clear"]
89pub type FLEXCOMM0_TX_R = crate::BitReader<FLEXCOMM0_TX_A>;
90#[doc = "FLEXCOMM0 TX enable clear\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92pub enum FLEXCOMM0_TX_A {
93 #[doc = "0: No effect"]
94 FLEXCOMM0_TX_0 = 0,
95 #[doc = "1: Clears the ENA0 Bit"]
96 FLEXCOMM0_TX_1 = 1,
97}
98impl From<FLEXCOMM0_TX_A> for bool {
99 #[inline(always)]
100 fn from(variant: FLEXCOMM0_TX_A) -> Self {
101 variant as u8 != 0
102 }
103}
104impl FLEXCOMM0_TX_R {
105 #[doc = "Get enumerated values variant"]
106 #[inline(always)]
107 pub fn variant(&self) -> FLEXCOMM0_TX_A {
108 match self.bits {
109 false => FLEXCOMM0_TX_A::FLEXCOMM0_TX_0,
110 true => FLEXCOMM0_TX_A::FLEXCOMM0_TX_1,
111 }
112 }
113 #[doc = "Checks if the value of the field is `FLEXCOMM0_TX_0`"]
114 #[inline(always)]
115 pub fn is_flexcomm0_tx_0(&self) -> bool {
116 *self == FLEXCOMM0_TX_A::FLEXCOMM0_TX_0
117 }
118 #[doc = "Checks if the value of the field is `FLEXCOMM0_TX_1`"]
119 #[inline(always)]
120 pub fn is_flexcomm0_tx_1(&self) -> bool {
121 *self == FLEXCOMM0_TX_A::FLEXCOMM0_TX_1
122 }
123}
124#[doc = "Field `FLEXCOMM0_TX` writer - FLEXCOMM0 TX enable clear"]
125pub type FLEXCOMM0_TX_W<'a, const O: u8> =
126 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM0_TX_A, O>;
127impl<'a, const O: u8> FLEXCOMM0_TX_W<'a, O> {
128 #[doc = "No effect"]
129 #[inline(always)]
130 pub fn flexcomm0_tx_0(self) -> &'a mut W {
131 self.variant(FLEXCOMM0_TX_A::FLEXCOMM0_TX_0)
132 }
133 #[doc = "Clears the ENA0 Bit"]
134 #[inline(always)]
135 pub fn flexcomm0_tx_1(self) -> &'a mut W {
136 self.variant(FLEXCOMM0_TX_A::FLEXCOMM0_TX_1)
137 }
138}
139#[doc = "Field `FLEXCOMM1_RX` reader - FLEXCOMM1 RX enable clear"]
140pub type FLEXCOMM1_RX_R = crate::BitReader<FLEXCOMM1_RX_A>;
141#[doc = "FLEXCOMM1 RX enable clear\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum FLEXCOMM1_RX_A {
144 #[doc = "0: No effect"]
145 FLEXCOMM1_RX_0 = 0,
146 #[doc = "1: Clears the ENA0 Bit"]
147 FLEXCOMM1_RX_1 = 1,
148}
149impl From<FLEXCOMM1_RX_A> for bool {
150 #[inline(always)]
151 fn from(variant: FLEXCOMM1_RX_A) -> Self {
152 variant as u8 != 0
153 }
154}
155impl FLEXCOMM1_RX_R {
156 #[doc = "Get enumerated values variant"]
157 #[inline(always)]
158 pub fn variant(&self) -> FLEXCOMM1_RX_A {
159 match self.bits {
160 false => FLEXCOMM1_RX_A::FLEXCOMM1_RX_0,
161 true => FLEXCOMM1_RX_A::FLEXCOMM1_RX_1,
162 }
163 }
164 #[doc = "Checks if the value of the field is `FLEXCOMM1_RX_0`"]
165 #[inline(always)]
166 pub fn is_flexcomm1_rx_0(&self) -> bool {
167 *self == FLEXCOMM1_RX_A::FLEXCOMM1_RX_0
168 }
169 #[doc = "Checks if the value of the field is `FLEXCOMM1_RX_1`"]
170 #[inline(always)]
171 pub fn is_flexcomm1_rx_1(&self) -> bool {
172 *self == FLEXCOMM1_RX_A::FLEXCOMM1_RX_1
173 }
174}
175#[doc = "Field `FLEXCOMM1_RX` writer - FLEXCOMM1 RX enable clear"]
176pub type FLEXCOMM1_RX_W<'a, const O: u8> =
177 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM1_RX_A, O>;
178impl<'a, const O: u8> FLEXCOMM1_RX_W<'a, O> {
179 #[doc = "No effect"]
180 #[inline(always)]
181 pub fn flexcomm1_rx_0(self) -> &'a mut W {
182 self.variant(FLEXCOMM1_RX_A::FLEXCOMM1_RX_0)
183 }
184 #[doc = "Clears the ENA0 Bit"]
185 #[inline(always)]
186 pub fn flexcomm1_rx_1(self) -> &'a mut W {
187 self.variant(FLEXCOMM1_RX_A::FLEXCOMM1_RX_1)
188 }
189}
190#[doc = "Field `FLEXCOMM1_TX` reader - FLEXCOMM1 TX enable clear"]
191pub type FLEXCOMM1_TX_R = crate::BitReader<FLEXCOMM1_TX_A>;
192#[doc = "FLEXCOMM1 TX enable clear\n\nValue on reset: 0"]
193#[derive(Clone, Copy, Debug, PartialEq, Eq)]
194pub enum FLEXCOMM1_TX_A {
195 #[doc = "0: No effect"]
196 FLEXCOMM1_TX_0 = 0,
197 #[doc = "1: Clears the ENA0 Bit"]
198 FLEXCOMM1_TX_1 = 1,
199}
200impl From<FLEXCOMM1_TX_A> for bool {
201 #[inline(always)]
202 fn from(variant: FLEXCOMM1_TX_A) -> Self {
203 variant as u8 != 0
204 }
205}
206impl FLEXCOMM1_TX_R {
207 #[doc = "Get enumerated values variant"]
208 #[inline(always)]
209 pub fn variant(&self) -> FLEXCOMM1_TX_A {
210 match self.bits {
211 false => FLEXCOMM1_TX_A::FLEXCOMM1_TX_0,
212 true => FLEXCOMM1_TX_A::FLEXCOMM1_TX_1,
213 }
214 }
215 #[doc = "Checks if the value of the field is `FLEXCOMM1_TX_0`"]
216 #[inline(always)]
217 pub fn is_flexcomm1_tx_0(&self) -> bool {
218 *self == FLEXCOMM1_TX_A::FLEXCOMM1_TX_0
219 }
220 #[doc = "Checks if the value of the field is `FLEXCOMM1_TX_1`"]
221 #[inline(always)]
222 pub fn is_flexcomm1_tx_1(&self) -> bool {
223 *self == FLEXCOMM1_TX_A::FLEXCOMM1_TX_1
224 }
225}
226#[doc = "Field `FLEXCOMM1_TX` writer - FLEXCOMM1 TX enable clear"]
227pub type FLEXCOMM1_TX_W<'a, const O: u8> =
228 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM1_TX_A, O>;
229impl<'a, const O: u8> FLEXCOMM1_TX_W<'a, O> {
230 #[doc = "No effect"]
231 #[inline(always)]
232 pub fn flexcomm1_tx_0(self) -> &'a mut W {
233 self.variant(FLEXCOMM1_TX_A::FLEXCOMM1_TX_0)
234 }
235 #[doc = "Clears the ENA0 Bit"]
236 #[inline(always)]
237 pub fn flexcomm1_tx_1(self) -> &'a mut W {
238 self.variant(FLEXCOMM1_TX_A::FLEXCOMM1_TX_1)
239 }
240}
241#[doc = "Field `FLEXCOMM2_RX` reader - FLEXCOMM2 RX enable clear"]
242pub type FLEXCOMM2_RX_R = crate::BitReader<FLEXCOMM2_RX_A>;
243#[doc = "FLEXCOMM2 RX enable clear\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245pub enum FLEXCOMM2_RX_A {
246 #[doc = "0: No effect"]
247 FLEXCOMM2_RX_0 = 0,
248 #[doc = "1: Clears the ENA0 Bit"]
249 FLEXCOMM2_RX_1 = 1,
250}
251impl From<FLEXCOMM2_RX_A> for bool {
252 #[inline(always)]
253 fn from(variant: FLEXCOMM2_RX_A) -> Self {
254 variant as u8 != 0
255 }
256}
257impl FLEXCOMM2_RX_R {
258 #[doc = "Get enumerated values variant"]
259 #[inline(always)]
260 pub fn variant(&self) -> FLEXCOMM2_RX_A {
261 match self.bits {
262 false => FLEXCOMM2_RX_A::FLEXCOMM2_RX_0,
263 true => FLEXCOMM2_RX_A::FLEXCOMM2_RX_1,
264 }
265 }
266 #[doc = "Checks if the value of the field is `FLEXCOMM2_RX_0`"]
267 #[inline(always)]
268 pub fn is_flexcomm2_rx_0(&self) -> bool {
269 *self == FLEXCOMM2_RX_A::FLEXCOMM2_RX_0
270 }
271 #[doc = "Checks if the value of the field is `FLEXCOMM2_RX_1`"]
272 #[inline(always)]
273 pub fn is_flexcomm2_rx_1(&self) -> bool {
274 *self == FLEXCOMM2_RX_A::FLEXCOMM2_RX_1
275 }
276}
277#[doc = "Field `FLEXCOMM2_RX` writer - FLEXCOMM2 RX enable clear"]
278pub type FLEXCOMM2_RX_W<'a, const O: u8> =
279 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM2_RX_A, O>;
280impl<'a, const O: u8> FLEXCOMM2_RX_W<'a, O> {
281 #[doc = "No effect"]
282 #[inline(always)]
283 pub fn flexcomm2_rx_0(self) -> &'a mut W {
284 self.variant(FLEXCOMM2_RX_A::FLEXCOMM2_RX_0)
285 }
286 #[doc = "Clears the ENA0 Bit"]
287 #[inline(always)]
288 pub fn flexcomm2_rx_1(self) -> &'a mut W {
289 self.variant(FLEXCOMM2_RX_A::FLEXCOMM2_RX_1)
290 }
291}
292#[doc = "Field `FLEXCOMM2_TX` reader - FLEXCOMM2 TX enable clear"]
293pub type FLEXCOMM2_TX_R = crate::BitReader<FLEXCOMM2_TX_A>;
294#[doc = "FLEXCOMM2 TX enable clear\n\nValue on reset: 0"]
295#[derive(Clone, Copy, Debug, PartialEq, Eq)]
296pub enum FLEXCOMM2_TX_A {
297 #[doc = "0: No effect"]
298 FLEXCOMM2_TX_0 = 0,
299 #[doc = "1: Clears the ENA0 Bit"]
300 FLEXCOMM2_TX_1 = 1,
301}
302impl From<FLEXCOMM2_TX_A> for bool {
303 #[inline(always)]
304 fn from(variant: FLEXCOMM2_TX_A) -> Self {
305 variant as u8 != 0
306 }
307}
308impl FLEXCOMM2_TX_R {
309 #[doc = "Get enumerated values variant"]
310 #[inline(always)]
311 pub fn variant(&self) -> FLEXCOMM2_TX_A {
312 match self.bits {
313 false => FLEXCOMM2_TX_A::FLEXCOMM2_TX_0,
314 true => FLEXCOMM2_TX_A::FLEXCOMM2_TX_1,
315 }
316 }
317 #[doc = "Checks if the value of the field is `FLEXCOMM2_TX_0`"]
318 #[inline(always)]
319 pub fn is_flexcomm2_tx_0(&self) -> bool {
320 *self == FLEXCOMM2_TX_A::FLEXCOMM2_TX_0
321 }
322 #[doc = "Checks if the value of the field is `FLEXCOMM2_TX_1`"]
323 #[inline(always)]
324 pub fn is_flexcomm2_tx_1(&self) -> bool {
325 *self == FLEXCOMM2_TX_A::FLEXCOMM2_TX_1
326 }
327}
328#[doc = "Field `FLEXCOMM2_TX` writer - FLEXCOMM2 TX enable clear"]
329pub type FLEXCOMM2_TX_W<'a, const O: u8> =
330 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM2_TX_A, O>;
331impl<'a, const O: u8> FLEXCOMM2_TX_W<'a, O> {
332 #[doc = "No effect"]
333 #[inline(always)]
334 pub fn flexcomm2_tx_0(self) -> &'a mut W {
335 self.variant(FLEXCOMM2_TX_A::FLEXCOMM2_TX_0)
336 }
337 #[doc = "Clears the ENA0 Bit"]
338 #[inline(always)]
339 pub fn flexcomm2_tx_1(self) -> &'a mut W {
340 self.variant(FLEXCOMM2_TX_A::FLEXCOMM2_TX_1)
341 }
342}
343#[doc = "Field `FLEXCOMM3_RX` reader - FLEXCOMM3 RX enable clear"]
344pub type FLEXCOMM3_RX_R = crate::BitReader<FLEXCOMM3_RX_A>;
345#[doc = "FLEXCOMM3 RX enable clear\n\nValue on reset: 0"]
346#[derive(Clone, Copy, Debug, PartialEq, Eq)]
347pub enum FLEXCOMM3_RX_A {
348 #[doc = "0: No effect"]
349 FLEXCOMM3_RX_0 = 0,
350 #[doc = "1: Clears the ENA0 Bit"]
351 FLEXCOMM3_RX_1 = 1,
352}
353impl From<FLEXCOMM3_RX_A> for bool {
354 #[inline(always)]
355 fn from(variant: FLEXCOMM3_RX_A) -> Self {
356 variant as u8 != 0
357 }
358}
359impl FLEXCOMM3_RX_R {
360 #[doc = "Get enumerated values variant"]
361 #[inline(always)]
362 pub fn variant(&self) -> FLEXCOMM3_RX_A {
363 match self.bits {
364 false => FLEXCOMM3_RX_A::FLEXCOMM3_RX_0,
365 true => FLEXCOMM3_RX_A::FLEXCOMM3_RX_1,
366 }
367 }
368 #[doc = "Checks if the value of the field is `FLEXCOMM3_RX_0`"]
369 #[inline(always)]
370 pub fn is_flexcomm3_rx_0(&self) -> bool {
371 *self == FLEXCOMM3_RX_A::FLEXCOMM3_RX_0
372 }
373 #[doc = "Checks if the value of the field is `FLEXCOMM3_RX_1`"]
374 #[inline(always)]
375 pub fn is_flexcomm3_rx_1(&self) -> bool {
376 *self == FLEXCOMM3_RX_A::FLEXCOMM3_RX_1
377 }
378}
379#[doc = "Field `FLEXCOMM3_RX` writer - FLEXCOMM3 RX enable clear"]
380pub type FLEXCOMM3_RX_W<'a, const O: u8> =
381 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM3_RX_A, O>;
382impl<'a, const O: u8> FLEXCOMM3_RX_W<'a, O> {
383 #[doc = "No effect"]
384 #[inline(always)]
385 pub fn flexcomm3_rx_0(self) -> &'a mut W {
386 self.variant(FLEXCOMM3_RX_A::FLEXCOMM3_RX_0)
387 }
388 #[doc = "Clears the ENA0 Bit"]
389 #[inline(always)]
390 pub fn flexcomm3_rx_1(self) -> &'a mut W {
391 self.variant(FLEXCOMM3_RX_A::FLEXCOMM3_RX_1)
392 }
393}
394#[doc = "Field `FLEXCOMM3_TX` reader - FLEXCOMM3 TX enable clear"]
395pub type FLEXCOMM3_TX_R = crate::BitReader<FLEXCOMM3_TX_A>;
396#[doc = "FLEXCOMM3 TX enable clear\n\nValue on reset: 0"]
397#[derive(Clone, Copy, Debug, PartialEq, Eq)]
398pub enum FLEXCOMM3_TX_A {
399 #[doc = "0: No effect"]
400 FLEXCOMM3_TX_1 = 0,
401 #[doc = "1: Clears the ENA0 Bit"]
402 FLEXCOMM3_TX_0 = 1,
403}
404impl From<FLEXCOMM3_TX_A> for bool {
405 #[inline(always)]
406 fn from(variant: FLEXCOMM3_TX_A) -> Self {
407 variant as u8 != 0
408 }
409}
410impl FLEXCOMM3_TX_R {
411 #[doc = "Get enumerated values variant"]
412 #[inline(always)]
413 pub fn variant(&self) -> FLEXCOMM3_TX_A {
414 match self.bits {
415 false => FLEXCOMM3_TX_A::FLEXCOMM3_TX_1,
416 true => FLEXCOMM3_TX_A::FLEXCOMM3_TX_0,
417 }
418 }
419 #[doc = "Checks if the value of the field is `FLEXCOMM3_TX_1`"]
420 #[inline(always)]
421 pub fn is_flexcomm3_tx_1(&self) -> bool {
422 *self == FLEXCOMM3_TX_A::FLEXCOMM3_TX_1
423 }
424 #[doc = "Checks if the value of the field is `FLEXCOMM3_TX_0`"]
425 #[inline(always)]
426 pub fn is_flexcomm3_tx_0(&self) -> bool {
427 *self == FLEXCOMM3_TX_A::FLEXCOMM3_TX_0
428 }
429}
430#[doc = "Field `FLEXCOMM3_TX` writer - FLEXCOMM3 TX enable clear"]
431pub type FLEXCOMM3_TX_W<'a, const O: u8> =
432 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM3_TX_A, O>;
433impl<'a, const O: u8> FLEXCOMM3_TX_W<'a, O> {
434 #[doc = "No effect"]
435 #[inline(always)]
436 pub fn flexcomm3_tx_1(self) -> &'a mut W {
437 self.variant(FLEXCOMM3_TX_A::FLEXCOMM3_TX_1)
438 }
439 #[doc = "Clears the ENA0 Bit"]
440 #[inline(always)]
441 pub fn flexcomm3_tx_0(self) -> &'a mut W {
442 self.variant(FLEXCOMM3_TX_A::FLEXCOMM3_TX_0)
443 }
444}
445#[doc = "Field `FLEXCOMM4_RX` reader - FLEXCOMM4 RX enable clear"]
446pub type FLEXCOMM4_RX_R = crate::BitReader<FLEXCOMM4_RX_A>;
447#[doc = "FLEXCOMM4 RX enable clear\n\nValue on reset: 0"]
448#[derive(Clone, Copy, Debug, PartialEq, Eq)]
449pub enum FLEXCOMM4_RX_A {
450 #[doc = "0: No effect"]
451 FLEXCOMM4_RX_0 = 0,
452 #[doc = "1: Clears the ENA0 Bit"]
453 FLEXCOMM4_RX_1 = 1,
454}
455impl From<FLEXCOMM4_RX_A> for bool {
456 #[inline(always)]
457 fn from(variant: FLEXCOMM4_RX_A) -> Self {
458 variant as u8 != 0
459 }
460}
461impl FLEXCOMM4_RX_R {
462 #[doc = "Get enumerated values variant"]
463 #[inline(always)]
464 pub fn variant(&self) -> FLEXCOMM4_RX_A {
465 match self.bits {
466 false => FLEXCOMM4_RX_A::FLEXCOMM4_RX_0,
467 true => FLEXCOMM4_RX_A::FLEXCOMM4_RX_1,
468 }
469 }
470 #[doc = "Checks if the value of the field is `FLEXCOMM4_RX_0`"]
471 #[inline(always)]
472 pub fn is_flexcomm4_rx_0(&self) -> bool {
473 *self == FLEXCOMM4_RX_A::FLEXCOMM4_RX_0
474 }
475 #[doc = "Checks if the value of the field is `FLEXCOMM4_RX_1`"]
476 #[inline(always)]
477 pub fn is_flexcomm4_rx_1(&self) -> bool {
478 *self == FLEXCOMM4_RX_A::FLEXCOMM4_RX_1
479 }
480}
481#[doc = "Field `FLEXCOMM4_RX` writer - FLEXCOMM4 RX enable clear"]
482pub type FLEXCOMM4_RX_W<'a, const O: u8> =
483 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM4_RX_A, O>;
484impl<'a, const O: u8> FLEXCOMM4_RX_W<'a, O> {
485 #[doc = "No effect"]
486 #[inline(always)]
487 pub fn flexcomm4_rx_0(self) -> &'a mut W {
488 self.variant(FLEXCOMM4_RX_A::FLEXCOMM4_RX_0)
489 }
490 #[doc = "Clears the ENA0 Bit"]
491 #[inline(always)]
492 pub fn flexcomm4_rx_1(self) -> &'a mut W {
493 self.variant(FLEXCOMM4_RX_A::FLEXCOMM4_RX_1)
494 }
495}
496#[doc = "Field `FLEXCOMM4_TX` reader - FLEXCOMM4 TX enable clear"]
497pub type FLEXCOMM4_TX_R = crate::BitReader<FLEXCOMM4_TX_A>;
498#[doc = "FLEXCOMM4 TX enable clear\n\nValue on reset: 0"]
499#[derive(Clone, Copy, Debug, PartialEq, Eq)]
500pub enum FLEXCOMM4_TX_A {
501 #[doc = "0: No effect"]
502 FLEXCOMM4_TX_0 = 0,
503 #[doc = "1: Clears the ENA0 Bit"]
504 FLEXCOMM4_TX_1 = 1,
505}
506impl From<FLEXCOMM4_TX_A> for bool {
507 #[inline(always)]
508 fn from(variant: FLEXCOMM4_TX_A) -> Self {
509 variant as u8 != 0
510 }
511}
512impl FLEXCOMM4_TX_R {
513 #[doc = "Get enumerated values variant"]
514 #[inline(always)]
515 pub fn variant(&self) -> FLEXCOMM4_TX_A {
516 match self.bits {
517 false => FLEXCOMM4_TX_A::FLEXCOMM4_TX_0,
518 true => FLEXCOMM4_TX_A::FLEXCOMM4_TX_1,
519 }
520 }
521 #[doc = "Checks if the value of the field is `FLEXCOMM4_TX_0`"]
522 #[inline(always)]
523 pub fn is_flexcomm4_tx_0(&self) -> bool {
524 *self == FLEXCOMM4_TX_A::FLEXCOMM4_TX_0
525 }
526 #[doc = "Checks if the value of the field is `FLEXCOMM4_TX_1`"]
527 #[inline(always)]
528 pub fn is_flexcomm4_tx_1(&self) -> bool {
529 *self == FLEXCOMM4_TX_A::FLEXCOMM4_TX_1
530 }
531}
532#[doc = "Field `FLEXCOMM4_TX` writer - FLEXCOMM4 TX enable clear"]
533pub type FLEXCOMM4_TX_W<'a, const O: u8> =
534 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM4_TX_A, O>;
535impl<'a, const O: u8> FLEXCOMM4_TX_W<'a, O> {
536 #[doc = "No effect"]
537 #[inline(always)]
538 pub fn flexcomm4_tx_0(self) -> &'a mut W {
539 self.variant(FLEXCOMM4_TX_A::FLEXCOMM4_TX_0)
540 }
541 #[doc = "Clears the ENA0 Bit"]
542 #[inline(always)]
543 pub fn flexcomm4_tx_1(self) -> &'a mut W {
544 self.variant(FLEXCOMM4_TX_A::FLEXCOMM4_TX_1)
545 }
546}
547#[doc = "Field `FLEXCOMM5_RX` reader - FLEXCOMM5 RX enable clear"]
548pub type FLEXCOMM5_RX_R = crate::BitReader<FLEXCOMM5_RX_A>;
549#[doc = "FLEXCOMM5 RX enable clear\n\nValue on reset: 0"]
550#[derive(Clone, Copy, Debug, PartialEq, Eq)]
551pub enum FLEXCOMM5_RX_A {
552 #[doc = "0: No effect"]
553 FLEXCOMM5_RX_0 = 0,
554 #[doc = "1: Clears the ENA0 Bit"]
555 FLEXCOMM5_RX_1 = 1,
556}
557impl From<FLEXCOMM5_RX_A> for bool {
558 #[inline(always)]
559 fn from(variant: FLEXCOMM5_RX_A) -> Self {
560 variant as u8 != 0
561 }
562}
563impl FLEXCOMM5_RX_R {
564 #[doc = "Get enumerated values variant"]
565 #[inline(always)]
566 pub fn variant(&self) -> FLEXCOMM5_RX_A {
567 match self.bits {
568 false => FLEXCOMM5_RX_A::FLEXCOMM5_RX_0,
569 true => FLEXCOMM5_RX_A::FLEXCOMM5_RX_1,
570 }
571 }
572 #[doc = "Checks if the value of the field is `FLEXCOMM5_RX_0`"]
573 #[inline(always)]
574 pub fn is_flexcomm5_rx_0(&self) -> bool {
575 *self == FLEXCOMM5_RX_A::FLEXCOMM5_RX_0
576 }
577 #[doc = "Checks if the value of the field is `FLEXCOMM5_RX_1`"]
578 #[inline(always)]
579 pub fn is_flexcomm5_rx_1(&self) -> bool {
580 *self == FLEXCOMM5_RX_A::FLEXCOMM5_RX_1
581 }
582}
583#[doc = "Field `FLEXCOMM5_RX` writer - FLEXCOMM5 RX enable clear"]
584pub type FLEXCOMM5_RX_W<'a, const O: u8> =
585 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM5_RX_A, O>;
586impl<'a, const O: u8> FLEXCOMM5_RX_W<'a, O> {
587 #[doc = "No effect"]
588 #[inline(always)]
589 pub fn flexcomm5_rx_0(self) -> &'a mut W {
590 self.variant(FLEXCOMM5_RX_A::FLEXCOMM5_RX_0)
591 }
592 #[doc = "Clears the ENA0 Bit"]
593 #[inline(always)]
594 pub fn flexcomm5_rx_1(self) -> &'a mut W {
595 self.variant(FLEXCOMM5_RX_A::FLEXCOMM5_RX_1)
596 }
597}
598#[doc = "Field `FLEXCOMM5_TX` reader - FLEXCOMM5 TX enable clear"]
599pub type FLEXCOMM5_TX_R = crate::BitReader<FLEXCOMM5_TX_A>;
600#[doc = "FLEXCOMM5 TX enable clear\n\nValue on reset: 0"]
601#[derive(Clone, Copy, Debug, PartialEq, Eq)]
602pub enum FLEXCOMM5_TX_A {
603 #[doc = "0: No effect"]
604 FLEXCOMM5_TX_0 = 0,
605 #[doc = "1: Clears the ENA0 Bit"]
606 FLEXCOMM5_TX_1 = 1,
607}
608impl From<FLEXCOMM5_TX_A> for bool {
609 #[inline(always)]
610 fn from(variant: FLEXCOMM5_TX_A) -> Self {
611 variant as u8 != 0
612 }
613}
614impl FLEXCOMM5_TX_R {
615 #[doc = "Get enumerated values variant"]
616 #[inline(always)]
617 pub fn variant(&self) -> FLEXCOMM5_TX_A {
618 match self.bits {
619 false => FLEXCOMM5_TX_A::FLEXCOMM5_TX_0,
620 true => FLEXCOMM5_TX_A::FLEXCOMM5_TX_1,
621 }
622 }
623 #[doc = "Checks if the value of the field is `FLEXCOMM5_TX_0`"]
624 #[inline(always)]
625 pub fn is_flexcomm5_tx_0(&self) -> bool {
626 *self == FLEXCOMM5_TX_A::FLEXCOMM5_TX_0
627 }
628 #[doc = "Checks if the value of the field is `FLEXCOMM5_TX_1`"]
629 #[inline(always)]
630 pub fn is_flexcomm5_tx_1(&self) -> bool {
631 *self == FLEXCOMM5_TX_A::FLEXCOMM5_TX_1
632 }
633}
634#[doc = "Field `FLEXCOMM5_TX` writer - FLEXCOMM5 TX enable clear"]
635pub type FLEXCOMM5_TX_W<'a, const O: u8> =
636 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM5_TX_A, O>;
637impl<'a, const O: u8> FLEXCOMM5_TX_W<'a, O> {
638 #[doc = "No effect"]
639 #[inline(always)]
640 pub fn flexcomm5_tx_0(self) -> &'a mut W {
641 self.variant(FLEXCOMM5_TX_A::FLEXCOMM5_TX_0)
642 }
643 #[doc = "Clears the ENA0 Bit"]
644 #[inline(always)]
645 pub fn flexcomm5_tx_1(self) -> &'a mut W {
646 self.variant(FLEXCOMM5_TX_A::FLEXCOMM5_TX_1)
647 }
648}
649#[doc = "Field `FLEXCOMM6_RX` reader - FLEXCOMM6 RX enable"]
650pub type FLEXCOMM6_RX_R = crate::BitReader<FLEXCOMM6_RX_A>;
651#[doc = "FLEXCOMM6 RX enable\n\nValue on reset: 0"]
652#[derive(Clone, Copy, Debug, PartialEq, Eq)]
653pub enum FLEXCOMM6_RX_A {
654 #[doc = "0: No effect"]
655 FLEXCOMM6_RX_0 = 0,
656 #[doc = "1: Clears the ENA0 Bit"]
657 FLEXCOMM6_RX_1 = 1,
658}
659impl From<FLEXCOMM6_RX_A> for bool {
660 #[inline(always)]
661 fn from(variant: FLEXCOMM6_RX_A) -> Self {
662 variant as u8 != 0
663 }
664}
665impl FLEXCOMM6_RX_R {
666 #[doc = "Get enumerated values variant"]
667 #[inline(always)]
668 pub fn variant(&self) -> FLEXCOMM6_RX_A {
669 match self.bits {
670 false => FLEXCOMM6_RX_A::FLEXCOMM6_RX_0,
671 true => FLEXCOMM6_RX_A::FLEXCOMM6_RX_1,
672 }
673 }
674 #[doc = "Checks if the value of the field is `FLEXCOMM6_RX_0`"]
675 #[inline(always)]
676 pub fn is_flexcomm6_rx_0(&self) -> bool {
677 *self == FLEXCOMM6_RX_A::FLEXCOMM6_RX_0
678 }
679 #[doc = "Checks if the value of the field is `FLEXCOMM6_RX_1`"]
680 #[inline(always)]
681 pub fn is_flexcomm6_rx_1(&self) -> bool {
682 *self == FLEXCOMM6_RX_A::FLEXCOMM6_RX_1
683 }
684}
685#[doc = "Field `FLEXCOMM6_RX` writer - FLEXCOMM6 RX enable"]
686pub type FLEXCOMM6_RX_W<'a, const O: u8> =
687 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM6_RX_A, O>;
688impl<'a, const O: u8> FLEXCOMM6_RX_W<'a, O> {
689 #[doc = "No effect"]
690 #[inline(always)]
691 pub fn flexcomm6_rx_0(self) -> &'a mut W {
692 self.variant(FLEXCOMM6_RX_A::FLEXCOMM6_RX_0)
693 }
694 #[doc = "Clears the ENA0 Bit"]
695 #[inline(always)]
696 pub fn flexcomm6_rx_1(self) -> &'a mut W {
697 self.variant(FLEXCOMM6_RX_A::FLEXCOMM6_RX_1)
698 }
699}
700#[doc = "Field `FLEXCOMM6_TX` reader - FLEXCOMM6 TX enable"]
701pub type FLEXCOMM6_TX_R = crate::BitReader<FLEXCOMM6_TX_A>;
702#[doc = "FLEXCOMM6 TX enable\n\nValue on reset: 0"]
703#[derive(Clone, Copy, Debug, PartialEq, Eq)]
704pub enum FLEXCOMM6_TX_A {
705 #[doc = "0: No effect"]
706 FLEXCOMM6_TX_0 = 0,
707 #[doc = "1: Clears the ENA0 Bit"]
708 FLEXCOMM6_TX_1 = 1,
709}
710impl From<FLEXCOMM6_TX_A> for bool {
711 #[inline(always)]
712 fn from(variant: FLEXCOMM6_TX_A) -> Self {
713 variant as u8 != 0
714 }
715}
716impl FLEXCOMM6_TX_R {
717 #[doc = "Get enumerated values variant"]
718 #[inline(always)]
719 pub fn variant(&self) -> FLEXCOMM6_TX_A {
720 match self.bits {
721 false => FLEXCOMM6_TX_A::FLEXCOMM6_TX_0,
722 true => FLEXCOMM6_TX_A::FLEXCOMM6_TX_1,
723 }
724 }
725 #[doc = "Checks if the value of the field is `FLEXCOMM6_TX_0`"]
726 #[inline(always)]
727 pub fn is_flexcomm6_tx_0(&self) -> bool {
728 *self == FLEXCOMM6_TX_A::FLEXCOMM6_TX_0
729 }
730 #[doc = "Checks if the value of the field is `FLEXCOMM6_TX_1`"]
731 #[inline(always)]
732 pub fn is_flexcomm6_tx_1(&self) -> bool {
733 *self == FLEXCOMM6_TX_A::FLEXCOMM6_TX_1
734 }
735}
736#[doc = "Field `FLEXCOMM6_TX` writer - FLEXCOMM6 TX enable"]
737pub type FLEXCOMM6_TX_W<'a, const O: u8> =
738 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM6_TX_A, O>;
739impl<'a, const O: u8> FLEXCOMM6_TX_W<'a, O> {
740 #[doc = "No effect"]
741 #[inline(always)]
742 pub fn flexcomm6_tx_0(self) -> &'a mut W {
743 self.variant(FLEXCOMM6_TX_A::FLEXCOMM6_TX_0)
744 }
745 #[doc = "Clears the ENA0 Bit"]
746 #[inline(always)]
747 pub fn flexcomm6_tx_1(self) -> &'a mut W {
748 self.variant(FLEXCOMM6_TX_A::FLEXCOMM6_TX_1)
749 }
750}
751#[doc = "Field `FLEXCOMM7_RX` reader - FLEXCOMM7 RX enable"]
752pub type FLEXCOMM7_RX_R = crate::BitReader<FLEXCOMM7_RX_A>;
753#[doc = "FLEXCOMM7 RX enable\n\nValue on reset: 0"]
754#[derive(Clone, Copy, Debug, PartialEq, Eq)]
755pub enum FLEXCOMM7_RX_A {
756 #[doc = "0: No effect"]
757 FLEXCOMM5_RX_0 = 0,
758 #[doc = "1: Clears the ENA0 Bit"]
759 FLEXCOMM5_RX_1 = 1,
760}
761impl From<FLEXCOMM7_RX_A> for bool {
762 #[inline(always)]
763 fn from(variant: FLEXCOMM7_RX_A) -> Self {
764 variant as u8 != 0
765 }
766}
767impl FLEXCOMM7_RX_R {
768 #[doc = "Get enumerated values variant"]
769 #[inline(always)]
770 pub fn variant(&self) -> FLEXCOMM7_RX_A {
771 match self.bits {
772 false => FLEXCOMM7_RX_A::FLEXCOMM5_RX_0,
773 true => FLEXCOMM7_RX_A::FLEXCOMM5_RX_1,
774 }
775 }
776 #[doc = "Checks if the value of the field is `FLEXCOMM5_RX_0`"]
777 #[inline(always)]
778 pub fn is_flexcomm5_rx_0(&self) -> bool {
779 *self == FLEXCOMM7_RX_A::FLEXCOMM5_RX_0
780 }
781 #[doc = "Checks if the value of the field is `FLEXCOMM5_RX_1`"]
782 #[inline(always)]
783 pub fn is_flexcomm5_rx_1(&self) -> bool {
784 *self == FLEXCOMM7_RX_A::FLEXCOMM5_RX_1
785 }
786}
787#[doc = "Field `FLEXCOMM7_RX` writer - FLEXCOMM7 RX enable"]
788pub type FLEXCOMM7_RX_W<'a, const O: u8> =
789 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM7_RX_A, O>;
790impl<'a, const O: u8> FLEXCOMM7_RX_W<'a, O> {
791 #[doc = "No effect"]
792 #[inline(always)]
793 pub fn flexcomm5_rx_0(self) -> &'a mut W {
794 self.variant(FLEXCOMM7_RX_A::FLEXCOMM5_RX_0)
795 }
796 #[doc = "Clears the ENA0 Bit"]
797 #[inline(always)]
798 pub fn flexcomm5_rx_1(self) -> &'a mut W {
799 self.variant(FLEXCOMM7_RX_A::FLEXCOMM5_RX_1)
800 }
801}
802#[doc = "Field `FLEXCOMM7_TX` reader - FLEXCOMM7 TX enable"]
803pub type FLEXCOMM7_TX_R = crate::BitReader<FLEXCOMM7_TX_A>;
804#[doc = "FLEXCOMM7 TX enable\n\nValue on reset: 0"]
805#[derive(Clone, Copy, Debug, PartialEq, Eq)]
806pub enum FLEXCOMM7_TX_A {
807 #[doc = "0: No effect"]
808 FLEXCOMM7_TX_0 = 0,
809 #[doc = "1: Clears the ENA0 Bit"]
810 FLEXCOMM7_TX_1 = 1,
811}
812impl From<FLEXCOMM7_TX_A> for bool {
813 #[inline(always)]
814 fn from(variant: FLEXCOMM7_TX_A) -> Self {
815 variant as u8 != 0
816 }
817}
818impl FLEXCOMM7_TX_R {
819 #[doc = "Get enumerated values variant"]
820 #[inline(always)]
821 pub fn variant(&self) -> FLEXCOMM7_TX_A {
822 match self.bits {
823 false => FLEXCOMM7_TX_A::FLEXCOMM7_TX_0,
824 true => FLEXCOMM7_TX_A::FLEXCOMM7_TX_1,
825 }
826 }
827 #[doc = "Checks if the value of the field is `FLEXCOMM7_TX_0`"]
828 #[inline(always)]
829 pub fn is_flexcomm7_tx_0(&self) -> bool {
830 *self == FLEXCOMM7_TX_A::FLEXCOMM7_TX_0
831 }
832 #[doc = "Checks if the value of the field is `FLEXCOMM7_TX_1`"]
833 #[inline(always)]
834 pub fn is_flexcomm7_tx_1(&self) -> bool {
835 *self == FLEXCOMM7_TX_A::FLEXCOMM7_TX_1
836 }
837}
838#[doc = "Field `FLEXCOMM7_TX` writer - FLEXCOMM7 TX enable"]
839pub type FLEXCOMM7_TX_W<'a, const O: u8> =
840 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM7_TX_A, O>;
841impl<'a, const O: u8> FLEXCOMM7_TX_W<'a, O> {
842 #[doc = "No effect"]
843 #[inline(always)]
844 pub fn flexcomm7_tx_0(self) -> &'a mut W {
845 self.variant(FLEXCOMM7_TX_A::FLEXCOMM7_TX_0)
846 }
847 #[doc = "Clears the ENA0 Bit"]
848 #[inline(always)]
849 pub fn flexcomm7_tx_1(self) -> &'a mut W {
850 self.variant(FLEXCOMM7_TX_A::FLEXCOMM7_TX_1)
851 }
852}
853#[doc = "Field `DMIC0_CH0_FLEXCOMM8_RX_DMA` reader - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable"]
854pub type DMIC0_CH0_FLEXCOMM8_RX_DMA_R = crate::BitReader<DMIC0_CH0_FLEXCOMM8_RX_DMA_A>;
855#[doc = "DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable\n\nValue on reset: 0"]
856#[derive(Clone, Copy, Debug, PartialEq, Eq)]
857pub enum DMIC0_CH0_FLEXCOMM8_RX_DMA_A {
858 #[doc = "0: No effect"]
859 DMIC0_CH0_FLEXCOMM8_RX_DMA_0 = 0,
860 #[doc = "1: Clears the ENA0 Bit"]
861 DMIC0_CH0_FLEXCOMM8_RX_DMA_1 = 1,
862}
863impl From<DMIC0_CH0_FLEXCOMM8_RX_DMA_A> for bool {
864 #[inline(always)]
865 fn from(variant: DMIC0_CH0_FLEXCOMM8_RX_DMA_A) -> Self {
866 variant as u8 != 0
867 }
868}
869impl DMIC0_CH0_FLEXCOMM8_RX_DMA_R {
870 #[doc = "Get enumerated values variant"]
871 #[inline(always)]
872 pub fn variant(&self) -> DMIC0_CH0_FLEXCOMM8_RX_DMA_A {
873 match self.bits {
874 false => DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_0,
875 true => DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_1,
876 }
877 }
878 #[doc = "Checks if the value of the field is `DMIC0_CH0_FLEXCOMM8_RX_DMA_0`"]
879 #[inline(always)]
880 pub fn is_dmic0_ch0_flexcomm8_rx_dma_0(&self) -> bool {
881 *self == DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_0
882 }
883 #[doc = "Checks if the value of the field is `DMIC0_CH0_FLEXCOMM8_RX_DMA_1`"]
884 #[inline(always)]
885 pub fn is_dmic0_ch0_flexcomm8_rx_dma_1(&self) -> bool {
886 *self == DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_1
887 }
888}
889#[doc = "Field `DMIC0_CH0_FLEXCOMM8_RX_DMA` writer - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable"]
890pub type DMIC0_CH0_FLEXCOMM8_RX_DMA_W<'a, const O: u8> =
891 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH0_FLEXCOMM8_RX_DMA_A, O>;
892impl<'a, const O: u8> DMIC0_CH0_FLEXCOMM8_RX_DMA_W<'a, O> {
893 #[doc = "No effect"]
894 #[inline(always)]
895 pub fn dmic0_ch0_flexcomm8_rx_dma_0(self) -> &'a mut W {
896 self.variant(DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_0)
897 }
898 #[doc = "Clears the ENA0 Bit"]
899 #[inline(always)]
900 pub fn dmic0_ch0_flexcomm8_rx_dma_1(self) -> &'a mut W {
901 self.variant(DMIC0_CH0_FLEXCOMM8_RX_DMA_A::DMIC0_CH0_FLEXCOMM8_RX_DMA_1)
902 }
903}
904#[doc = "Field `DMIC0_CH1_FLEXCOMM8_TX_DMA` reader - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable"]
905pub type DMIC0_CH1_FLEXCOMM8_TX_DMA_R = crate::BitReader<DMIC0_CH1_FLEXCOMM8_TX_DMA_A>;
906#[doc = "DMIC0 channel 1 / FLEXCOMM8 TX DMA enable\n\nValue on reset: 0"]
907#[derive(Clone, Copy, Debug, PartialEq, Eq)]
908pub enum DMIC0_CH1_FLEXCOMM8_TX_DMA_A {
909 #[doc = "0: No effect"]
910 DMIC0_CH1_FLEXCOMM8_TX_DMA_0 = 0,
911 #[doc = "1: Clears the ENA0 Bit"]
912 DMIC0_CH1_FLEXCOMM8_TX_DMA_1 = 1,
913}
914impl From<DMIC0_CH1_FLEXCOMM8_TX_DMA_A> for bool {
915 #[inline(always)]
916 fn from(variant: DMIC0_CH1_FLEXCOMM8_TX_DMA_A) -> Self {
917 variant as u8 != 0
918 }
919}
920impl DMIC0_CH1_FLEXCOMM8_TX_DMA_R {
921 #[doc = "Get enumerated values variant"]
922 #[inline(always)]
923 pub fn variant(&self) -> DMIC0_CH1_FLEXCOMM8_TX_DMA_A {
924 match self.bits {
925 false => DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_0,
926 true => DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_1,
927 }
928 }
929 #[doc = "Checks if the value of the field is `DMIC0_CH1_FLEXCOMM8_TX_DMA_0`"]
930 #[inline(always)]
931 pub fn is_dmic0_ch1_flexcomm8_tx_dma_0(&self) -> bool {
932 *self == DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_0
933 }
934 #[doc = "Checks if the value of the field is `DMIC0_CH1_FLEXCOMM8_TX_DMA_1`"]
935 #[inline(always)]
936 pub fn is_dmic0_ch1_flexcomm8_tx_dma_1(&self) -> bool {
937 *self == DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_1
938 }
939}
940#[doc = "Field `DMIC0_CH1_FLEXCOMM8_TX_DMA` writer - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable"]
941pub type DMIC0_CH1_FLEXCOMM8_TX_DMA_W<'a, const O: u8> =
942 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH1_FLEXCOMM8_TX_DMA_A, O>;
943impl<'a, const O: u8> DMIC0_CH1_FLEXCOMM8_TX_DMA_W<'a, O> {
944 #[doc = "No effect"]
945 #[inline(always)]
946 pub fn dmic0_ch1_flexcomm8_tx_dma_0(self) -> &'a mut W {
947 self.variant(DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_0)
948 }
949 #[doc = "Clears the ENA0 Bit"]
950 #[inline(always)]
951 pub fn dmic0_ch1_flexcomm8_tx_dma_1(self) -> &'a mut W {
952 self.variant(DMIC0_CH1_FLEXCOMM8_TX_DMA_A::DMIC0_CH1_FLEXCOMM8_TX_DMA_1)
953 }
954}
955#[doc = "Field `DMIC0_CH2_FLEXCOMM9_RX_DMA` reader - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable"]
956pub type DMIC0_CH2_FLEXCOMM9_RX_DMA_R = crate::BitReader<DMIC0_CH2_FLEXCOMM9_RX_DMA_A>;
957#[doc = "DMIC0 channel 2 / FLEXCOMM9 RX DMA enable\n\nValue on reset: 0"]
958#[derive(Clone, Copy, Debug, PartialEq, Eq)]
959pub enum DMIC0_CH2_FLEXCOMM9_RX_DMA_A {
960 #[doc = "0: No effect"]
961 DMIC0_CH2_FLEXCOMM9_RX_DMA_0 = 0,
962 #[doc = "1: Clears the ENA0 Bit"]
963 DMIC0_CH2_FLEXCOMM9_RX_DMA_1 = 1,
964}
965impl From<DMIC0_CH2_FLEXCOMM9_RX_DMA_A> for bool {
966 #[inline(always)]
967 fn from(variant: DMIC0_CH2_FLEXCOMM9_RX_DMA_A) -> Self {
968 variant as u8 != 0
969 }
970}
971impl DMIC0_CH2_FLEXCOMM9_RX_DMA_R {
972 #[doc = "Get enumerated values variant"]
973 #[inline(always)]
974 pub fn variant(&self) -> DMIC0_CH2_FLEXCOMM9_RX_DMA_A {
975 match self.bits {
976 false => DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_0,
977 true => DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_1,
978 }
979 }
980 #[doc = "Checks if the value of the field is `DMIC0_CH2_FLEXCOMM9_RX_DMA_0`"]
981 #[inline(always)]
982 pub fn is_dmic0_ch2_flexcomm9_rx_dma_0(&self) -> bool {
983 *self == DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_0
984 }
985 #[doc = "Checks if the value of the field is `DMIC0_CH2_FLEXCOMM9_RX_DMA_1`"]
986 #[inline(always)]
987 pub fn is_dmic0_ch2_flexcomm9_rx_dma_1(&self) -> bool {
988 *self == DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_1
989 }
990}
991#[doc = "Field `DMIC0_CH2_FLEXCOMM9_RX_DMA` writer - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable"]
992pub type DMIC0_CH2_FLEXCOMM9_RX_DMA_W<'a, const O: u8> =
993 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH2_FLEXCOMM9_RX_DMA_A, O>;
994impl<'a, const O: u8> DMIC0_CH2_FLEXCOMM9_RX_DMA_W<'a, O> {
995 #[doc = "No effect"]
996 #[inline(always)]
997 pub fn dmic0_ch2_flexcomm9_rx_dma_0(self) -> &'a mut W {
998 self.variant(DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_0)
999 }
1000 #[doc = "Clears the ENA0 Bit"]
1001 #[inline(always)]
1002 pub fn dmic0_ch2_flexcomm9_rx_dma_1(self) -> &'a mut W {
1003 self.variant(DMIC0_CH2_FLEXCOMM9_RX_DMA_A::DMIC0_CH2_FLEXCOMM9_RX_DMA_1)
1004 }
1005}
1006#[doc = "Field `DMIC0_CH3_FLEXCOMM9_TX_DMA` reader - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable"]
1007pub type DMIC0_CH3_FLEXCOMM9_TX_DMA_R = crate::BitReader<DMIC0_CH3_FLEXCOMM9_TX_DMA_A>;
1008#[doc = "DMIC0 channel 3 / FLEXCOMM9 TX DMA enable\n\nValue on reset: 0"]
1009#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1010pub enum DMIC0_CH3_FLEXCOMM9_TX_DMA_A {
1011 #[doc = "0: No effect"]
1012 DMIC0_CH3_FLEXCOMM9_TX_DMA_0 = 0,
1013 #[doc = "1: Clears the ENA0 Bit"]
1014 DMIC0_CH3_FLEXCOMM9_TX_DMA_1 = 1,
1015}
1016impl From<DMIC0_CH3_FLEXCOMM9_TX_DMA_A> for bool {
1017 #[inline(always)]
1018 fn from(variant: DMIC0_CH3_FLEXCOMM9_TX_DMA_A) -> Self {
1019 variant as u8 != 0
1020 }
1021}
1022impl DMIC0_CH3_FLEXCOMM9_TX_DMA_R {
1023 #[doc = "Get enumerated values variant"]
1024 #[inline(always)]
1025 pub fn variant(&self) -> DMIC0_CH3_FLEXCOMM9_TX_DMA_A {
1026 match self.bits {
1027 false => DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_0,
1028 true => DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_1,
1029 }
1030 }
1031 #[doc = "Checks if the value of the field is `DMIC0_CH3_FLEXCOMM9_TX_DMA_0`"]
1032 #[inline(always)]
1033 pub fn is_dmic0_ch3_flexcomm9_tx_dma_0(&self) -> bool {
1034 *self == DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_0
1035 }
1036 #[doc = "Checks if the value of the field is `DMIC0_CH3_FLEXCOMM9_TX_DMA_1`"]
1037 #[inline(always)]
1038 pub fn is_dmic0_ch3_flexcomm9_tx_dma_1(&self) -> bool {
1039 *self == DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_1
1040 }
1041}
1042#[doc = "Field `DMIC0_CH3_FLEXCOMM9_TX_DMA` writer - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable"]
1043pub type DMIC0_CH3_FLEXCOMM9_TX_DMA_W<'a, const O: u8> =
1044 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH3_FLEXCOMM9_TX_DMA_A, O>;
1045impl<'a, const O: u8> DMIC0_CH3_FLEXCOMM9_TX_DMA_W<'a, O> {
1046 #[doc = "No effect"]
1047 #[inline(always)]
1048 pub fn dmic0_ch3_flexcomm9_tx_dma_0(self) -> &'a mut W {
1049 self.variant(DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_0)
1050 }
1051 #[doc = "Clears the ENA0 Bit"]
1052 #[inline(always)]
1053 pub fn dmic0_ch3_flexcomm9_tx_dma_1(self) -> &'a mut W {
1054 self.variant(DMIC0_CH3_FLEXCOMM9_TX_DMA_A::DMIC0_CH3_FLEXCOMM9_TX_DMA_1)
1055 }
1056}
1057#[doc = "Field `DMIC0_CH4_FLEXCOMM10_RX_DMA` reader - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable"]
1058pub type DMIC0_CH4_FLEXCOMM10_RX_DMA_R = crate::BitReader<DMIC0_CH4_FLEXCOMM10_RX_DMA_A>;
1059#[doc = "DMIC0 channel 4 / FLEXCOMM10 RX DMA enable\n\nValue on reset: 0"]
1060#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1061pub enum DMIC0_CH4_FLEXCOMM10_RX_DMA_A {
1062 #[doc = "0: No effect"]
1063 DMIC0_CH4_FLEXCOMM10_RX_DMA_0 = 0,
1064 #[doc = "1: Clears the ENA0 Bit"]
1065 DMIC0_CH4_FLEXCOMM10_RX_DMA_1 = 1,
1066}
1067impl From<DMIC0_CH4_FLEXCOMM10_RX_DMA_A> for bool {
1068 #[inline(always)]
1069 fn from(variant: DMIC0_CH4_FLEXCOMM10_RX_DMA_A) -> Self {
1070 variant as u8 != 0
1071 }
1072}
1073impl DMIC0_CH4_FLEXCOMM10_RX_DMA_R {
1074 #[doc = "Get enumerated values variant"]
1075 #[inline(always)]
1076 pub fn variant(&self) -> DMIC0_CH4_FLEXCOMM10_RX_DMA_A {
1077 match self.bits {
1078 false => DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_0,
1079 true => DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_1,
1080 }
1081 }
1082 #[doc = "Checks if the value of the field is `DMIC0_CH4_FLEXCOMM10_RX_DMA_0`"]
1083 #[inline(always)]
1084 pub fn is_dmic0_ch4_flexcomm10_rx_dma_0(&self) -> bool {
1085 *self == DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_0
1086 }
1087 #[doc = "Checks if the value of the field is `DMIC0_CH4_FLEXCOMM10_RX_DMA_1`"]
1088 #[inline(always)]
1089 pub fn is_dmic0_ch4_flexcomm10_rx_dma_1(&self) -> bool {
1090 *self == DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_1
1091 }
1092}
1093#[doc = "Field `DMIC0_CH4_FLEXCOMM10_RX_DMA` writer - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable"]
1094pub type DMIC0_CH4_FLEXCOMM10_RX_DMA_W<'a, const O: u8> =
1095 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH4_FLEXCOMM10_RX_DMA_A, O>;
1096impl<'a, const O: u8> DMIC0_CH4_FLEXCOMM10_RX_DMA_W<'a, O> {
1097 #[doc = "No effect"]
1098 #[inline(always)]
1099 pub fn dmic0_ch4_flexcomm10_rx_dma_0(self) -> &'a mut W {
1100 self.variant(DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_0)
1101 }
1102 #[doc = "Clears the ENA0 Bit"]
1103 #[inline(always)]
1104 pub fn dmic0_ch4_flexcomm10_rx_dma_1(self) -> &'a mut W {
1105 self.variant(DMIC0_CH4_FLEXCOMM10_RX_DMA_A::DMIC0_CH4_FLEXCOMM10_RX_DMA_1)
1106 }
1107}
1108#[doc = "Field `DMIC0_CH5_FLEXCOMM10_TX_DMA` reader - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable"]
1109pub type DMIC0_CH5_FLEXCOMM10_TX_DMA_R = crate::BitReader<DMIC0_CH5_FLEXCOMM10_TX_DMA_A>;
1110#[doc = "DMIC0 channel 5 / FLEXCOMM10 TX DMA enable\n\nValue on reset: 0"]
1111#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1112pub enum DMIC0_CH5_FLEXCOMM10_TX_DMA_A {
1113 #[doc = "0: No effect"]
1114 DMIC0_CH5_FLEXCOMM10_TX_DMA_0 = 0,
1115 #[doc = "1: Clears the ENA0 Bit"]
1116 DMIC0_CH5_FLEXCOMM10_TX_DMA_1 = 1,
1117}
1118impl From<DMIC0_CH5_FLEXCOMM10_TX_DMA_A> for bool {
1119 #[inline(always)]
1120 fn from(variant: DMIC0_CH5_FLEXCOMM10_TX_DMA_A) -> Self {
1121 variant as u8 != 0
1122 }
1123}
1124impl DMIC0_CH5_FLEXCOMM10_TX_DMA_R {
1125 #[doc = "Get enumerated values variant"]
1126 #[inline(always)]
1127 pub fn variant(&self) -> DMIC0_CH5_FLEXCOMM10_TX_DMA_A {
1128 match self.bits {
1129 false => DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_0,
1130 true => DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_1,
1131 }
1132 }
1133 #[doc = "Checks if the value of the field is `DMIC0_CH5_FLEXCOMM10_TX_DMA_0`"]
1134 #[inline(always)]
1135 pub fn is_dmic0_ch5_flexcomm10_tx_dma_0(&self) -> bool {
1136 *self == DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_0
1137 }
1138 #[doc = "Checks if the value of the field is `DMIC0_CH5_FLEXCOMM10_TX_DMA_1`"]
1139 #[inline(always)]
1140 pub fn is_dmic0_ch5_flexcomm10_tx_dma_1(&self) -> bool {
1141 *self == DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_1
1142 }
1143}
1144#[doc = "Field `DMIC0_CH5_FLEXCOMM10_TX_DMA` writer - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable"]
1145pub type DMIC0_CH5_FLEXCOMM10_TX_DMA_W<'a, const O: u8> =
1146 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH5_FLEXCOMM10_TX_DMA_A, O>;
1147impl<'a, const O: u8> DMIC0_CH5_FLEXCOMM10_TX_DMA_W<'a, O> {
1148 #[doc = "No effect"]
1149 #[inline(always)]
1150 pub fn dmic0_ch5_flexcomm10_tx_dma_0(self) -> &'a mut W {
1151 self.variant(DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_0)
1152 }
1153 #[doc = "Clears the ENA0 Bit"]
1154 #[inline(always)]
1155 pub fn dmic0_ch5_flexcomm10_tx_dma_1(self) -> &'a mut W {
1156 self.variant(DMIC0_CH5_FLEXCOMM10_TX_DMA_A::DMIC0_CH5_FLEXCOMM10_TX_DMA_1)
1157 }
1158}
1159#[doc = "Field `DMIC0_CH6_FLEXCOMM13_RX_DMA` reader - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable"]
1160pub type DMIC0_CH6_FLEXCOMM13_RX_DMA_R = crate::BitReader<DMIC0_CH6_FLEXCOMM13_RX_DMA_A>;
1161#[doc = "DMIC0 channel 6 / FLEXCOMM13 RX DMA enable\n\nValue on reset: 0"]
1162#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1163pub enum DMIC0_CH6_FLEXCOMM13_RX_DMA_A {
1164 #[doc = "0: No effect"]
1165 DMIC0_CH6_FLEXCOMM13_RX_DMA_0 = 0,
1166 #[doc = "1: Clears the ENA0 Bit"]
1167 DMIC0_CH6_FLEXCOMM13_RX_DMA_1 = 1,
1168}
1169impl From<DMIC0_CH6_FLEXCOMM13_RX_DMA_A> for bool {
1170 #[inline(always)]
1171 fn from(variant: DMIC0_CH6_FLEXCOMM13_RX_DMA_A) -> Self {
1172 variant as u8 != 0
1173 }
1174}
1175impl DMIC0_CH6_FLEXCOMM13_RX_DMA_R {
1176 #[doc = "Get enumerated values variant"]
1177 #[inline(always)]
1178 pub fn variant(&self) -> DMIC0_CH6_FLEXCOMM13_RX_DMA_A {
1179 match self.bits {
1180 false => DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_0,
1181 true => DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_1,
1182 }
1183 }
1184 #[doc = "Checks if the value of the field is `DMIC0_CH6_FLEXCOMM13_RX_DMA_0`"]
1185 #[inline(always)]
1186 pub fn is_dmic0_ch6_flexcomm13_rx_dma_0(&self) -> bool {
1187 *self == DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_0
1188 }
1189 #[doc = "Checks if the value of the field is `DMIC0_CH6_FLEXCOMM13_RX_DMA_1`"]
1190 #[inline(always)]
1191 pub fn is_dmic0_ch6_flexcomm13_rx_dma_1(&self) -> bool {
1192 *self == DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_1
1193 }
1194}
1195#[doc = "Field `DMIC0_CH6_FLEXCOMM13_RX_DMA` writer - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable"]
1196pub type DMIC0_CH6_FLEXCOMM13_RX_DMA_W<'a, const O: u8> =
1197 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH6_FLEXCOMM13_RX_DMA_A, O>;
1198impl<'a, const O: u8> DMIC0_CH6_FLEXCOMM13_RX_DMA_W<'a, O> {
1199 #[doc = "No effect"]
1200 #[inline(always)]
1201 pub fn dmic0_ch6_flexcomm13_rx_dma_0(self) -> &'a mut W {
1202 self.variant(DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_0)
1203 }
1204 #[doc = "Clears the ENA0 Bit"]
1205 #[inline(always)]
1206 pub fn dmic0_ch6_flexcomm13_rx_dma_1(self) -> &'a mut W {
1207 self.variant(DMIC0_CH6_FLEXCOMM13_RX_DMA_A::DMIC0_CH6_FLEXCOMM13_RX_DMA_1)
1208 }
1209}
1210#[doc = "Field `DMIC0_CH7_FLEXCOMM13_TX_DMA` reader - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable"]
1211pub type DMIC0_CH7_FLEXCOMM13_TX_DMA_R = crate::BitReader<DMIC0_CH7_FLEXCOMM13_TX_DMA_A>;
1212#[doc = "DMIC0 channel 7 / FLEXCOMM13 TX DMA enable\n\nValue on reset: 0"]
1213#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1214pub enum DMIC0_CH7_FLEXCOMM13_TX_DMA_A {
1215 #[doc = "0: No effect"]
1216 DMIC0_CH7_FLEXCOMM13_TX_DMA_0 = 0,
1217 #[doc = "1: Clears the ENA0 Bit"]
1218 DMIC0_CH7_FLEXCOMM13_TX_DMA_1 = 1,
1219}
1220impl From<DMIC0_CH7_FLEXCOMM13_TX_DMA_A> for bool {
1221 #[inline(always)]
1222 fn from(variant: DMIC0_CH7_FLEXCOMM13_TX_DMA_A) -> Self {
1223 variant as u8 != 0
1224 }
1225}
1226impl DMIC0_CH7_FLEXCOMM13_TX_DMA_R {
1227 #[doc = "Get enumerated values variant"]
1228 #[inline(always)]
1229 pub fn variant(&self) -> DMIC0_CH7_FLEXCOMM13_TX_DMA_A {
1230 match self.bits {
1231 false => DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_0,
1232 true => DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_1,
1233 }
1234 }
1235 #[doc = "Checks if the value of the field is `DMIC0_CH7_FLEXCOMM13_TX_DMA_0`"]
1236 #[inline(always)]
1237 pub fn is_dmic0_ch7_flexcomm13_tx_dma_0(&self) -> bool {
1238 *self == DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_0
1239 }
1240 #[doc = "Checks if the value of the field is `DMIC0_CH7_FLEXCOMM13_TX_DMA_1`"]
1241 #[inline(always)]
1242 pub fn is_dmic0_ch7_flexcomm13_tx_dma_1(&self) -> bool {
1243 *self == DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_1
1244 }
1245}
1246#[doc = "Field `DMIC0_CH7_FLEXCOMM13_TX_DMA` writer - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable"]
1247pub type DMIC0_CH7_FLEXCOMM13_TX_DMA_W<'a, const O: u8> =
1248 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, DMIC0_CH7_FLEXCOMM13_TX_DMA_A, O>;
1249impl<'a, const O: u8> DMIC0_CH7_FLEXCOMM13_TX_DMA_W<'a, O> {
1250 #[doc = "No effect"]
1251 #[inline(always)]
1252 pub fn dmic0_ch7_flexcomm13_tx_dma_0(self) -> &'a mut W {
1253 self.variant(DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_0)
1254 }
1255 #[doc = "Clears the ENA0 Bit"]
1256 #[inline(always)]
1257 pub fn dmic0_ch7_flexcomm13_tx_dma_1(self) -> &'a mut W {
1258 self.variant(DMIC0_CH7_FLEXCOMM13_TX_DMA_A::DMIC0_CH7_FLEXCOMM13_TX_DMA_1)
1259 }
1260}
1261#[doc = "Field `I3C0_RX` reader - I3C RX enable clear"]
1262pub type I3C0_RX_R = crate::BitReader<I3C0_RX_A>;
1263#[doc = "I3C RX enable clear\n\nValue on reset: 0"]
1264#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1265pub enum I3C0_RX_A {
1266 #[doc = "0: No effect"]
1267 I3C0_RX_0 = 0,
1268 #[doc = "1: Clears the ENA0 Bit"]
1269 I3C0_RX_1 = 1,
1270}
1271impl From<I3C0_RX_A> for bool {
1272 #[inline(always)]
1273 fn from(variant: I3C0_RX_A) -> Self {
1274 variant as u8 != 0
1275 }
1276}
1277impl I3C0_RX_R {
1278 #[doc = "Get enumerated values variant"]
1279 #[inline(always)]
1280 pub fn variant(&self) -> I3C0_RX_A {
1281 match self.bits {
1282 false => I3C0_RX_A::I3C0_RX_0,
1283 true => I3C0_RX_A::I3C0_RX_1,
1284 }
1285 }
1286 #[doc = "Checks if the value of the field is `I3C0_RX_0`"]
1287 #[inline(always)]
1288 pub fn is_i3c0_rx_0(&self) -> bool {
1289 *self == I3C0_RX_A::I3C0_RX_0
1290 }
1291 #[doc = "Checks if the value of the field is `I3C0_RX_1`"]
1292 #[inline(always)]
1293 pub fn is_i3c0_rx_1(&self) -> bool {
1294 *self == I3C0_RX_A::I3C0_RX_1
1295 }
1296}
1297#[doc = "Field `I3C0_RX` writer - I3C RX enable clear"]
1298pub type I3C0_RX_W<'a, const O: u8> =
1299 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, I3C0_RX_A, O>;
1300impl<'a, const O: u8> I3C0_RX_W<'a, O> {
1301 #[doc = "No effect"]
1302 #[inline(always)]
1303 pub fn i3c0_rx_0(self) -> &'a mut W {
1304 self.variant(I3C0_RX_A::I3C0_RX_0)
1305 }
1306 #[doc = "Clears the ENA0 Bit"]
1307 #[inline(always)]
1308 pub fn i3c0_rx_1(self) -> &'a mut W {
1309 self.variant(I3C0_RX_A::I3C0_RX_1)
1310 }
1311}
1312#[doc = "Field `I3C0_TX` reader - I3C TX enable clear"]
1313pub type I3C0_TX_R = crate::BitReader<I3C0_TX_A>;
1314#[doc = "I3C TX enable clear\n\nValue on reset: 0"]
1315#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1316pub enum I3C0_TX_A {
1317 #[doc = "0: No effect"]
1318 I3C0_TX_0 = 0,
1319 #[doc = "1: Clears the ENA0 Bit"]
1320 I3C0_TX_1 = 1,
1321}
1322impl From<I3C0_TX_A> for bool {
1323 #[inline(always)]
1324 fn from(variant: I3C0_TX_A) -> Self {
1325 variant as u8 != 0
1326 }
1327}
1328impl I3C0_TX_R {
1329 #[doc = "Get enumerated values variant"]
1330 #[inline(always)]
1331 pub fn variant(&self) -> I3C0_TX_A {
1332 match self.bits {
1333 false => I3C0_TX_A::I3C0_TX_0,
1334 true => I3C0_TX_A::I3C0_TX_1,
1335 }
1336 }
1337 #[doc = "Checks if the value of the field is `I3C0_TX_0`"]
1338 #[inline(always)]
1339 pub fn is_i3c0_tx_0(&self) -> bool {
1340 *self == I3C0_TX_A::I3C0_TX_0
1341 }
1342 #[doc = "Checks if the value of the field is `I3C0_TX_1`"]
1343 #[inline(always)]
1344 pub fn is_i3c0_tx_1(&self) -> bool {
1345 *self == I3C0_TX_A::I3C0_TX_1
1346 }
1347}
1348#[doc = "Field `I3C0_TX` writer - I3C TX enable clear"]
1349pub type I3C0_TX_W<'a, const O: u8> =
1350 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, I3C0_TX_A, O>;
1351impl<'a, const O: u8> I3C0_TX_W<'a, O> {
1352 #[doc = "No effect"]
1353 #[inline(always)]
1354 pub fn i3c0_tx_0(self) -> &'a mut W {
1355 self.variant(I3C0_TX_A::I3C0_TX_0)
1356 }
1357 #[doc = "Clears the ENA0 Bit"]
1358 #[inline(always)]
1359 pub fn i3c0_tx_1(self) -> &'a mut W {
1360 self.variant(I3C0_TX_A::I3C0_TX_1)
1361 }
1362}
1363#[doc = "Field `FLEXCOMM14_RX` reader - FLEXCOMM14 RX enable clear"]
1364pub type FLEXCOMM14_RX_R = crate::BitReader<FLEXCOMM14_RX_A>;
1365#[doc = "FLEXCOMM14 RX enable clear\n\nValue on reset: 0"]
1366#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1367pub enum FLEXCOMM14_RX_A {
1368 #[doc = "0: No effect"]
1369 FLEXCOMM14_RX_0 = 0,
1370 #[doc = "1: Clears the ENA0 Bit"]
1371 FLEXCOMM14_RX_1 = 1,
1372}
1373impl From<FLEXCOMM14_RX_A> for bool {
1374 #[inline(always)]
1375 fn from(variant: FLEXCOMM14_RX_A) -> Self {
1376 variant as u8 != 0
1377 }
1378}
1379impl FLEXCOMM14_RX_R {
1380 #[doc = "Get enumerated values variant"]
1381 #[inline(always)]
1382 pub fn variant(&self) -> FLEXCOMM14_RX_A {
1383 match self.bits {
1384 false => FLEXCOMM14_RX_A::FLEXCOMM14_RX_0,
1385 true => FLEXCOMM14_RX_A::FLEXCOMM14_RX_1,
1386 }
1387 }
1388 #[doc = "Checks if the value of the field is `FLEXCOMM14_RX_0`"]
1389 #[inline(always)]
1390 pub fn is_flexcomm14_rx_0(&self) -> bool {
1391 *self == FLEXCOMM14_RX_A::FLEXCOMM14_RX_0
1392 }
1393 #[doc = "Checks if the value of the field is `FLEXCOMM14_RX_1`"]
1394 #[inline(always)]
1395 pub fn is_flexcomm14_rx_1(&self) -> bool {
1396 *self == FLEXCOMM14_RX_A::FLEXCOMM14_RX_1
1397 }
1398}
1399#[doc = "Field `FLEXCOMM14_RX` writer - FLEXCOMM14 RX enable clear"]
1400pub type FLEXCOMM14_RX_W<'a, const O: u8> =
1401 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM14_RX_A, O>;
1402impl<'a, const O: u8> FLEXCOMM14_RX_W<'a, O> {
1403 #[doc = "No effect"]
1404 #[inline(always)]
1405 pub fn flexcomm14_rx_0(self) -> &'a mut W {
1406 self.variant(FLEXCOMM14_RX_A::FLEXCOMM14_RX_0)
1407 }
1408 #[doc = "Clears the ENA0 Bit"]
1409 #[inline(always)]
1410 pub fn flexcomm14_rx_1(self) -> &'a mut W {
1411 self.variant(FLEXCOMM14_RX_A::FLEXCOMM14_RX_1)
1412 }
1413}
1414#[doc = "Field `FLEXCOMM14_TX` reader - FLEXCOMM14 TX enable clear"]
1415pub type FLEXCOMM14_TX_R = crate::BitReader<FLEXCOMM14_TX_A>;
1416#[doc = "FLEXCOMM14 TX enable clear\n\nValue on reset: 0"]
1417#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1418pub enum FLEXCOMM14_TX_A {
1419 #[doc = "0: No effect"]
1420 FLEXCOMM14_TX_0 = 0,
1421 #[doc = "1: Clears the ENA0 Bit"]
1422 FLEXCOMM14_TX_1 = 1,
1423}
1424impl From<FLEXCOMM14_TX_A> for bool {
1425 #[inline(always)]
1426 fn from(variant: FLEXCOMM14_TX_A) -> Self {
1427 variant as u8 != 0
1428 }
1429}
1430impl FLEXCOMM14_TX_R {
1431 #[doc = "Get enumerated values variant"]
1432 #[inline(always)]
1433 pub fn variant(&self) -> FLEXCOMM14_TX_A {
1434 match self.bits {
1435 false => FLEXCOMM14_TX_A::FLEXCOMM14_TX_0,
1436 true => FLEXCOMM14_TX_A::FLEXCOMM14_TX_1,
1437 }
1438 }
1439 #[doc = "Checks if the value of the field is `FLEXCOMM14_TX_0`"]
1440 #[inline(always)]
1441 pub fn is_flexcomm14_tx_0(&self) -> bool {
1442 *self == FLEXCOMM14_TX_A::FLEXCOMM14_TX_0
1443 }
1444 #[doc = "Checks if the value of the field is `FLEXCOMM14_TX_1`"]
1445 #[inline(always)]
1446 pub fn is_flexcomm14_tx_1(&self) -> bool {
1447 *self == FLEXCOMM14_TX_A::FLEXCOMM14_TX_1
1448 }
1449}
1450#[doc = "Field `FLEXCOMM14_TX` writer - FLEXCOMM14 TX enable clear"]
1451pub type FLEXCOMM14_TX_W<'a, const O: u8> =
1452 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM14_TX_A, O>;
1453impl<'a, const O: u8> FLEXCOMM14_TX_W<'a, O> {
1454 #[doc = "No effect"]
1455 #[inline(always)]
1456 pub fn flexcomm14_tx_0(self) -> &'a mut W {
1457 self.variant(FLEXCOMM14_TX_A::FLEXCOMM14_TX_0)
1458 }
1459 #[doc = "Clears the ENA0 Bit"]
1460 #[inline(always)]
1461 pub fn flexcomm14_tx_1(self) -> &'a mut W {
1462 self.variant(FLEXCOMM14_TX_A::FLEXCOMM14_TX_1)
1463 }
1464}
1465#[doc = "Field `FLEXCOMM16_RX` reader - FLEXCOMM16 RX enable"]
1466pub type FLEXCOMM16_RX_R = crate::BitReader<FLEXCOMM16_RX_A>;
1467#[doc = "FLEXCOMM16 RX enable\n\nValue on reset: 0"]
1468#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1469pub enum FLEXCOMM16_RX_A {
1470 #[doc = "0: No effect"]
1471 FLEXCOMM16_RX_0 = 0,
1472 #[doc = "1: Clears the ENA0 bit"]
1473 FLEXCOMM16_RX_1 = 1,
1474}
1475impl From<FLEXCOMM16_RX_A> for bool {
1476 #[inline(always)]
1477 fn from(variant: FLEXCOMM16_RX_A) -> Self {
1478 variant as u8 != 0
1479 }
1480}
1481impl FLEXCOMM16_RX_R {
1482 #[doc = "Get enumerated values variant"]
1483 #[inline(always)]
1484 pub fn variant(&self) -> FLEXCOMM16_RX_A {
1485 match self.bits {
1486 false => FLEXCOMM16_RX_A::FLEXCOMM16_RX_0,
1487 true => FLEXCOMM16_RX_A::FLEXCOMM16_RX_1,
1488 }
1489 }
1490 #[doc = "Checks if the value of the field is `FLEXCOMM16_RX_0`"]
1491 #[inline(always)]
1492 pub fn is_flexcomm16_rx_0(&self) -> bool {
1493 *self == FLEXCOMM16_RX_A::FLEXCOMM16_RX_0
1494 }
1495 #[doc = "Checks if the value of the field is `FLEXCOMM16_RX_1`"]
1496 #[inline(always)]
1497 pub fn is_flexcomm16_rx_1(&self) -> bool {
1498 *self == FLEXCOMM16_RX_A::FLEXCOMM16_RX_1
1499 }
1500}
1501#[doc = "Field `FLEXCOMM16_RX` writer - FLEXCOMM16 RX enable"]
1502pub type FLEXCOMM16_RX_W<'a, const O: u8> =
1503 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM16_RX_A, O>;
1504impl<'a, const O: u8> FLEXCOMM16_RX_W<'a, O> {
1505 #[doc = "No effect"]
1506 #[inline(always)]
1507 pub fn flexcomm16_rx_0(self) -> &'a mut W {
1508 self.variant(FLEXCOMM16_RX_A::FLEXCOMM16_RX_0)
1509 }
1510 #[doc = "Clears the ENA0 bit"]
1511 #[inline(always)]
1512 pub fn flexcomm16_rx_1(self) -> &'a mut W {
1513 self.variant(FLEXCOMM16_RX_A::FLEXCOMM16_RX_1)
1514 }
1515}
1516#[doc = "Field `FLEXCOMM16_TX` reader - FLEXCOMM16 TX enable"]
1517pub type FLEXCOMM16_TX_R = crate::BitReader<FLEXCOMM16_TX_A>;
1518#[doc = "FLEXCOMM16 TX enable\n\nValue on reset: 0"]
1519#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1520pub enum FLEXCOMM16_TX_A {
1521 #[doc = "0: No effect"]
1522 FLEXCOMM16_TX_0 = 0,
1523 #[doc = "1: Clears the ENA0 bit"]
1524 FLEXCOMM16_TX_1 = 1,
1525}
1526impl From<FLEXCOMM16_TX_A> for bool {
1527 #[inline(always)]
1528 fn from(variant: FLEXCOMM16_TX_A) -> Self {
1529 variant as u8 != 0
1530 }
1531}
1532impl FLEXCOMM16_TX_R {
1533 #[doc = "Get enumerated values variant"]
1534 #[inline(always)]
1535 pub fn variant(&self) -> FLEXCOMM16_TX_A {
1536 match self.bits {
1537 false => FLEXCOMM16_TX_A::FLEXCOMM16_TX_0,
1538 true => FLEXCOMM16_TX_A::FLEXCOMM16_TX_1,
1539 }
1540 }
1541 #[doc = "Checks if the value of the field is `FLEXCOMM16_TX_0`"]
1542 #[inline(always)]
1543 pub fn is_flexcomm16_tx_0(&self) -> bool {
1544 *self == FLEXCOMM16_TX_A::FLEXCOMM16_TX_0
1545 }
1546 #[doc = "Checks if the value of the field is `FLEXCOMM16_TX_1`"]
1547 #[inline(always)]
1548 pub fn is_flexcomm16_tx_1(&self) -> bool {
1549 *self == FLEXCOMM16_TX_A::FLEXCOMM16_TX_1
1550 }
1551}
1552#[doc = "Field `FLEXCOMM16_TX` writer - FLEXCOMM16 TX enable"]
1553pub type FLEXCOMM16_TX_W<'a, const O: u8> =
1554 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, FLEXCOMM16_TX_A, O>;
1555impl<'a, const O: u8> FLEXCOMM16_TX_W<'a, O> {
1556 #[doc = "No effect"]
1557 #[inline(always)]
1558 pub fn flexcomm16_tx_0(self) -> &'a mut W {
1559 self.variant(FLEXCOMM16_TX_A::FLEXCOMM16_TX_0)
1560 }
1561 #[doc = "Clears the ENA0 bit"]
1562 #[inline(always)]
1563 pub fn flexcomm16_tx_1(self) -> &'a mut W {
1564 self.variant(FLEXCOMM16_TX_A::FLEXCOMM16_TX_1)
1565 }
1566}
1567#[doc = "Field `I3C1_RX` reader - I3C1_RX enable"]
1568pub type I3C1_RX_R = crate::BitReader<I3C1_RX_A>;
1569#[doc = "I3C1_RX enable\n\nValue on reset: 0"]
1570#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1571pub enum I3C1_RX_A {
1572 #[doc = "0: No effect"]
1573 I3C1_RX_0 = 0,
1574 #[doc = "1: Clears the ENA0 bit"]
1575 I3C1_RX_1 = 1,
1576}
1577impl From<I3C1_RX_A> for bool {
1578 #[inline(always)]
1579 fn from(variant: I3C1_RX_A) -> Self {
1580 variant as u8 != 0
1581 }
1582}
1583impl I3C1_RX_R {
1584 #[doc = "Get enumerated values variant"]
1585 #[inline(always)]
1586 pub fn variant(&self) -> I3C1_RX_A {
1587 match self.bits {
1588 false => I3C1_RX_A::I3C1_RX_0,
1589 true => I3C1_RX_A::I3C1_RX_1,
1590 }
1591 }
1592 #[doc = "Checks if the value of the field is `I3C1_RX_0`"]
1593 #[inline(always)]
1594 pub fn is_i3c1_rx_0(&self) -> bool {
1595 *self == I3C1_RX_A::I3C1_RX_0
1596 }
1597 #[doc = "Checks if the value of the field is `I3C1_RX_1`"]
1598 #[inline(always)]
1599 pub fn is_i3c1_rx_1(&self) -> bool {
1600 *self == I3C1_RX_A::I3C1_RX_1
1601 }
1602}
1603#[doc = "Field `I3C1_RX` writer - I3C1_RX enable"]
1604pub type I3C1_RX_W<'a, const O: u8> =
1605 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, I3C1_RX_A, O>;
1606impl<'a, const O: u8> I3C1_RX_W<'a, O> {
1607 #[doc = "No effect"]
1608 #[inline(always)]
1609 pub fn i3c1_rx_0(self) -> &'a mut W {
1610 self.variant(I3C1_RX_A::I3C1_RX_0)
1611 }
1612 #[doc = "Clears the ENA0 bit"]
1613 #[inline(always)]
1614 pub fn i3c1_rx_1(self) -> &'a mut W {
1615 self.variant(I3C1_RX_A::I3C1_RX_1)
1616 }
1617}
1618#[doc = "Field `I3C1_TX` reader - I3C1_TX enable"]
1619pub type I3C1_TX_R = crate::BitReader<I3C1_TX_A>;
1620#[doc = "I3C1_TX enable\n\nValue on reset: 0"]
1621#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1622pub enum I3C1_TX_A {
1623 #[doc = "0: No effect"]
1624 I3C1_TX_0 = 0,
1625 #[doc = "1: Clears the ENA0 bit"]
1626 I3C1_TX_1 = 1,
1627}
1628impl From<I3C1_TX_A> for bool {
1629 #[inline(always)]
1630 fn from(variant: I3C1_TX_A) -> Self {
1631 variant as u8 != 0
1632 }
1633}
1634impl I3C1_TX_R {
1635 #[doc = "Get enumerated values variant"]
1636 #[inline(always)]
1637 pub fn variant(&self) -> I3C1_TX_A {
1638 match self.bits {
1639 false => I3C1_TX_A::I3C1_TX_0,
1640 true => I3C1_TX_A::I3C1_TX_1,
1641 }
1642 }
1643 #[doc = "Checks if the value of the field is `I3C1_TX_0`"]
1644 #[inline(always)]
1645 pub fn is_i3c1_tx_0(&self) -> bool {
1646 *self == I3C1_TX_A::I3C1_TX_0
1647 }
1648 #[doc = "Checks if the value of the field is `I3C1_TX_1`"]
1649 #[inline(always)]
1650 pub fn is_i3c1_tx_1(&self) -> bool {
1651 *self == I3C1_TX_A::I3C1_TX_1
1652 }
1653}
1654#[doc = "Field `I3C1_TX` writer - I3C1_TX enable"]
1655pub type I3C1_TX_W<'a, const O: u8> =
1656 crate::BitWriter<'a, u32, DMAC1_REQ_ENA0_CLR_SPEC, I3C1_TX_A, O>;
1657impl<'a, const O: u8> I3C1_TX_W<'a, O> {
1658 #[doc = "No effect"]
1659 #[inline(always)]
1660 pub fn i3c1_tx_0(self) -> &'a mut W {
1661 self.variant(I3C1_TX_A::I3C1_TX_0)
1662 }
1663 #[doc = "Clears the ENA0 bit"]
1664 #[inline(always)]
1665 pub fn i3c1_tx_1(self) -> &'a mut W {
1666 self.variant(I3C1_TX_A::I3C1_TX_1)
1667 }
1668}
1669impl R {
1670 #[doc = "Bit 0 - FLEXCOMM0 RX enable clear"]
1671 #[inline(always)]
1672 pub fn flexcomm0_rx(&self) -> FLEXCOMM0_RX_R {
1673 FLEXCOMM0_RX_R::new((self.bits & 1) != 0)
1674 }
1675 #[doc = "Bit 1 - FLEXCOMM0 TX enable clear"]
1676 #[inline(always)]
1677 pub fn flexcomm0_tx(&self) -> FLEXCOMM0_TX_R {
1678 FLEXCOMM0_TX_R::new(((self.bits >> 1) & 1) != 0)
1679 }
1680 #[doc = "Bit 2 - FLEXCOMM1 RX enable clear"]
1681 #[inline(always)]
1682 pub fn flexcomm1_rx(&self) -> FLEXCOMM1_RX_R {
1683 FLEXCOMM1_RX_R::new(((self.bits >> 2) & 1) != 0)
1684 }
1685 #[doc = "Bit 3 - FLEXCOMM1 TX enable clear"]
1686 #[inline(always)]
1687 pub fn flexcomm1_tx(&self) -> FLEXCOMM1_TX_R {
1688 FLEXCOMM1_TX_R::new(((self.bits >> 3) & 1) != 0)
1689 }
1690 #[doc = "Bit 4 - FLEXCOMM2 RX enable clear"]
1691 #[inline(always)]
1692 pub fn flexcomm2_rx(&self) -> FLEXCOMM2_RX_R {
1693 FLEXCOMM2_RX_R::new(((self.bits >> 4) & 1) != 0)
1694 }
1695 #[doc = "Bit 5 - FLEXCOMM2 TX enable clear"]
1696 #[inline(always)]
1697 pub fn flexcomm2_tx(&self) -> FLEXCOMM2_TX_R {
1698 FLEXCOMM2_TX_R::new(((self.bits >> 5) & 1) != 0)
1699 }
1700 #[doc = "Bit 6 - FLEXCOMM3 RX enable clear"]
1701 #[inline(always)]
1702 pub fn flexcomm3_rx(&self) -> FLEXCOMM3_RX_R {
1703 FLEXCOMM3_RX_R::new(((self.bits >> 6) & 1) != 0)
1704 }
1705 #[doc = "Bit 7 - FLEXCOMM3 TX enable clear"]
1706 #[inline(always)]
1707 pub fn flexcomm3_tx(&self) -> FLEXCOMM3_TX_R {
1708 FLEXCOMM3_TX_R::new(((self.bits >> 7) & 1) != 0)
1709 }
1710 #[doc = "Bit 8 - FLEXCOMM4 RX enable clear"]
1711 #[inline(always)]
1712 pub fn flexcomm4_rx(&self) -> FLEXCOMM4_RX_R {
1713 FLEXCOMM4_RX_R::new(((self.bits >> 8) & 1) != 0)
1714 }
1715 #[doc = "Bit 9 - FLEXCOMM4 TX enable clear"]
1716 #[inline(always)]
1717 pub fn flexcomm4_tx(&self) -> FLEXCOMM4_TX_R {
1718 FLEXCOMM4_TX_R::new(((self.bits >> 9) & 1) != 0)
1719 }
1720 #[doc = "Bit 10 - FLEXCOMM5 RX enable clear"]
1721 #[inline(always)]
1722 pub fn flexcomm5_rx(&self) -> FLEXCOMM5_RX_R {
1723 FLEXCOMM5_RX_R::new(((self.bits >> 10) & 1) != 0)
1724 }
1725 #[doc = "Bit 11 - FLEXCOMM5 TX enable clear"]
1726 #[inline(always)]
1727 pub fn flexcomm5_tx(&self) -> FLEXCOMM5_TX_R {
1728 FLEXCOMM5_TX_R::new(((self.bits >> 11) & 1) != 0)
1729 }
1730 #[doc = "Bit 12 - FLEXCOMM6 RX enable"]
1731 #[inline(always)]
1732 pub fn flexcomm6_rx(&self) -> FLEXCOMM6_RX_R {
1733 FLEXCOMM6_RX_R::new(((self.bits >> 12) & 1) != 0)
1734 }
1735 #[doc = "Bit 13 - FLEXCOMM6 TX enable"]
1736 #[inline(always)]
1737 pub fn flexcomm6_tx(&self) -> FLEXCOMM6_TX_R {
1738 FLEXCOMM6_TX_R::new(((self.bits >> 13) & 1) != 0)
1739 }
1740 #[doc = "Bit 14 - FLEXCOMM7 RX enable"]
1741 #[inline(always)]
1742 pub fn flexcomm7_rx(&self) -> FLEXCOMM7_RX_R {
1743 FLEXCOMM7_RX_R::new(((self.bits >> 14) & 1) != 0)
1744 }
1745 #[doc = "Bit 15 - FLEXCOMM7 TX enable"]
1746 #[inline(always)]
1747 pub fn flexcomm7_tx(&self) -> FLEXCOMM7_TX_R {
1748 FLEXCOMM7_TX_R::new(((self.bits >> 15) & 1) != 0)
1749 }
1750 #[doc = "Bit 16 - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable"]
1751 #[inline(always)]
1752 pub fn dmic0_ch0_flexcomm8_rx_dma(&self) -> DMIC0_CH0_FLEXCOMM8_RX_DMA_R {
1753 DMIC0_CH0_FLEXCOMM8_RX_DMA_R::new(((self.bits >> 16) & 1) != 0)
1754 }
1755 #[doc = "Bit 17 - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable"]
1756 #[inline(always)]
1757 pub fn dmic0_ch1_flexcomm8_tx_dma(&self) -> DMIC0_CH1_FLEXCOMM8_TX_DMA_R {
1758 DMIC0_CH1_FLEXCOMM8_TX_DMA_R::new(((self.bits >> 17) & 1) != 0)
1759 }
1760 #[doc = "Bit 18 - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable"]
1761 #[inline(always)]
1762 pub fn dmic0_ch2_flexcomm9_rx_dma(&self) -> DMIC0_CH2_FLEXCOMM9_RX_DMA_R {
1763 DMIC0_CH2_FLEXCOMM9_RX_DMA_R::new(((self.bits >> 18) & 1) != 0)
1764 }
1765 #[doc = "Bit 19 - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable"]
1766 #[inline(always)]
1767 pub fn dmic0_ch3_flexcomm9_tx_dma(&self) -> DMIC0_CH3_FLEXCOMM9_TX_DMA_R {
1768 DMIC0_CH3_FLEXCOMM9_TX_DMA_R::new(((self.bits >> 19) & 1) != 0)
1769 }
1770 #[doc = "Bit 20 - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable"]
1771 #[inline(always)]
1772 pub fn dmic0_ch4_flexcomm10_rx_dma(&self) -> DMIC0_CH4_FLEXCOMM10_RX_DMA_R {
1773 DMIC0_CH4_FLEXCOMM10_RX_DMA_R::new(((self.bits >> 20) & 1) != 0)
1774 }
1775 #[doc = "Bit 21 - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable"]
1776 #[inline(always)]
1777 pub fn dmic0_ch5_flexcomm10_tx_dma(&self) -> DMIC0_CH5_FLEXCOMM10_TX_DMA_R {
1778 DMIC0_CH5_FLEXCOMM10_TX_DMA_R::new(((self.bits >> 21) & 1) != 0)
1779 }
1780 #[doc = "Bit 22 - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable"]
1781 #[inline(always)]
1782 pub fn dmic0_ch6_flexcomm13_rx_dma(&self) -> DMIC0_CH6_FLEXCOMM13_RX_DMA_R {
1783 DMIC0_CH6_FLEXCOMM13_RX_DMA_R::new(((self.bits >> 22) & 1) != 0)
1784 }
1785 #[doc = "Bit 23 - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable"]
1786 #[inline(always)]
1787 pub fn dmic0_ch7_flexcomm13_tx_dma(&self) -> DMIC0_CH7_FLEXCOMM13_TX_DMA_R {
1788 DMIC0_CH7_FLEXCOMM13_TX_DMA_R::new(((self.bits >> 23) & 1) != 0)
1789 }
1790 #[doc = "Bit 24 - I3C RX enable clear"]
1791 #[inline(always)]
1792 pub fn i3c0_rx(&self) -> I3C0_RX_R {
1793 I3C0_RX_R::new(((self.bits >> 24) & 1) != 0)
1794 }
1795 #[doc = "Bit 25 - I3C TX enable clear"]
1796 #[inline(always)]
1797 pub fn i3c0_tx(&self) -> I3C0_TX_R {
1798 I3C0_TX_R::new(((self.bits >> 25) & 1) != 0)
1799 }
1800 #[doc = "Bit 26 - FLEXCOMM14 RX enable clear"]
1801 #[inline(always)]
1802 pub fn flexcomm14_rx(&self) -> FLEXCOMM14_RX_R {
1803 FLEXCOMM14_RX_R::new(((self.bits >> 26) & 1) != 0)
1804 }
1805 #[doc = "Bit 27 - FLEXCOMM14 TX enable clear"]
1806 #[inline(always)]
1807 pub fn flexcomm14_tx(&self) -> FLEXCOMM14_TX_R {
1808 FLEXCOMM14_TX_R::new(((self.bits >> 27) & 1) != 0)
1809 }
1810 #[doc = "Bit 28 - FLEXCOMM16 RX enable"]
1811 #[inline(always)]
1812 pub fn flexcomm16_rx(&self) -> FLEXCOMM16_RX_R {
1813 FLEXCOMM16_RX_R::new(((self.bits >> 28) & 1) != 0)
1814 }
1815 #[doc = "Bit 29 - FLEXCOMM16 TX enable"]
1816 #[inline(always)]
1817 pub fn flexcomm16_tx(&self) -> FLEXCOMM16_TX_R {
1818 FLEXCOMM16_TX_R::new(((self.bits >> 29) & 1) != 0)
1819 }
1820 #[doc = "Bit 30 - I3C1_RX enable"]
1821 #[inline(always)]
1822 pub fn i3c1_rx(&self) -> I3C1_RX_R {
1823 I3C1_RX_R::new(((self.bits >> 30) & 1) != 0)
1824 }
1825 #[doc = "Bit 31 - I3C1_TX enable"]
1826 #[inline(always)]
1827 pub fn i3c1_tx(&self) -> I3C1_TX_R {
1828 I3C1_TX_R::new(((self.bits >> 31) & 1) != 0)
1829 }
1830}
1831impl W {
1832 #[doc = "Bit 0 - FLEXCOMM0 RX enable clear"]
1833 #[inline(always)]
1834 #[must_use]
1835 pub fn flexcomm0_rx(&mut self) -> FLEXCOMM0_RX_W<0> {
1836 FLEXCOMM0_RX_W::new(self)
1837 }
1838 #[doc = "Bit 1 - FLEXCOMM0 TX enable clear"]
1839 #[inline(always)]
1840 #[must_use]
1841 pub fn flexcomm0_tx(&mut self) -> FLEXCOMM0_TX_W<1> {
1842 FLEXCOMM0_TX_W::new(self)
1843 }
1844 #[doc = "Bit 2 - FLEXCOMM1 RX enable clear"]
1845 #[inline(always)]
1846 #[must_use]
1847 pub fn flexcomm1_rx(&mut self) -> FLEXCOMM1_RX_W<2> {
1848 FLEXCOMM1_RX_W::new(self)
1849 }
1850 #[doc = "Bit 3 - FLEXCOMM1 TX enable clear"]
1851 #[inline(always)]
1852 #[must_use]
1853 pub fn flexcomm1_tx(&mut self) -> FLEXCOMM1_TX_W<3> {
1854 FLEXCOMM1_TX_W::new(self)
1855 }
1856 #[doc = "Bit 4 - FLEXCOMM2 RX enable clear"]
1857 #[inline(always)]
1858 #[must_use]
1859 pub fn flexcomm2_rx(&mut self) -> FLEXCOMM2_RX_W<4> {
1860 FLEXCOMM2_RX_W::new(self)
1861 }
1862 #[doc = "Bit 5 - FLEXCOMM2 TX enable clear"]
1863 #[inline(always)]
1864 #[must_use]
1865 pub fn flexcomm2_tx(&mut self) -> FLEXCOMM2_TX_W<5> {
1866 FLEXCOMM2_TX_W::new(self)
1867 }
1868 #[doc = "Bit 6 - FLEXCOMM3 RX enable clear"]
1869 #[inline(always)]
1870 #[must_use]
1871 pub fn flexcomm3_rx(&mut self) -> FLEXCOMM3_RX_W<6> {
1872 FLEXCOMM3_RX_W::new(self)
1873 }
1874 #[doc = "Bit 7 - FLEXCOMM3 TX enable clear"]
1875 #[inline(always)]
1876 #[must_use]
1877 pub fn flexcomm3_tx(&mut self) -> FLEXCOMM3_TX_W<7> {
1878 FLEXCOMM3_TX_W::new(self)
1879 }
1880 #[doc = "Bit 8 - FLEXCOMM4 RX enable clear"]
1881 #[inline(always)]
1882 #[must_use]
1883 pub fn flexcomm4_rx(&mut self) -> FLEXCOMM4_RX_W<8> {
1884 FLEXCOMM4_RX_W::new(self)
1885 }
1886 #[doc = "Bit 9 - FLEXCOMM4 TX enable clear"]
1887 #[inline(always)]
1888 #[must_use]
1889 pub fn flexcomm4_tx(&mut self) -> FLEXCOMM4_TX_W<9> {
1890 FLEXCOMM4_TX_W::new(self)
1891 }
1892 #[doc = "Bit 10 - FLEXCOMM5 RX enable clear"]
1893 #[inline(always)]
1894 #[must_use]
1895 pub fn flexcomm5_rx(&mut self) -> FLEXCOMM5_RX_W<10> {
1896 FLEXCOMM5_RX_W::new(self)
1897 }
1898 #[doc = "Bit 11 - FLEXCOMM5 TX enable clear"]
1899 #[inline(always)]
1900 #[must_use]
1901 pub fn flexcomm5_tx(&mut self) -> FLEXCOMM5_TX_W<11> {
1902 FLEXCOMM5_TX_W::new(self)
1903 }
1904 #[doc = "Bit 12 - FLEXCOMM6 RX enable"]
1905 #[inline(always)]
1906 #[must_use]
1907 pub fn flexcomm6_rx(&mut self) -> FLEXCOMM6_RX_W<12> {
1908 FLEXCOMM6_RX_W::new(self)
1909 }
1910 #[doc = "Bit 13 - FLEXCOMM6 TX enable"]
1911 #[inline(always)]
1912 #[must_use]
1913 pub fn flexcomm6_tx(&mut self) -> FLEXCOMM6_TX_W<13> {
1914 FLEXCOMM6_TX_W::new(self)
1915 }
1916 #[doc = "Bit 14 - FLEXCOMM7 RX enable"]
1917 #[inline(always)]
1918 #[must_use]
1919 pub fn flexcomm7_rx(&mut self) -> FLEXCOMM7_RX_W<14> {
1920 FLEXCOMM7_RX_W::new(self)
1921 }
1922 #[doc = "Bit 15 - FLEXCOMM7 TX enable"]
1923 #[inline(always)]
1924 #[must_use]
1925 pub fn flexcomm7_tx(&mut self) -> FLEXCOMM7_TX_W<15> {
1926 FLEXCOMM7_TX_W::new(self)
1927 }
1928 #[doc = "Bit 16 - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable"]
1929 #[inline(always)]
1930 #[must_use]
1931 pub fn dmic0_ch0_flexcomm8_rx_dma(&mut self) -> DMIC0_CH0_FLEXCOMM8_RX_DMA_W<16> {
1932 DMIC0_CH0_FLEXCOMM8_RX_DMA_W::new(self)
1933 }
1934 #[doc = "Bit 17 - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable"]
1935 #[inline(always)]
1936 #[must_use]
1937 pub fn dmic0_ch1_flexcomm8_tx_dma(&mut self) -> DMIC0_CH1_FLEXCOMM8_TX_DMA_W<17> {
1938 DMIC0_CH1_FLEXCOMM8_TX_DMA_W::new(self)
1939 }
1940 #[doc = "Bit 18 - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable"]
1941 #[inline(always)]
1942 #[must_use]
1943 pub fn dmic0_ch2_flexcomm9_rx_dma(&mut self) -> DMIC0_CH2_FLEXCOMM9_RX_DMA_W<18> {
1944 DMIC0_CH2_FLEXCOMM9_RX_DMA_W::new(self)
1945 }
1946 #[doc = "Bit 19 - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable"]
1947 #[inline(always)]
1948 #[must_use]
1949 pub fn dmic0_ch3_flexcomm9_tx_dma(&mut self) -> DMIC0_CH3_FLEXCOMM9_TX_DMA_W<19> {
1950 DMIC0_CH3_FLEXCOMM9_TX_DMA_W::new(self)
1951 }
1952 #[doc = "Bit 20 - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable"]
1953 #[inline(always)]
1954 #[must_use]
1955 pub fn dmic0_ch4_flexcomm10_rx_dma(&mut self) -> DMIC0_CH4_FLEXCOMM10_RX_DMA_W<20> {
1956 DMIC0_CH4_FLEXCOMM10_RX_DMA_W::new(self)
1957 }
1958 #[doc = "Bit 21 - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable"]
1959 #[inline(always)]
1960 #[must_use]
1961 pub fn dmic0_ch5_flexcomm10_tx_dma(&mut self) -> DMIC0_CH5_FLEXCOMM10_TX_DMA_W<21> {
1962 DMIC0_CH5_FLEXCOMM10_TX_DMA_W::new(self)
1963 }
1964 #[doc = "Bit 22 - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable"]
1965 #[inline(always)]
1966 #[must_use]
1967 pub fn dmic0_ch6_flexcomm13_rx_dma(&mut self) -> DMIC0_CH6_FLEXCOMM13_RX_DMA_W<22> {
1968 DMIC0_CH6_FLEXCOMM13_RX_DMA_W::new(self)
1969 }
1970 #[doc = "Bit 23 - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable"]
1971 #[inline(always)]
1972 #[must_use]
1973 pub fn dmic0_ch7_flexcomm13_tx_dma(&mut self) -> DMIC0_CH7_FLEXCOMM13_TX_DMA_W<23> {
1974 DMIC0_CH7_FLEXCOMM13_TX_DMA_W::new(self)
1975 }
1976 #[doc = "Bit 24 - I3C RX enable clear"]
1977 #[inline(always)]
1978 #[must_use]
1979 pub fn i3c0_rx(&mut self) -> I3C0_RX_W<24> {
1980 I3C0_RX_W::new(self)
1981 }
1982 #[doc = "Bit 25 - I3C TX enable clear"]
1983 #[inline(always)]
1984 #[must_use]
1985 pub fn i3c0_tx(&mut self) -> I3C0_TX_W<25> {
1986 I3C0_TX_W::new(self)
1987 }
1988 #[doc = "Bit 26 - FLEXCOMM14 RX enable clear"]
1989 #[inline(always)]
1990 #[must_use]
1991 pub fn flexcomm14_rx(&mut self) -> FLEXCOMM14_RX_W<26> {
1992 FLEXCOMM14_RX_W::new(self)
1993 }
1994 #[doc = "Bit 27 - FLEXCOMM14 TX enable clear"]
1995 #[inline(always)]
1996 #[must_use]
1997 pub fn flexcomm14_tx(&mut self) -> FLEXCOMM14_TX_W<27> {
1998 FLEXCOMM14_TX_W::new(self)
1999 }
2000 #[doc = "Bit 28 - FLEXCOMM16 RX enable"]
2001 #[inline(always)]
2002 #[must_use]
2003 pub fn flexcomm16_rx(&mut self) -> FLEXCOMM16_RX_W<28> {
2004 FLEXCOMM16_RX_W::new(self)
2005 }
2006 #[doc = "Bit 29 - FLEXCOMM16 TX enable"]
2007 #[inline(always)]
2008 #[must_use]
2009 pub fn flexcomm16_tx(&mut self) -> FLEXCOMM16_TX_W<29> {
2010 FLEXCOMM16_TX_W::new(self)
2011 }
2012 #[doc = "Bit 30 - I3C1_RX enable"]
2013 #[inline(always)]
2014 #[must_use]
2015 pub fn i3c1_rx(&mut self) -> I3C1_RX_W<30> {
2016 I3C1_RX_W::new(self)
2017 }
2018 #[doc = "Bit 31 - I3C1_TX enable"]
2019 #[inline(always)]
2020 #[must_use]
2021 pub fn i3c1_tx(&mut self) -> I3C1_TX_W<31> {
2022 I3C1_TX_W::new(self)
2023 }
2024 #[doc = "Writes raw bits to the register."]
2025 #[inline(always)]
2026 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2027 self.0.bits(bits);
2028 self
2029 }
2030}
2031#[doc = "DMAC1 request enable clear 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac1_req_ena0_clr](index.html) module"]
2032pub struct DMAC1_REQ_ENA0_CLR_SPEC;
2033impl crate::RegisterSpec for DMAC1_REQ_ENA0_CLR_SPEC {
2034 type Ux = u32;
2035}
2036#[doc = "`read()` method returns [dmac1_req_ena0_clr::R](R) reader structure"]
2037impl crate::Readable for DMAC1_REQ_ENA0_CLR_SPEC {
2038 type Reader = R;
2039}
2040#[doc = "`write(|w| ..)` method takes [dmac1_req_ena0_clr::W](W) writer structure"]
2041impl crate::Writable for DMAC1_REQ_ENA0_CLR_SPEC {
2042 type Writer = W;
2043 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
2044 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
2045}
2046#[doc = "`reset()` method sets DMAC1_REQ_ENA0_CLR to value 0"]
2047impl crate::Resettable for DMAC1_REQ_ENA0_CLR_SPEC {
2048 const RESET_VALUE: Self::Ux = 0;
2049}