mimxrt595s/clkctl1/
fc11fclksel.rs

1#[doc = "Register `FC11FCLKSEL` reader"]
2pub struct R(crate::R<FC11FCLKSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FC11FCLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FC11FCLKSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FC11FCLKSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FC11FCLKSEL` writer"]
17pub struct W(crate::W<FC11FCLKSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FC11FCLKSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FC11FCLKSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FC11FCLKSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SEL` reader - Flexcomm Functional Clock Source"]
38pub type SEL_R = crate::FieldReader<u8, SEL_A>;
39#[doc = "Flexcomm Functional Clock Source\n\nValue on reset: 7"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SEL_A {
43    #[doc = "0: FRO_DIV4 clock"]
44    FRRO_DIV4 = 0,
45    #[doc = "1: Audio PLL Clock"]
46    MASTER_CLOCK = 1,
47    #[doc = "7: None, output gated to reduce power"]
48    NONE = 7,
49}
50impl From<SEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: SEL_A) -> Self {
53        variant as _
54    }
55}
56impl SEL_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<SEL_A> {
60        match self.bits {
61            0 => Some(SEL_A::FRRO_DIV4),
62            1 => Some(SEL_A::MASTER_CLOCK),
63            7 => Some(SEL_A::NONE),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `FRRO_DIV4`"]
68    #[inline(always)]
69    pub fn is_frro_div4(&self) -> bool {
70        *self == SEL_A::FRRO_DIV4
71    }
72    #[doc = "Checks if the value of the field is `MASTER_CLOCK`"]
73    #[inline(always)]
74    pub fn is_master_clock(&self) -> bool {
75        *self == SEL_A::MASTER_CLOCK
76    }
77    #[doc = "Checks if the value of the field is `NONE`"]
78    #[inline(always)]
79    pub fn is_none(&self) -> bool {
80        *self == SEL_A::NONE
81    }
82}
83#[doc = "Field `SEL` writer - Flexcomm Functional Clock Source"]
84pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FC11FCLKSEL_SPEC, u8, SEL_A, 3, O>;
85impl<'a, const O: u8> SEL_W<'a, O> {
86    #[doc = "FRO_DIV4 clock"]
87    #[inline(always)]
88    pub fn frro_div4(self) -> &'a mut W {
89        self.variant(SEL_A::FRRO_DIV4)
90    }
91    #[doc = "Audio PLL Clock"]
92    #[inline(always)]
93    pub fn master_clock(self) -> &'a mut W {
94        self.variant(SEL_A::MASTER_CLOCK)
95    }
96    #[doc = "None, output gated to reduce power"]
97    #[inline(always)]
98    pub fn none(self) -> &'a mut W {
99        self.variant(SEL_A::NONE)
100    }
101}
102impl R {
103    #[doc = "Bits 0:2 - Flexcomm Functional Clock Source"]
104    #[inline(always)]
105    pub fn sel(&self) -> SEL_R {
106        SEL_R::new((self.bits & 7) as u8)
107    }
108}
109impl W {
110    #[doc = "Bits 0:2 - Flexcomm Functional Clock Source"]
111    #[inline(always)]
112    #[must_use]
113    pub fn sel(&mut self) -> SEL_W<0> {
114        SEL_W::new(self)
115    }
116    #[doc = "Writes raw bits to the register."]
117    #[inline(always)]
118    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
119        self.0.bits(bits);
120        self
121    }
122}
123#[doc = "Flexcomm11 Clock Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fc11fclksel](index.html) module"]
124pub struct FC11FCLKSEL_SPEC;
125impl crate::RegisterSpec for FC11FCLKSEL_SPEC {
126    type Ux = u32;
127}
128#[doc = "`read()` method returns [fc11fclksel::R](R) reader structure"]
129impl crate::Readable for FC11FCLKSEL_SPEC {
130    type Reader = R;
131}
132#[doc = "`write(|w| ..)` method takes [fc11fclksel::W](W) writer structure"]
133impl crate::Writable for FC11FCLKSEL_SPEC {
134    type Writer = W;
135    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
137}
138#[doc = "`reset()` method sets FC11FCLKSEL to value 0x07"]
139impl crate::Resettable for FC11FCLKSEL_SPEC {
140    const RESET_VALUE: Self::Ux = 0x07;
141}
mimxrt595s/clkctl1/fc11fclksel.rs

mimxrt595s/clkctl1/
fc11fclksel.rs
