mimxrt595_evk/
lib.rs

1//! A board support package for MIMXRT595-EVK, the official evaluation kit
2//! for the NXP i.MX RT500 family of microcontrollers.
3//!
4//! It also includes a `memory.x` file intended for inclusion into the linker
5//! script provided by crate `cortex-m-rt`.
6//!
7//! If you are building an application targeting this board, you will need to
8//! arrange for your flash image to contain a suitable flash control block
9//! and initial vector table so that the on-chip boot ROM will consider it
10//! eligable for use as boot media. You can get a default implementation of
11//! that by linking the separate crate `mimxrt595-evk-bootstub` into your
12//! program, or customize what's generated using the macros in crate
13//! `mimxrt500-bootstub`.
14#![no_std]
15
16/// The RT500 HAL crate, re-exported for convenience.
17pub use mimxrt500_hal as hal;
18
19/// Additional types used inside [`Pins`].
20pub mod pins;
21
22pub mod bootstub;
23
24/// Wraps the HAL-level Pins with alternative pin names that match the
25/// documented connections on the evaluation kit board.
26///
27/// Where possible the pins are grouped into nested structs based on the
28/// physical packages they are connected to, for convenience when passing all
29/// of the related pins together to a function that initializes a device driver.
30/// Some pins are connected to multiple on-board devices, so this categorization
31/// is not comprehensive.
32///
33/// To avoid emitting mode-setting code for pins that might never actually be
34/// used, the pins are still provided initially in unknown mode, and can then
35/// be converted into the appropriate mode by converting into one of the
36/// provided type aliases that specify the typical mode used for the device
37/// in question. For example, the following sets the red LED pin to be a GPIO
38/// output, with the `.into` method performing the mode change automatically:
39///
40/// ```rust
41/// let red_pin: mimxrt595_evk::pins::RgbLedRedPin = pins.rgb_led.red.into();
42/// ```
43pub struct Pins {
44    /// The pins connected to the on-board accelerometer chip.
45    pub accelerometer: pins::AccelerometerPins,
46
47    /// The pins connected to either of the on-board audio chips.
48    pub audio: pins::AudioPins,
49
50    /// The two pins connected to the "user buttons" at the top of the board,
51    /// as described in user guide section 8.8.
52    pub buttons: pins::UserButtonPins,
53
54    /// The pins connected to the "FlexIO" connector on the bottom of the board.
55    pub flex_io: pins::FlexIoPins,
56
57    /// The pins connected to the Link2 virtual COM port.
58    pub isp_uart: pins::IspUartPins,
59
60    /// The pins connected to both the MMC chip and the SD card socket.
61    pub mmc: pins::MmcPins,
62
63    /// The pins connected to the on-board PSRAM chip.
64    pub psram: pins::PsramPins,
65
66    /// The three pins connected to the on-board RGB LED, as described in
67    /// user guide section 8.7.
68    pub rgb_led: pins::RgbLedPins,
69}
70
71impl Pins {
72    /// Wrap the HAL-level pins object with the board-specific pins API.
73    #[inline(always)]
74    pub fn wrap(hal_pins: hal::gpio::Pins) -> Self {
75        Pins {
76            rgb_led: pins::RgbLedPins {
77                red: hal_pins.pio0_14,
78                green: hal_pins.pio1_0,
79                blue: hal_pins.pio3_17,
80            },
81            buttons: pins::UserButtonPins {
82                nmi: hal_pins.pio0_25,
83                irq: hal_pins.pio0_10,
84            },
85            accelerometer: pins::AccelerometerPins {
86                i2c_scl: hal_pins.pio0_29,
87                i2c_sda: hal_pins.pio0_30,
88                interrupt: hal_pins.pio0_22,
89            },
90            audio: pins::AudioPins {
91                i3c_sda: hal_pins.pio2_30,
92                i3c_scl: hal_pins.pio2_29,
93                i2s_bclk: hal_pins.pio0_7,
94                i2s_dai: hal_pins.pio0_9,
95                i2s_dao: hal_pins.pio0_23,
96                i2s_ws: hal_pins.pio0_8,
97                mclk: hal_pins.pio1_10,
98                alt_int: hal_pins.pio0_0,
99            },
100            flex_io: pins::FlexIoPins {
101                d0: hal_pins.pio4_20,
102                d1: hal_pins.pio4_21,
103                d2: hal_pins.pio4_22,
104                d3: hal_pins.pio4_23,
105                d4: hal_pins.pio4_24,
106                d5: hal_pins.pio4_25,
107                d6: hal_pins.pio4_26,
108                d7: hal_pins.pio4_27,
109                d8: hal_pins.pio4_28,
110                d9: hal_pins.pio4_29,
111                d10: hal_pins.pio4_30,
112                d11: hal_pins.pio4_31,
113                d12: hal_pins.pio5_0,
114                d13: hal_pins.pio5_1,
115                d14: hal_pins.pio5_2,
116                d15: hal_pins.pio5_3,
117            },
118            isp_uart: pins::IspUartPins {
119                txd: hal_pins.pio0_1,
120                rxd: hal_pins.pio0_2,
121                cts: hal_pins.pio0_3,
122                rts: hal_pins.pio0_4,
123            },
124            mmc: pins::MmcPins {
125                clk: hal_pins.pio1_30,
126                cmd: hal_pins.pio1_31,
127                d0: hal_pins.pio2_0,
128                d1: hal_pins.pio2_1,
129                d2: hal_pins.pio2_2,
130                d3: hal_pins.pio2_3,
131                d4: hal_pins.pio2_5,
132                d5: hal_pins.pio2_6,
133                d6: hal_pins.pio2_7,
134                d7: hal_pins.pio2_8,
135                sd_cd: hal_pins.pio2_9,
136                mmc_reset: hal_pins.pio2_10,
137                mmc_ds_sd_power_enable: hal_pins.pio2_4,
138            },
139            psram: pins::PsramPins {
140                cs: hal_pins.pio4_18,
141                reset: hal_pins.pio0_28,
142                sclk: hal_pins.pio4_11,
143                sclk_n: hal_pins.pio4_17,
144                dqs: hal_pins.pio4_16,
145                d0: hal_pins.pio4_12,
146                d1: hal_pins.pio4_13,
147                d2: hal_pins.pio4_14,
148                d3: hal_pins.pio4_15,
149                d4: hal_pins.pio5_15,
150                d5: hal_pins.pio5_16,
151                d6: hal_pins.pio5_17,
152                d7: hal_pins.pio5_18,
153            },
154        }
155    }
156}
157
158use mimxrt500_hal::bootrom::{
159    flexspi_lut_seq, FlexSpiDllTime, FlexSpiLutSeq, FlexSpiMemConfig, FlexSpiNorFlashConfig,
160    FlexspiLutCmd::*, FlexspiPad::*,
161};
162
163#[used]
164#[no_mangle]
165#[link_section = ".boot_hdr"]
166static NOR_FLASH_CONFIG: FlexSpiNorFlashConfig = FlexSpiNorFlashConfig {
167    mem_config: FlexSpiMemConfig {
168        tag: FlexSpiMemConfig::TAG,
169        version: FlexSpiMemConfig::VERSION,
170        reserved0: 0,
171        read_sample_clk_src: 3,
172        cs_hold_time: 3,
173        cs_setup_time: 3,
174        column_address_width: 0,
175        device_mode_cfg_enable: 1,
176        device_mode_type: 2,
177        wait_time_cfg_commands: 1,
178        device_mode_seq: FlexSpiLutSeq {
179            seq_num: 1,
180            seq_id: 6,
181            reserved: 0,
182        },
183        device_mode_arg: 2, // Enable OPI DDR mode
184        config_cmd_enable: 0,
185        config_mode_type: [0; 3],
186        config_cmd_seqs: [
187            FlexSpiLutSeq {
188                seq_num: 0,
189                seq_id: 0,
190                reserved: 0,
191            },
192            FlexSpiLutSeq {
193                seq_num: 0,
194                seq_id: 0,
195                reserved: 0,
196            },
197            FlexSpiLutSeq {
198                seq_num: 0,
199                seq_id: 0,
200                reserved: 0,
201            },
202        ],
203        reserved1: 0,
204        config_cmd_args: [0; 3],
205        reserved2: 0,
206        controller_misc_option: 0x50,
207        device_type: 0x01,
208        serial_flash_pad_type: 8,
209        serial_clk_freq: 3,
210        lut_custom_seq_enable: 0,
211        reserved3: [0; 2],
212        serial_flash_a1_size: 64 * 1024 * 1024,
213        serial_flash_a2_size: 0,
214        serial_flash_b1_size: 0,
215        serial_flash_b2_size: 0,
216        cs_pad_setting_override: 0,
217        sclk_pad_setting_override: 0,
218        data_pad_setting_override: 0,
219        dqs_pad_setting_override: 0,
220        timeout_in_ms: 0,
221        command_interval: 0,
222        data_valid_time: [FlexSpiDllTime {
223            delay_cells: 0,
224            time_100ps: 0,
225        }; 2],
226        busy_offset: 0,
227        busy_bit_polarity: 0,
228        lookup_table: [
229            // Read
230            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0xee, CMD_DDR, FLEXSPI_8PAD, 0x11),
231            flexspi_lut_seq(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),
232            flexspi_lut_seq(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),
233            0,
234            // Read status SPI
235            flexspi_lut_seq(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
236            0,
237            0,
238            0,
239            // Read status OPI
240            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xFA),
241            flexspi_lut_seq(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),
242            flexspi_lut_seq(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00),
243            0,
244            // Write enable
245            flexspi_lut_seq(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00),
246            0,
247            0,
248            0,
249            // Write enable - OPI
250            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9),
251            0,
252            0,
253            0,
254            // Erase Sector
255            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE),
256            flexspi_lut_seq(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),
257            0,
258            0,
259            // Enable OPI DDR mode
260            flexspi_lut_seq(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00),
261            flexspi_lut_seq(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00),
262            flexspi_lut_seq(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01),
263            0,
264            // Unused
265            0,
266            0,
267            0,
268            0,
269            // Erase block
270            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0xDC, CMD_DDR, FLEXSPI_8PAD, 0x23),
271            flexspi_lut_seq(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00),
272            0,
273            0,
274            // Page program
275            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED),
276            flexspi_lut_seq(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04),
277            0,
278            0,
279            // Unused
280            0,
281            0,
282            0,
283            0,
284            // Erase chip
285            flexspi_lut_seq(CMD_DDR, FLEXSPI_8PAD, 0x60, CMD_DDR, FLEXSPI_8PAD, 0x9F),
286            0,
287            0,
288            0,
289            // Remainder is unused
290            0,
291            0,
292            0,
293            0,
294            0,
295            0,
296            0,
297            0,
298            0,
299            0,
300            0,
301            0,
302            0,
303            0,
304            0,
305            0,
306        ],
307        lut_custom_seq: [FlexSpiLutSeq {
308            seq_num: 0,
309            seq_id: 0,
310            reserved: 0,
311        }; 12],
312        reserved4: [0; 4],
313    },
314    page_size: 256,
315    sector_size: 4096,
316    ip_cmd_serial_clk_freq: 1,
317    is_uniform_block_size: 0,
318    is_data_order_swapped: 0,
319    reserved0: [0; 1],
320    serial_nor_type: 2,
321    need_exit_no_cmd_mode: 0,
322    half_clk_for_non_read_cmd: 0,
323    need_restore_no_cmd_mode: 0,
324    block_size: 64 * 1024,
325    flash_state_ctx: 0x07008200,
326    reserved2: [0; 10],
327};
mimxrt595_evk/lib.rs

mimxrt595_evk/
lib.rs
