miden_processor/trace/chiplets/ace/
mod.rs1use alloc::collections::BTreeMap;
2
3use miden_air::trace::{RowIndex, chiplets::ace::ACE_CHIPLET_NUM_COLS};
4use miden_core::{Felt, field::PrimeCharacteristicRing};
5
6use crate::trace::ChipletTraceFragment;
7
8mod trace;
9pub use trace::CircuitEvaluation;
10
11mod instruction;
12#[cfg(test)]
13mod tests;
14
15pub const PTR_OFFSET_ELEM: Felt = Felt::ONE;
16pub const PTR_OFFSET_WORD: Felt = Felt::new_unchecked(4);
17pub const MAX_NUM_ACE_WIRES: u32 = instruction::MAX_ID;
18
19pub const MAX_EVAL_CIRCUIT_WIRES: u32 = 1 << 15;
24
25pub const MAX_EVAL_CIRCUIT_INVOCATIONS: u32 = 1 << 5;
30
31#[derive(Debug, Default)]
39pub struct Ace {
40 circuit_evaluations: BTreeMap<RowIndex, CircuitEvaluation>,
41}
42
43impl Ace {
44 pub(crate) fn trace_len(&self) -> usize {
46 self.circuit_evaluations.values().map(CircuitEvaluation::num_rows).sum()
47 }
48
49 pub(crate) fn fill_trace(self, trace: &mut ChipletTraceFragment) {
51 debug_assert_eq!(self.trace_len(), trace.len(), "inconsistent trace lengths");
53 debug_assert_eq!(ACE_CHIPLET_NUM_COLS, trace.width(), "inconsistent trace widths");
54
55 let mut gen_trace = Felt::zero_vec(self.trace_len() * ACE_CHIPLET_NUM_COLS);
57
58 let mut offset = 0;
59 for eval_ctx in self.circuit_evaluations.into_values() {
60 eval_ctx.fill(offset, &mut gen_trace);
61 offset += eval_ctx.num_rows();
62 }
63
64 trace.copy_rows_from(&gen_trace);
65 }
66
67 pub(crate) fn add_circuit_evaluation(
69 &mut self,
70 clk: RowIndex,
71 circuit_eval: CircuitEvaluation,
72 ) {
73 self.circuit_evaluations.insert(clk, circuit_eval);
74 }
75}