miden_processor/trace/chiplets/ace/
mod.rs1use alloc::collections::BTreeMap;
2
3use miden_air::trace::{RowIndex, chiplets::ace::ACE_CHIPLET_NUM_COLS};
4use miden_core::{Felt, field::PrimeCharacteristicRing};
5
6use crate::trace::ChipletTraceFragment;
7
8mod trace;
9pub use trace::CircuitEvaluation;
10
11mod instruction;
12#[cfg(test)]
13mod tests;
14
15pub const PTR_OFFSET_ELEM: Felt = Felt::ONE;
16pub const PTR_OFFSET_WORD: Felt = Felt::new_unchecked(4);
17pub const MAX_NUM_ACE_WIRES: u32 = instruction::MAX_ID;
18
19#[derive(Debug, Default)]
27pub struct Ace {
28 circuit_evaluations: BTreeMap<RowIndex, CircuitEvaluation>,
29}
30
31impl Ace {
32 pub(crate) fn trace_len(&self) -> usize {
34 self.circuit_evaluations.values().map(CircuitEvaluation::num_rows).sum()
35 }
36
37 pub(crate) fn fill_trace(self, trace: &mut ChipletTraceFragment) {
39 debug_assert_eq!(self.trace_len(), trace.len(), "inconsistent trace lengths");
41 debug_assert_eq!(ACE_CHIPLET_NUM_COLS, trace.width(), "inconsistent trace widths");
42
43 let mut gen_trace = Felt::zero_vec(self.trace_len() * ACE_CHIPLET_NUM_COLS);
45
46 let mut offset = 0;
47 for eval_ctx in self.circuit_evaluations.into_values() {
48 eval_ctx.fill(offset, &mut gen_trace);
49 offset += eval_ctx.num_rows();
50 }
51
52 trace.copy_rows_from(&gen_trace);
53 }
54
55 pub(crate) fn add_circuit_evaluation(
57 &mut self,
58 clk: RowIndex,
59 circuit_eval: CircuitEvaluation,
60 ) {
61 self.circuit_evaluations.insert(clk, circuit_eval);
62 }
63}