Expand description
Modules§
- acpi_
ec0 - adc
- asif
- bc_
link0 - cache
- cct
- cntr_
tmr0 - common
- dma_
chan00 - dma_
chan01 - dma_
chan02 - dma_
main - ec_
reg_ bank - ecia
- eeprom
- emi0
- espi_io
- espi_
memory - espi_
msvw00_ 06 - espi_
msvw07_ 10 - espi_
scratch - espi_
smvw00_ 10 - fan0
- fpu
- gcr
- gp_spi0
- gpio
- htm0
- imspi
- kbc
- kms
- led0
- mbx
- otp
- pcr
- peci
- phot
- pm1
- port92
- port_
80_ debug - powerguard_
0 - ps2_0
- pwm0
- qmspi
- rc_id0
- rtc
- rtos
- safbc_
cache - safbc_
ec - safcomm
- smb0
- spi_
slave - tach0
- tfdp
- timer16_
0 - timer32_
0 - uart0
- vbat
- vbat_
ram - vci
- wdt
- week
Enums§
- Buffer
Type - Pin buffer drive type.
- Dir
- Pin direction.
- Function
- Interrupt
- Pgs
- Power Gating Signals provide the chip Power Emulation options.
- Pol
- Pull
- Configure internal pull-up and pull-down resistors.
- Sel
- Slew
Ctrl - Strength
- interrupt
Constants§
- ACPI_
EC0 - The ACPI-ECI provides a four byte full duplex data interface.
- ACPI_
EC1 - ACPI_
EC2 - ACPI_
EC3 - ACPI_
EC4 - ADC
- This block is designed to convert external analog voltage readings into digital values.
- ASIF
- The ASIF allows the Host and EC to use index addressing to access registers residing in an external IC.
- BC_
LINK0 - This block provides BC-Link connectivity to a slave device. The BC-Link protocol includes a start bit to signal the beginning of a message and a turnaround (TAR) period for bus transfer between the Master and Companion devices.
- CACHE
- This is the CACHE Controller
- CCT
- This is a 16-bit auto-reloading timer/counter.
- CNTR_
TMR0 - This interface is a 16-bit auto-reloading timer/counter.
- CNTR_
TMR1 - CNTR_
TMR2 - CNTR_
TMR3 - DMA_
CHAN00 - DMA Channel 00 Registers
- DMA_
CHAN01 - DMA Channel 01 Registers
- DMA_
CHAN02 - DMA Channel 02 Registers
- DMA_
CHAN03 - DMA_
CHAN04 - DMA_
CHAN05 - DMA_
CHAN06 - DMA_
CHAN07 - DMA_
CHAN08 - DMA_
CHAN09 - DMA_
CHAN10 - DMA_
CHAN11 - DMA_
CHAN12 - DMA_
CHAN13 - DMA_
CHAN14 - DMA_
CHAN15 - DMA_
MAIN - DMA Main Registers
- ECIA
- The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
- EC_
REG_ BANK - This block is designed to be accessed internally by the EC via the register interface.
- EEPROM
- This block is the 2K x 8bit EEPROM.
- EMI0
- The EMI provides a communication between system host and Embedded Controller.
- EMI1
- EMI2
- ESPI_IO
- The ESPI is used by the system host to configure the chip and communicate with the logical devices implemented in the design.
- ESPI_
MEMORY - The eSPI Memory Component is one of two Logical Devices (along with the I/O Component) that provide access to all the registers in the device.
- ESPI_
MSVW00_ 06 - The Virtual Wire Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC.
- ESPI_
MSVW07_ 10 - The ESPI VW Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC.
- ESPI_
SCRATCH - 32 Byte ESPI Test Register
- ESPI_
SMVW00_ 10 - The ESPI VW Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC.
- FAN0
- The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors the fan’s speed and automatically adjusts the drive to maintain the desired fan speed. This RPM based Fan Control Algorithm controls a PWM output based on a tachometer input.
- FAN1
- FPU
- Floating Point Unit
- GCR
- The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
- GPIO
- GPIO Pin Control Registers
- GP_SPI0
- The General Purpose Serial Peripheral Interface (GP-SPI) may be used to communicate with various peripheral devices, e.g., EEPROMS, DACs, ADCs, that use a standard Serial Peripheral Interface.
- GP_SPI1
- HTM0
- The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode.
- HTM1
- IMSPI
- Internal Master SPI.
- KBC
- The Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042 behavior.
- KMS
- The Keyboard Scan Interface block provides a register interface to directly scan an external keyboard matrix of size up to 18x8.
- LED0
- The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
- LED1
- LED2
- LED3
- MBX
- The Mailbox provides a standard run-time mechanism for the host to communicate with the Embedded Controller (EC).
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority
- OTP
- OTP Programming registers.
- PCR
- The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip.
- PECI
- The PECI Interface allows the EC to retrieve temperature readings from PECI-compliant devices.
- PHOT
- This block monitors the PROCHOT# signal and designed to detect single assertions and monitor cumulative PROCHOT active time.
- PM1
- These features comply with the ACPI Specification through a combination of hardware and EC software.
- PORT92
- The registers listed in the Configuration Register Summary table are for a single instance of the Legacy Port92/GATEA20 logic.
- PORT_
80_ DEBUG - Diagnostic data is written by the Host Interface to the Port 80 BIOS Debug Port.
- POWERGUARD_
0 - This block monitors PowerGuard output signals (or locked rotor signals) from various types of fans, and determines their speed.
- POWERGUARD_
1 - PS2_0
- The four PS/2 Ports implementation eliminates the need to bit bang I/O ports to generate PS/2 traffic.
- PWM0
- The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz.
- PWM1
- PWM2
- PWM3
- PWM4
- PWM5
- PWM6
- PWM7
- PWM8
- PWM9
- PWM10
- PWM11
- QMSPI
- The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface.
- RC_ID0
- This interface provides a single pin interface which can discriminate a number of quantized RC constants.
- RC_ID1
- RC_ID2
- RTC
- This is the set of registers that are automatically counted by hardware every 1 second while the block is enabled.
- RTOS
- RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
- SAFBC_
CACHE - SAF BRIDGE CACHE INTERFACE
- SAFBC_
EC - SAF BRIDGE COMPONENT
- SAFCOMM
- This register contains one bit PREFETCH_EN that should be set to ‘1’ during initialization, to enable Prefetch Mode operation in SAFS Mode. Prefetch Mode allows overlapped anticipatory reading of information from Flash during the eSPI delivery of previously-read data to the Host Chipset. If enabled, Prefetching is invoked during consecutive Reads that are 64 bytes in length and from consecutive 64-byte aligned Flash addresses. With roughly equal clock rates on eSPI and SPI, these features together can approximately double the effective bandwidth of consecutive Flash reads performed over eSPI. In SAFS operation (SAF_MODE_ENABLE bit = 1) attempted accesses by EC firmware to this register are blocked.
- SMB0
- The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
- SMB1
- SMB2
- SMB3
- SMB4
- SPI_
SLAVE - SPI Slave Register.
- TACH0
- This block monitors TACH output signals from various types of fans, and determines their speed
- TACH1
- TACH2
- TACH3
- TFDP
- The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
- TIME
R16_ 0 - This 16-bit timer block offers a simple mechanism for firmware to maintain a time base.
- TIME
R16_ 1 - TIME
R16_ 2 - TIME
R16_ 3 - TIME
R32_ 0 - This 32-bit timer block offers a simple mechanism for firmware to maintain a time base.
- TIME
R32_ 1 - UART0
- The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
- UART1
- VBAT
- The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers.
- VBAT_
RAM - The VBAT RAM is operational while the main power rail is operational, and will retain its values powered by battery power while the main rail is unpowered.
- VCI
- The VBAT-Powered Control Interfaces with the RTC With Date and DST Adjustment as well as the Week Alarm.
- WDT
- The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
- WEEK
- The Week Timer and the Sub-Week Timer assert the Power-Up Event Output which automatically powers-up the system from the G3 state