Struct microbit::hal::pac::generic::W [−]
pub struct W<U, REG> { /* fields omitted */ }
Expand description
Implementations
impl<U, REG> W<U, REG>
impl<U, REG> W<U, REG>
impl W<u32, Reg<u32, _CUSTOMER>>
impl W<u32, Reg<u32, _CUSTOMER>>
pub fn customer(&mut self) -> CUSTOMER_W<'_>
pub fn customer(&mut self) -> CUSTOMER_W<'_>
Bits 0:31 - Reserved for customer
impl W<u32, Reg<u32, _DEBUGCTRL>>
impl W<u32, Reg<u32, _DEBUGCTRL>>
pub fn cpuniden(&mut self) -> CPUNIDEN_W<'_>
pub fn cpuniden(&mut self) -> CPUNIDEN_W<'_>
Bits 0:7 - Configure CPU non-intrusive debug features
pub fn cpufpben(&mut self) -> CPUFPBEN_W<'_>
pub fn cpufpben(&mut self) -> CPUFPBEN_W<'_>
Bits 8:15 - Configure CPU flash patch and breakpoint (FPB) unit behavior
impl W<u32, Reg<u32, _TASKS_HFCLKSTART>>
impl W<u32, Reg<u32, _TASKS_HFCLKSTART>>
pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W<'_>
pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W<'_>
Bit 0 - Start HFXO crystal oscillator
impl W<u32, Reg<u32, _TASKS_HFCLKSTOP>>
impl W<u32, Reg<u32, _TASKS_HFCLKSTOP>>
pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W<'_>
pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W<'_>
Bit 0 - Stop HFXO crystal oscillator
impl W<u32, Reg<u32, _TASKS_LFCLKSTART>>
impl W<u32, Reg<u32, _TASKS_LFCLKSTART>>
pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W<'_>
pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W<'_>
Bit 0 - Start LFCLK
impl W<u32, Reg<u32, _TASKS_LFCLKSTOP>>
impl W<u32, Reg<u32, _TASKS_LFCLKSTOP>>
pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W<'_>
pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W<'_>
Bit 0 - Stop LFCLK
impl W<u32, Reg<u32, _TASKS_CAL>>
impl W<u32, Reg<u32, _TASKS_CAL>>
pub fn tasks_cal(&mut self) -> TASKS_CAL_W<'_>
pub fn tasks_cal(&mut self) -> TASKS_CAL_W<'_>
Bit 0 - Start calibration of LFRC
impl W<u32, Reg<u32, _TASKS_CTSTART>>
impl W<u32, Reg<u32, _TASKS_CTSTART>>
pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W<'_>
pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W<'_>
Bit 0 - Start calibration timer
impl W<u32, Reg<u32, _TASKS_CTSTOP>>
impl W<u32, Reg<u32, _TASKS_CTSTOP>>
pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W<'_>
pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W<'_>
Bit 0 - Stop calibration timer
impl W<u32, Reg<u32, _EVENTS_HFCLKSTARTED>>
impl W<u32, Reg<u32, _EVENTS_HFCLKSTARTED>>
pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W<'_>
pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W<'_>
Bit 0 - HFXO crystal oscillator started
impl W<u32, Reg<u32, _EVENTS_LFCLKSTARTED>>
impl W<u32, Reg<u32, _EVENTS_LFCLKSTARTED>>
pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W<'_>
pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W<'_>
Bit 0 - LFCLK started
impl W<u32, Reg<u32, _EVENTS_DONE>>
impl W<u32, Reg<u32, _EVENTS_DONE>>
pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>
pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>
Bit 0 - Calibration of LFRC completed
impl W<u32, Reg<u32, _EVENTS_CTTO>>
impl W<u32, Reg<u32, _EVENTS_CTTO>>
pub fn events_ctto(&mut self) -> EVENTS_CTTO_W<'_>
pub fn events_ctto(&mut self) -> EVENTS_CTTO_W<'_>
Bit 0 - Calibration timer timeout
impl W<u32, Reg<u32, _EVENTS_CTSTARTED>>
impl W<u32, Reg<u32, _EVENTS_CTSTARTED>>
pub fn events_ctstarted(&mut self) -> EVENTS_CTSTARTED_W<'_>
pub fn events_ctstarted(&mut self) -> EVENTS_CTSTARTED_W<'_>
Bit 0 - Calibration timer has been started and is ready to process new tasks
impl W<u32, Reg<u32, _EVENTS_CTSTOPPED>>
impl W<u32, Reg<u32, _EVENTS_CTSTOPPED>>
pub fn events_ctstopped(&mut self) -> EVENTS_CTSTOPPED_W<'_>
pub fn events_ctstopped(&mut self) -> EVENTS_CTSTOPPED_W<'_>
Bit 0 - Calibration timer has been stopped and is ready to process new tasks
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event HFCLKSTARTED
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event LFCLKSTARTED
pub fn ctstarted(&mut self) -> CTSTARTED_W<'_>
pub fn ctstarted(&mut self) -> CTSTARTED_W<'_>
Bit 10 - Write ‘1’ to enable interrupt for event CTSTARTED
pub fn ctstopped(&mut self) -> CTSTOPPED_W<'_>
pub fn ctstopped(&mut self) -> CTSTOPPED_W<'_>
Bit 11 - Write ‘1’ to enable interrupt for event CTSTOPPED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event HFCLKSTARTED
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event LFCLKSTARTED
pub fn ctstarted(&mut self) -> CTSTARTED_W<'_>
pub fn ctstarted(&mut self) -> CTSTARTED_W<'_>
Bit 10 - Write ‘1’ to disable interrupt for event CTSTARTED
pub fn ctstopped(&mut self) -> CTSTOPPED_W<'_>
pub fn ctstopped(&mut self) -> CTSTOPPED_W<'_>
Bit 11 - Write ‘1’ to disable interrupt for event CTSTOPPED
impl W<u32, Reg<u32, _HFXODEBOUNCE>>
impl W<u32, Reg<u32, _HFXODEBOUNCE>>
pub fn hfxodebounce(&mut self) -> HFXODEBOUNCE_W<'_>
pub fn hfxodebounce(&mut self) -> HFXODEBOUNCE_W<'_>
Bits 0:7 - HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
impl W<u32, Reg<u32, _LFXODEBOUNCE>>
impl W<u32, Reg<u32, _LFXODEBOUNCE>>
pub fn lfxodebounce(&mut self) -> LFXODEBOUNCE_W<'_>
pub fn lfxodebounce(&mut self) -> LFXODEBOUNCE_W<'_>
Bit 0 - LFXO debounce time.
impl W<u32, Reg<u32, _TRACECONFIG>>
impl W<u32, Reg<u32, _TRACECONFIG>>
pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<'_>
pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<'_>
Bits 0:1 - Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.
pub fn tracemux(&mut self) -> TRACEMUX_W<'_>
pub fn tracemux(&mut self) -> TRACEMUX_W<'_>
Bits 16:17 - Pin multiplexing of trace signals. See pin assignment chapter for more details.
impl W<u32, Reg<u32, _POWER>>
impl W<u32, Reg<u32, _POWER>>
pub fn s10power(&mut self) -> S10POWER_W<'_>
pub fn s10power(&mut self) -> S10POWER_W<'_>
Bit 10 - Keep RAM section S10 on or off in System ON mode.
pub fn s11power(&mut self) -> S11POWER_W<'_>
pub fn s11power(&mut self) -> S11POWER_W<'_>
Bit 11 - Keep RAM section S11 on or off in System ON mode.
pub fn s12power(&mut self) -> S12POWER_W<'_>
pub fn s12power(&mut self) -> S12POWER_W<'_>
Bit 12 - Keep RAM section S12 on or off in System ON mode.
pub fn s13power(&mut self) -> S13POWER_W<'_>
pub fn s13power(&mut self) -> S13POWER_W<'_>
Bit 13 - Keep RAM section S13 on or off in System ON mode.
pub fn s14power(&mut self) -> S14POWER_W<'_>
pub fn s14power(&mut self) -> S14POWER_W<'_>
Bit 14 - Keep RAM section S14 on or off in System ON mode.
pub fn s15power(&mut self) -> S15POWER_W<'_>
pub fn s15power(&mut self) -> S15POWER_W<'_>
Bit 15 - Keep RAM section S15 on or off in System ON mode.
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
Bit 16 - Keep retention on RAM section S0 when RAM section is off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
Bit 17 - Keep retention on RAM section S1 when RAM section is off
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
Bit 18 - Keep retention on RAM section S2 when RAM section is off
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
Bit 19 - Keep retention on RAM section S3 when RAM section is off
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
Bit 20 - Keep retention on RAM section S4 when RAM section is off
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
Bit 21 - Keep retention on RAM section S5 when RAM section is off
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
Bit 22 - Keep retention on RAM section S6 when RAM section is off
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
Bit 23 - Keep retention on RAM section S7 when RAM section is off
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
Bit 24 - Keep retention on RAM section S8 when RAM section is off
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
Bit 25 - Keep retention on RAM section S9 when RAM section is off
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
Bit 26 - Keep retention on RAM section S10 when RAM section is off
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
Bit 27 - Keep retention on RAM section S11 when RAM section is off
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
Bit 28 - Keep retention on RAM section S12 when RAM section is off
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
Bit 29 - Keep retention on RAM section S13 when RAM section is off
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
Bit 30 - Keep retention on RAM section S14 when RAM section is off
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
Bit 31 - Keep retention on RAM section S15 when RAM section is off
impl W<u32, Reg<u32, _POWERSET>>
impl W<u32, Reg<u32, _POWERSET>>
pub fn s0power(&mut self) -> S0POWER_W<'_>
pub fn s0power(&mut self) -> S0POWER_W<'_>
Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
pub fn s1power(&mut self) -> S1POWER_W<'_>
Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode
pub fn s2power(&mut self) -> S2POWER_W<'_>
pub fn s2power(&mut self) -> S2POWER_W<'_>
Bit 2 - Keep RAM section S2 of RAMn on or off in System ON mode
pub fn s3power(&mut self) -> S3POWER_W<'_>
pub fn s3power(&mut self) -> S3POWER_W<'_>
Bit 3 - Keep RAM section S3 of RAMn on or off in System ON mode
pub fn s4power(&mut self) -> S4POWER_W<'_>
pub fn s4power(&mut self) -> S4POWER_W<'_>
Bit 4 - Keep RAM section S4 of RAMn on or off in System ON mode
pub fn s5power(&mut self) -> S5POWER_W<'_>
pub fn s5power(&mut self) -> S5POWER_W<'_>
Bit 5 - Keep RAM section S5 of RAMn on or off in System ON mode
pub fn s6power(&mut self) -> S6POWER_W<'_>
pub fn s6power(&mut self) -> S6POWER_W<'_>
Bit 6 - Keep RAM section S6 of RAMn on or off in System ON mode
pub fn s7power(&mut self) -> S7POWER_W<'_>
pub fn s7power(&mut self) -> S7POWER_W<'_>
Bit 7 - Keep RAM section S7 of RAMn on or off in System ON mode
pub fn s8power(&mut self) -> S8POWER_W<'_>
pub fn s8power(&mut self) -> S8POWER_W<'_>
Bit 8 - Keep RAM section S8 of RAMn on or off in System ON mode
pub fn s9power(&mut self) -> S9POWER_W<'_>
pub fn s9power(&mut self) -> S9POWER_W<'_>
Bit 9 - Keep RAM section S9 of RAMn on or off in System ON mode
pub fn s10power(&mut self) -> S10POWER_W<'_>
pub fn s10power(&mut self) -> S10POWER_W<'_>
Bit 10 - Keep RAM section S10 of RAMn on or off in System ON mode
pub fn s11power(&mut self) -> S11POWER_W<'_>
pub fn s11power(&mut self) -> S11POWER_W<'_>
Bit 11 - Keep RAM section S11 of RAMn on or off in System ON mode
pub fn s12power(&mut self) -> S12POWER_W<'_>
pub fn s12power(&mut self) -> S12POWER_W<'_>
Bit 12 - Keep RAM section S12 of RAMn on or off in System ON mode
pub fn s13power(&mut self) -> S13POWER_W<'_>
pub fn s13power(&mut self) -> S13POWER_W<'_>
Bit 13 - Keep RAM section S13 of RAMn on or off in System ON mode
pub fn s14power(&mut self) -> S14POWER_W<'_>
pub fn s14power(&mut self) -> S14POWER_W<'_>
Bit 14 - Keep RAM section S14 of RAMn on or off in System ON mode
pub fn s15power(&mut self) -> S15POWER_W<'_>
pub fn s15power(&mut self) -> S15POWER_W<'_>
Bit 15 - Keep RAM section S15 of RAMn on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
Bit 18 - Keep retention on RAM section S2 when RAM section is switched off
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
Bit 19 - Keep retention on RAM section S3 when RAM section is switched off
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
Bit 20 - Keep retention on RAM section S4 when RAM section is switched off
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
Bit 21 - Keep retention on RAM section S5 when RAM section is switched off
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
Bit 22 - Keep retention on RAM section S6 when RAM section is switched off
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
Bit 23 - Keep retention on RAM section S7 when RAM section is switched off
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
Bit 24 - Keep retention on RAM section S8 when RAM section is switched off
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
Bit 25 - Keep retention on RAM section S9 when RAM section is switched off
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
Bit 26 - Keep retention on RAM section S10 when RAM section is switched off
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
Bit 27 - Keep retention on RAM section S11 when RAM section is switched off
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
Bit 28 - Keep retention on RAM section S12 when RAM section is switched off
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
Bit 29 - Keep retention on RAM section S13 when RAM section is switched off
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
Bit 30 - Keep retention on RAM section S14 when RAM section is switched off
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
Bit 31 - Keep retention on RAM section S15 when RAM section is switched off
impl W<u32, Reg<u32, _POWERCLR>>
impl W<u32, Reg<u32, _POWERCLR>>
pub fn s0power(&mut self) -> S0POWER_W<'_>
pub fn s0power(&mut self) -> S0POWER_W<'_>
Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
pub fn s1power(&mut self) -> S1POWER_W<'_>
Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode
pub fn s2power(&mut self) -> S2POWER_W<'_>
pub fn s2power(&mut self) -> S2POWER_W<'_>
Bit 2 - Keep RAM section S2 of RAMn on or off in System ON mode
pub fn s3power(&mut self) -> S3POWER_W<'_>
pub fn s3power(&mut self) -> S3POWER_W<'_>
Bit 3 - Keep RAM section S3 of RAMn on or off in System ON mode
pub fn s4power(&mut self) -> S4POWER_W<'_>
pub fn s4power(&mut self) -> S4POWER_W<'_>
Bit 4 - Keep RAM section S4 of RAMn on or off in System ON mode
pub fn s5power(&mut self) -> S5POWER_W<'_>
pub fn s5power(&mut self) -> S5POWER_W<'_>
Bit 5 - Keep RAM section S5 of RAMn on or off in System ON mode
pub fn s6power(&mut self) -> S6POWER_W<'_>
pub fn s6power(&mut self) -> S6POWER_W<'_>
Bit 6 - Keep RAM section S6 of RAMn on or off in System ON mode
pub fn s7power(&mut self) -> S7POWER_W<'_>
pub fn s7power(&mut self) -> S7POWER_W<'_>
Bit 7 - Keep RAM section S7 of RAMn on or off in System ON mode
pub fn s8power(&mut self) -> S8POWER_W<'_>
pub fn s8power(&mut self) -> S8POWER_W<'_>
Bit 8 - Keep RAM section S8 of RAMn on or off in System ON mode
pub fn s9power(&mut self) -> S9POWER_W<'_>
pub fn s9power(&mut self) -> S9POWER_W<'_>
Bit 9 - Keep RAM section S9 of RAMn on or off in System ON mode
pub fn s10power(&mut self) -> S10POWER_W<'_>
pub fn s10power(&mut self) -> S10POWER_W<'_>
Bit 10 - Keep RAM section S10 of RAMn on or off in System ON mode
pub fn s11power(&mut self) -> S11POWER_W<'_>
pub fn s11power(&mut self) -> S11POWER_W<'_>
Bit 11 - Keep RAM section S11 of RAMn on or off in System ON mode
pub fn s12power(&mut self) -> S12POWER_W<'_>
pub fn s12power(&mut self) -> S12POWER_W<'_>
Bit 12 - Keep RAM section S12 of RAMn on or off in System ON mode
pub fn s13power(&mut self) -> S13POWER_W<'_>
pub fn s13power(&mut self) -> S13POWER_W<'_>
Bit 13 - Keep RAM section S13 of RAMn on or off in System ON mode
pub fn s14power(&mut self) -> S14POWER_W<'_>
pub fn s14power(&mut self) -> S14POWER_W<'_>
Bit 14 - Keep RAM section S14 of RAMn on or off in System ON mode
pub fn s15power(&mut self) -> S15POWER_W<'_>
pub fn s15power(&mut self) -> S15POWER_W<'_>
Bit 15 - Keep RAM section S15 of RAMn on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
pub fn s2retention(&mut self) -> S2RETENTION_W<'_>
Bit 18 - Keep retention on RAM section S2 when RAM section is switched off
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
pub fn s3retention(&mut self) -> S3RETENTION_W<'_>
Bit 19 - Keep retention on RAM section S3 when RAM section is switched off
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
pub fn s4retention(&mut self) -> S4RETENTION_W<'_>
Bit 20 - Keep retention on RAM section S4 when RAM section is switched off
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
pub fn s5retention(&mut self) -> S5RETENTION_W<'_>
Bit 21 - Keep retention on RAM section S5 when RAM section is switched off
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
pub fn s6retention(&mut self) -> S6RETENTION_W<'_>
Bit 22 - Keep retention on RAM section S6 when RAM section is switched off
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
pub fn s7retention(&mut self) -> S7RETENTION_W<'_>
Bit 23 - Keep retention on RAM section S7 when RAM section is switched off
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
pub fn s8retention(&mut self) -> S8RETENTION_W<'_>
Bit 24 - Keep retention on RAM section S8 when RAM section is switched off
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
pub fn s9retention(&mut self) -> S9RETENTION_W<'_>
Bit 25 - Keep retention on RAM section S9 when RAM section is switched off
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
pub fn s10retention(&mut self) -> S10RETENTION_W<'_>
Bit 26 - Keep retention on RAM section S10 when RAM section is switched off
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
pub fn s11retention(&mut self) -> S11RETENTION_W<'_>
Bit 27 - Keep retention on RAM section S11 when RAM section is switched off
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
pub fn s12retention(&mut self) -> S12RETENTION_W<'_>
Bit 28 - Keep retention on RAM section S12 when RAM section is switched off
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
pub fn s13retention(&mut self) -> S13RETENTION_W<'_>
Bit 29 - Keep retention on RAM section S13 when RAM section is switched off
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
pub fn s14retention(&mut self) -> S14RETENTION_W<'_>
Bit 30 - Keep retention on RAM section S14 when RAM section is switched off
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
pub fn s15retention(&mut self) -> S15RETENTION_W<'_>
Bit 31 - Keep retention on RAM section S15 when RAM section is switched off
impl W<u32, Reg<u32, _TASKS_CONSTLAT>>
impl W<u32, Reg<u32, _TASKS_CONSTLAT>>
pub fn tasks_constlat(&mut self) -> TASKS_CONSTLAT_W<'_>
pub fn tasks_constlat(&mut self) -> TASKS_CONSTLAT_W<'_>
Bit 0 - Enable Constant Latency mode
impl W<u32, Reg<u32, _TASKS_LOWPWR>>
impl W<u32, Reg<u32, _TASKS_LOWPWR>>
pub fn tasks_lowpwr(&mut self) -> TASKS_LOWPWR_W<'_>
pub fn tasks_lowpwr(&mut self) -> TASKS_LOWPWR_W<'_>
Bit 0 - Enable Low-power mode (variable latency)
impl W<u32, Reg<u32, _EVENTS_POFWARN>>
impl W<u32, Reg<u32, _EVENTS_POFWARN>>
pub fn events_pofwarn(&mut self) -> EVENTS_POFWARN_W<'_>
pub fn events_pofwarn(&mut self) -> EVENTS_POFWARN_W<'_>
Bit 0 - Power failure warning
impl W<u32, Reg<u32, _EVENTS_SLEEPENTER>>
impl W<u32, Reg<u32, _EVENTS_SLEEPENTER>>
pub fn events_sleepenter(&mut self) -> EVENTS_SLEEPENTER_W<'_>
pub fn events_sleepenter(&mut self) -> EVENTS_SLEEPENTER_W<'_>
Bit 0 - CPU entered WFI/WFE sleep
impl W<u32, Reg<u32, _EVENTS_SLEEPEXIT>>
impl W<u32, Reg<u32, _EVENTS_SLEEPEXIT>>
pub fn events_sleepexit(&mut self) -> EVENTS_SLEEPEXIT_W<'_>
pub fn events_sleepexit(&mut self) -> EVENTS_SLEEPEXIT_W<'_>
Bit 0 - CPU exited WFI/WFE sleep
impl W<u32, Reg<u32, _EVENTS_USBDETECTED>>
impl W<u32, Reg<u32, _EVENTS_USBDETECTED>>
pub fn events_usbdetected(&mut self) -> EVENTS_USBDETECTED_W<'_>
pub fn events_usbdetected(&mut self) -> EVENTS_USBDETECTED_W<'_>
Bit 0 - Voltage supply detected on VBUS
impl W<u32, Reg<u32, _EVENTS_USBREMOVED>>
impl W<u32, Reg<u32, _EVENTS_USBREMOVED>>
pub fn events_usbremoved(&mut self) -> EVENTS_USBREMOVED_W<'_>
pub fn events_usbremoved(&mut self) -> EVENTS_USBREMOVED_W<'_>
Bit 0 - Voltage supply removed from VBUS
impl W<u32, Reg<u32, _EVENTS_USBPWRRDY>>
impl W<u32, Reg<u32, _EVENTS_USBPWRRDY>>
pub fn events_usbpwrrdy(&mut self) -> EVENTS_USBPWRRDY_W<'_>
pub fn events_usbpwrrdy(&mut self) -> EVENTS_USBPWRRDY_W<'_>
Bit 0 - USB 3.3 V supply ready
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event SLEEPENTER
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event SLEEPEXIT
pub fn usbdetected(&mut self) -> USBDETECTED_W<'_>
pub fn usbdetected(&mut self) -> USBDETECTED_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event USBDETECTED
pub fn usbremoved(&mut self) -> USBREMOVED_W<'_>
pub fn usbremoved(&mut self) -> USBREMOVED_W<'_>
Bit 8 - Write ‘1’ to enable interrupt for event USBREMOVED
pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W<'_>
pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W<'_>
Bit 9 - Write ‘1’ to enable interrupt for event USBPWRRDY
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event SLEEPENTER
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event SLEEPEXIT
pub fn usbdetected(&mut self) -> USBDETECTED_W<'_>
pub fn usbdetected(&mut self) -> USBDETECTED_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event USBDETECTED
pub fn usbremoved(&mut self) -> USBREMOVED_W<'_>
pub fn usbremoved(&mut self) -> USBREMOVED_W<'_>
Bit 8 - Write ‘1’ to disable interrupt for event USBREMOVED
pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W<'_>
pub fn usbpwrrdy(&mut self) -> USBPWRRDY_W<'_>
Bit 9 - Write ‘1’ to disable interrupt for event USBPWRRDY
impl W<u32, Reg<u32, _RESETREAS>>
impl W<u32, Reg<u32, _RESETREAS>>
pub fn resetpin(&mut self) -> RESETPIN_W<'_>
pub fn resetpin(&mut self) -> RESETPIN_W<'_>
Bit 0 - Reset from pin-reset detected
pub fn off(&mut self) -> OFF_W<'_>
pub fn off(&mut self) -> OFF_W<'_>
Bit 16 - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
pub fn lpcomp(&mut self) -> LPCOMP_W<'_>
pub fn lpcomp(&mut self) -> LPCOMP_W<'_>
Bit 17 - Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
pub fn dif(&mut self) -> DIF_W<'_>
pub fn dif(&mut self) -> DIF_W<'_>
Bit 18 - Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
impl W<u32, Reg<u32, _SYSTEMOFF>>
impl W<u32, Reg<u32, _SYSTEMOFF>>
pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>
pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>
Bit 0 - Enable System OFF mode
impl W<u32, Reg<u32, _POFCON>>
impl W<u32, Reg<u32, _POFCON>>
pub fn threshold(&mut self) -> THRESHOLD_W<'_>
pub fn threshold(&mut self) -> THRESHOLD_W<'_>
Bits 1:4 - Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.
pub fn thresholdvddh(&mut self) -> THRESHOLDVDDH_W<'_>
pub fn thresholdvddh(&mut self) -> THRESHOLDVDDH_W<'_>
Bits 8:11 - Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).
impl W<u32, Reg<u32, _GPREGRET>>
impl W<u32, Reg<u32, _GPREGRET>>
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _GPREGRET2>>
impl W<u32, Reg<u32, _GPREGRET2>>
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
pub fn gpregret(&mut self) -> GPREGRET_W<'_>
Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _LATCH>>
impl W<u32, Reg<u32, _LATCH>>
pub fn pin0(&mut self) -> PIN0_W<'_>
pub fn pin0(&mut self) -> PIN0_W<'_>
Bit 0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write ‘1’ to clear.
pub fn pin1(&mut self) -> PIN1_W<'_>
pub fn pin1(&mut self) -> PIN1_W<'_>
Bit 1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write ‘1’ to clear.
pub fn pin2(&mut self) -> PIN2_W<'_>
pub fn pin2(&mut self) -> PIN2_W<'_>
Bit 2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write ‘1’ to clear.
pub fn pin3(&mut self) -> PIN3_W<'_>
pub fn pin3(&mut self) -> PIN3_W<'_>
Bit 3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write ‘1’ to clear.
pub fn pin4(&mut self) -> PIN4_W<'_>
pub fn pin4(&mut self) -> PIN4_W<'_>
Bit 4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write ‘1’ to clear.
pub fn pin5(&mut self) -> PIN5_W<'_>
pub fn pin5(&mut self) -> PIN5_W<'_>
Bit 5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write ‘1’ to clear.
pub fn pin6(&mut self) -> PIN6_W<'_>
pub fn pin6(&mut self) -> PIN6_W<'_>
Bit 6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write ‘1’ to clear.
pub fn pin7(&mut self) -> PIN7_W<'_>
pub fn pin7(&mut self) -> PIN7_W<'_>
Bit 7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write ‘1’ to clear.
pub fn pin8(&mut self) -> PIN8_W<'_>
pub fn pin8(&mut self) -> PIN8_W<'_>
Bit 8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write ‘1’ to clear.
pub fn pin9(&mut self) -> PIN9_W<'_>
pub fn pin9(&mut self) -> PIN9_W<'_>
Bit 9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write ‘1’ to clear.
pub fn pin10(&mut self) -> PIN10_W<'_>
pub fn pin10(&mut self) -> PIN10_W<'_>
Bit 10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write ‘1’ to clear.
pub fn pin11(&mut self) -> PIN11_W<'_>
pub fn pin11(&mut self) -> PIN11_W<'_>
Bit 11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write ‘1’ to clear.
pub fn pin12(&mut self) -> PIN12_W<'_>
pub fn pin12(&mut self) -> PIN12_W<'_>
Bit 12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write ‘1’ to clear.
pub fn pin13(&mut self) -> PIN13_W<'_>
pub fn pin13(&mut self) -> PIN13_W<'_>
Bit 13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write ‘1’ to clear.
pub fn pin14(&mut self) -> PIN14_W<'_>
pub fn pin14(&mut self) -> PIN14_W<'_>
Bit 14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write ‘1’ to clear.
pub fn pin15(&mut self) -> PIN15_W<'_>
pub fn pin15(&mut self) -> PIN15_W<'_>
Bit 15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write ‘1’ to clear.
pub fn pin16(&mut self) -> PIN16_W<'_>
pub fn pin16(&mut self) -> PIN16_W<'_>
Bit 16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write ‘1’ to clear.
pub fn pin17(&mut self) -> PIN17_W<'_>
pub fn pin17(&mut self) -> PIN17_W<'_>
Bit 17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write ‘1’ to clear.
pub fn pin18(&mut self) -> PIN18_W<'_>
pub fn pin18(&mut self) -> PIN18_W<'_>
Bit 18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write ‘1’ to clear.
pub fn pin19(&mut self) -> PIN19_W<'_>
pub fn pin19(&mut self) -> PIN19_W<'_>
Bit 19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write ‘1’ to clear.
pub fn pin20(&mut self) -> PIN20_W<'_>
pub fn pin20(&mut self) -> PIN20_W<'_>
Bit 20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write ‘1’ to clear.
pub fn pin21(&mut self) -> PIN21_W<'_>
pub fn pin21(&mut self) -> PIN21_W<'_>
Bit 21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write ‘1’ to clear.
pub fn pin22(&mut self) -> PIN22_W<'_>
pub fn pin22(&mut self) -> PIN22_W<'_>
Bit 22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write ‘1’ to clear.
pub fn pin23(&mut self) -> PIN23_W<'_>
pub fn pin23(&mut self) -> PIN23_W<'_>
Bit 23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write ‘1’ to clear.
pub fn pin24(&mut self) -> PIN24_W<'_>
pub fn pin24(&mut self) -> PIN24_W<'_>
Bit 24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write ‘1’ to clear.
pub fn pin25(&mut self) -> PIN25_W<'_>
pub fn pin25(&mut self) -> PIN25_W<'_>
Bit 25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write ‘1’ to clear.
pub fn pin26(&mut self) -> PIN26_W<'_>
pub fn pin26(&mut self) -> PIN26_W<'_>
Bit 26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write ‘1’ to clear.
pub fn pin27(&mut self) -> PIN27_W<'_>
pub fn pin27(&mut self) -> PIN27_W<'_>
Bit 27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write ‘1’ to clear.
pub fn pin28(&mut self) -> PIN28_W<'_>
pub fn pin28(&mut self) -> PIN28_W<'_>
Bit 28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write ‘1’ to clear.
pub fn pin29(&mut self) -> PIN29_W<'_>
pub fn pin29(&mut self) -> PIN29_W<'_>
Bit 29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write ‘1’ to clear.
impl W<u32, Reg<u32, _DETECTMODE>>
impl W<u32, Reg<u32, _DETECTMODE>>
pub fn detectmode(&mut self) -> DETECTMODE_W<'_>
pub fn detectmode(&mut self) -> DETECTMODE_W<'_>
Bit 0 - Select between default DETECT signal behaviour and LDETECT mode
impl W<u32, Reg<u32, _TASKS_TXEN>>
impl W<u32, Reg<u32, _TASKS_TXEN>>
pub fn tasks_txen(&mut self) -> TASKS_TXEN_W<'_>
pub fn tasks_txen(&mut self) -> TASKS_TXEN_W<'_>
Bit 0 - Enable RADIO in TX mode
impl W<u32, Reg<u32, _TASKS_RXEN>>
impl W<u32, Reg<u32, _TASKS_RXEN>>
pub fn tasks_rxen(&mut self) -> TASKS_RXEN_W<'_>
pub fn tasks_rxen(&mut self) -> TASKS_RXEN_W<'_>
Bit 0 - Enable RADIO in RX mode
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start RADIO
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop RADIO
impl W<u32, Reg<u32, _TASKS_DISABLE>>
impl W<u32, Reg<u32, _TASKS_DISABLE>>
pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W<'_>
pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W<'_>
Bit 0 - Disable RADIO
impl W<u32, Reg<u32, _TASKS_RSSISTART>>
impl W<u32, Reg<u32, _TASKS_RSSISTART>>
pub fn tasks_rssistart(&mut self) -> TASKS_RSSISTART_W<'_>
pub fn tasks_rssistart(&mut self) -> TASKS_RSSISTART_W<'_>
Bit 0 - Start the RSSI and take one single sample of the receive signal strength
impl W<u32, Reg<u32, _TASKS_RSSISTOP>>
impl W<u32, Reg<u32, _TASKS_RSSISTOP>>
pub fn tasks_rssistop(&mut self) -> TASKS_RSSISTOP_W<'_>
pub fn tasks_rssistop(&mut self) -> TASKS_RSSISTOP_W<'_>
Bit 0 - Stop the RSSI measurement
impl W<u32, Reg<u32, _TASKS_BCSTART>>
impl W<u32, Reg<u32, _TASKS_BCSTART>>
pub fn tasks_bcstart(&mut self) -> TASKS_BCSTART_W<'_>
pub fn tasks_bcstart(&mut self) -> TASKS_BCSTART_W<'_>
Bit 0 - Start the bit counter
impl W<u32, Reg<u32, _TASKS_BCSTOP>>
impl W<u32, Reg<u32, _TASKS_BCSTOP>>
pub fn tasks_bcstop(&mut self) -> TASKS_BCSTOP_W<'_>
pub fn tasks_bcstop(&mut self) -> TASKS_BCSTOP_W<'_>
Bit 0 - Stop the bit counter
impl W<u32, Reg<u32, _TASKS_EDSTART>>
impl W<u32, Reg<u32, _TASKS_EDSTART>>
pub fn tasks_edstart(&mut self) -> TASKS_EDSTART_W<'_>
pub fn tasks_edstart(&mut self) -> TASKS_EDSTART_W<'_>
Bit 0 - Start the energy detect measurement used in IEEE 802.15.4 mode
impl W<u32, Reg<u32, _TASKS_EDSTOP>>
impl W<u32, Reg<u32, _TASKS_EDSTOP>>
pub fn tasks_edstop(&mut self) -> TASKS_EDSTOP_W<'_>
pub fn tasks_edstop(&mut self) -> TASKS_EDSTOP_W<'_>
Bit 0 - Stop the energy detect measurement
impl W<u32, Reg<u32, _TASKS_CCASTART>>
impl W<u32, Reg<u32, _TASKS_CCASTART>>
pub fn tasks_ccastart(&mut self) -> TASKS_CCASTART_W<'_>
pub fn tasks_ccastart(&mut self) -> TASKS_CCASTART_W<'_>
Bit 0 - Start the clear channel assessment used in IEEE 802.15.4 mode
impl W<u32, Reg<u32, _TASKS_CCASTOP>>
impl W<u32, Reg<u32, _TASKS_CCASTOP>>
pub fn tasks_ccastop(&mut self) -> TASKS_CCASTOP_W<'_>
pub fn tasks_ccastop(&mut self) -> TASKS_CCASTOP_W<'_>
Bit 0 - Stop the clear channel assessment
impl W<u32, Reg<u32, _EVENTS_READY>>
impl W<u32, Reg<u32, _EVENTS_READY>>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
Bit 0 - RADIO has ramped up and is ready to be started
impl W<u32, Reg<u32, _EVENTS_ADDRESS>>
impl W<u32, Reg<u32, _EVENTS_ADDRESS>>
pub fn events_address(&mut self) -> EVENTS_ADDRESS_W<'_>
pub fn events_address(&mut self) -> EVENTS_ADDRESS_W<'_>
Bit 0 - Address sent or received
impl W<u32, Reg<u32, _EVENTS_PAYLOAD>>
impl W<u32, Reg<u32, _EVENTS_PAYLOAD>>
pub fn events_payload(&mut self) -> EVENTS_PAYLOAD_W<'_>
pub fn events_payload(&mut self) -> EVENTS_PAYLOAD_W<'_>
Bit 0 - Packet payload sent or received
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - Packet sent or received
impl W<u32, Reg<u32, _EVENTS_DISABLED>>
impl W<u32, Reg<u32, _EVENTS_DISABLED>>
pub fn events_disabled(&mut self) -> EVENTS_DISABLED_W<'_>
pub fn events_disabled(&mut self) -> EVENTS_DISABLED_W<'_>
Bit 0 - RADIO has been disabled
impl W<u32, Reg<u32, _EVENTS_DEVMATCH>>
impl W<u32, Reg<u32, _EVENTS_DEVMATCH>>
pub fn events_devmatch(&mut self) -> EVENTS_DEVMATCH_W<'_>
pub fn events_devmatch(&mut self) -> EVENTS_DEVMATCH_W<'_>
Bit 0 - A device address match occurred on the last received packet
impl W<u32, Reg<u32, _EVENTS_DEVMISS>>
impl W<u32, Reg<u32, _EVENTS_DEVMISS>>
pub fn events_devmiss(&mut self) -> EVENTS_DEVMISS_W<'_>
pub fn events_devmiss(&mut self) -> EVENTS_DEVMISS_W<'_>
Bit 0 - No device address match occurred on the last received packet
impl W<u32, Reg<u32, _EVENTS_RSSIEND>>
impl W<u32, Reg<u32, _EVENTS_RSSIEND>>
pub fn events_rssiend(&mut self) -> EVENTS_RSSIEND_W<'_>
pub fn events_rssiend(&mut self) -> EVENTS_RSSIEND_W<'_>
Bit 0 - Sampling of receive signal strength complete
impl W<u32, Reg<u32, _EVENTS_BCMATCH>>
impl W<u32, Reg<u32, _EVENTS_BCMATCH>>
pub fn events_bcmatch(&mut self) -> EVENTS_BCMATCH_W<'_>
pub fn events_bcmatch(&mut self) -> EVENTS_BCMATCH_W<'_>
Bit 0 - Bit counter reached bit count value
impl W<u32, Reg<u32, _EVENTS_CRCOK>>
impl W<u32, Reg<u32, _EVENTS_CRCOK>>
pub fn events_crcok(&mut self) -> EVENTS_CRCOK_W<'_>
pub fn events_crcok(&mut self) -> EVENTS_CRCOK_W<'_>
Bit 0 - Packet received with CRC ok
impl W<u32, Reg<u32, _EVENTS_CRCERROR>>
impl W<u32, Reg<u32, _EVENTS_CRCERROR>>
pub fn events_crcerror(&mut self) -> EVENTS_CRCERROR_W<'_>
pub fn events_crcerror(&mut self) -> EVENTS_CRCERROR_W<'_>
Bit 0 - Packet received with CRC error
impl W<u32, Reg<u32, _EVENTS_FRAMESTART>>
impl W<u32, Reg<u32, _EVENTS_FRAMESTART>>
pub fn events_framestart(&mut self) -> EVENTS_FRAMESTART_W<'_>
pub fn events_framestart(&mut self) -> EVENTS_FRAMESTART_W<'_>
Bit 0 - IEEE 802.15.4 length field received
impl W<u32, Reg<u32, _EVENTS_EDEND>>
impl W<u32, Reg<u32, _EVENTS_EDEND>>
pub fn events_edend(&mut self) -> EVENTS_EDEND_W<'_>
pub fn events_edend(&mut self) -> EVENTS_EDEND_W<'_>
Bit 0 - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
impl W<u32, Reg<u32, _EVENTS_EDSTOPPED>>
impl W<u32, Reg<u32, _EVENTS_EDSTOPPED>>
pub fn events_edstopped(&mut self) -> EVENTS_EDSTOPPED_W<'_>
pub fn events_edstopped(&mut self) -> EVENTS_EDSTOPPED_W<'_>
Bit 0 - The sampling of energy detection has stopped
impl W<u32, Reg<u32, _EVENTS_CCAIDLE>>
impl W<u32, Reg<u32, _EVENTS_CCAIDLE>>
pub fn events_ccaidle(&mut self) -> EVENTS_CCAIDLE_W<'_>
pub fn events_ccaidle(&mut self) -> EVENTS_CCAIDLE_W<'_>
Bit 0 - Wireless medium in idle - clear to send
impl W<u32, Reg<u32, _EVENTS_CCABUSY>>
impl W<u32, Reg<u32, _EVENTS_CCABUSY>>
pub fn events_ccabusy(&mut self) -> EVENTS_CCABUSY_W<'_>
pub fn events_ccabusy(&mut self) -> EVENTS_CCABUSY_W<'_>
Bit 0 - Wireless medium busy - do not send
impl W<u32, Reg<u32, _EVENTS_CCASTOPPED>>
impl W<u32, Reg<u32, _EVENTS_CCASTOPPED>>
pub fn events_ccastopped(&mut self) -> EVENTS_CCASTOPPED_W<'_>
pub fn events_ccastopped(&mut self) -> EVENTS_CCASTOPPED_W<'_>
Bit 0 - The CCA has stopped
impl W<u32, Reg<u32, _EVENTS_RATEBOOST>>
impl W<u32, Reg<u32, _EVENTS_RATEBOOST>>
pub fn events_rateboost(&mut self) -> EVENTS_RATEBOOST_W<'_>
pub fn events_rateboost(&mut self) -> EVENTS_RATEBOOST_W<'_>
Bit 0 - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
impl W<u32, Reg<u32, _EVENTS_TXREADY>>
impl W<u32, Reg<u32, _EVENTS_TXREADY>>
pub fn events_txready(&mut self) -> EVENTS_TXREADY_W<'_>
pub fn events_txready(&mut self) -> EVENTS_TXREADY_W<'_>
Bit 0 - RADIO has ramped up and is ready to be started TX path
impl W<u32, Reg<u32, _EVENTS_RXREADY>>
impl W<u32, Reg<u32, _EVENTS_RXREADY>>
pub fn events_rxready(&mut self) -> EVENTS_RXREADY_W<'_>
pub fn events_rxready(&mut self) -> EVENTS_RXREADY_W<'_>
Bit 0 - RADIO has ramped up and is ready to be started RX path
impl W<u32, Reg<u32, _EVENTS_MHRMATCH>>
impl W<u32, Reg<u32, _EVENTS_MHRMATCH>>
pub fn events_mhrmatch(&mut self) -> EVENTS_MHRMATCH_W<'_>
pub fn events_mhrmatch(&mut self) -> EVENTS_MHRMATCH_W<'_>
Bit 0 - MAC header match found
impl W<u32, Reg<u32, _EVENTS_SYNC>>
impl W<u32, Reg<u32, _EVENTS_SYNC>>
pub fn events_sync(&mut self) -> EVENTS_SYNC_W<'_>
pub fn events_sync(&mut self) -> EVENTS_SYNC_W<'_>
Bit 0 - Preamble indicator
impl W<u32, Reg<u32, _EVENTS_PHYEND>>
impl W<u32, Reg<u32, _EVENTS_PHYEND>>
pub fn events_phyend(&mut self) -> EVENTS_PHYEND_W<'_>
pub fn events_phyend(&mut self) -> EVENTS_PHYEND_W<'_>
Bit 0 - Generated when last bit is sent on air, or received from air
impl W<u32, Reg<u32, _EVENTS_CTEPRESENT>>
impl W<u32, Reg<u32, _EVENTS_CTEPRESENT>>
pub fn events_ctepresent(&mut self) -> EVENTS_CTEPRESENT_W<'_>
pub fn events_ctepresent(&mut self) -> EVENTS_CTEPRESENT_W<'_>
Bit 0 - CTE is present (early warning right after receiving CTEInfo byte)
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn ready_start(&mut self) -> READY_START_W<'_>
pub fn ready_start(&mut self) -> READY_START_W<'_>
Bit 0 - Shortcut between event READY and task START
pub fn end_disable(&mut self) -> END_DISABLE_W<'_>
pub fn end_disable(&mut self) -> END_DISABLE_W<'_>
Bit 1 - Shortcut between event END and task DISABLE
pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>
pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>
Bit 2 - Shortcut between event DISABLED and task TXEN
pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>
pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>
Bit 3 - Shortcut between event DISABLED and task RXEN
pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>
pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>
Bit 4 - Shortcut between event ADDRESS and task RSSISTART
pub fn end_start(&mut self) -> END_START_W<'_>
pub fn end_start(&mut self) -> END_START_W<'_>
Bit 5 - Shortcut between event END and task START
pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>
pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>
Bit 6 - Shortcut between event ADDRESS and task BCSTART
pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>
pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>
Bit 8 - Shortcut between event DISABLED and task RSSISTOP
pub fn rxready_ccastart(&mut self) -> RXREADY_CCASTART_W<'_>
pub fn rxready_ccastart(&mut self) -> RXREADY_CCASTART_W<'_>
Bit 11 - Shortcut between event RXREADY and task CCASTART
pub fn ccaidle_txen(&mut self) -> CCAIDLE_TXEN_W<'_>
pub fn ccaidle_txen(&mut self) -> CCAIDLE_TXEN_W<'_>
Bit 12 - Shortcut between event CCAIDLE and task TXEN
pub fn ccabusy_disable(&mut self) -> CCABUSY_DISABLE_W<'_>
pub fn ccabusy_disable(&mut self) -> CCABUSY_DISABLE_W<'_>
Bit 13 - Shortcut between event CCABUSY and task DISABLE
pub fn framestart_bcstart(&mut self) -> FRAMESTART_BCSTART_W<'_>
pub fn framestart_bcstart(&mut self) -> FRAMESTART_BCSTART_W<'_>
Bit 14 - Shortcut between event FRAMESTART and task BCSTART
pub fn ready_edstart(&mut self) -> READY_EDSTART_W<'_>
pub fn ready_edstart(&mut self) -> READY_EDSTART_W<'_>
Bit 15 - Shortcut between event READY and task EDSTART
pub fn edend_disable(&mut self) -> EDEND_DISABLE_W<'_>
pub fn edend_disable(&mut self) -> EDEND_DISABLE_W<'_>
Bit 16 - Shortcut between event EDEND and task DISABLE
pub fn ccaidle_stop(&mut self) -> CCAIDLE_STOP_W<'_>
pub fn ccaidle_stop(&mut self) -> CCAIDLE_STOP_W<'_>
Bit 17 - Shortcut between event CCAIDLE and task STOP
pub fn txready_start(&mut self) -> TXREADY_START_W<'_>
pub fn txready_start(&mut self) -> TXREADY_START_W<'_>
Bit 18 - Shortcut between event TXREADY and task START
pub fn rxready_start(&mut self) -> RXREADY_START_W<'_>
pub fn rxready_start(&mut self) -> RXREADY_START_W<'_>
Bit 19 - Shortcut between event RXREADY and task START
pub fn phyend_disable(&mut self) -> PHYEND_DISABLE_W<'_>
pub fn phyend_disable(&mut self) -> PHYEND_DISABLE_W<'_>
Bit 20 - Shortcut between event PHYEND and task DISABLE
pub fn phyend_start(&mut self) -> PHYEND_START_W<'_>
pub fn phyend_start(&mut self) -> PHYEND_START_W<'_>
Bit 21 - Shortcut between event PHYEND and task START
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn disabled(&mut self) -> DISABLED_W<'_>
pub fn disabled(&mut self) -> DISABLED_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event DISABLED
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event DEVMATCH
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
Bit 13 - Write ‘1’ to enable interrupt for event CRCERROR
pub fn framestart(&mut self) -> FRAMESTART_W<'_>
pub fn framestart(&mut self) -> FRAMESTART_W<'_>
Bit 14 - Write ‘1’ to enable interrupt for event FRAMESTART
pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>
pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>
Bit 16 - Write ‘1’ to enable interrupt for event EDSTOPPED
pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>
pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event CCASTOPPED
pub fn rateboost(&mut self) -> RATEBOOST_W<'_>
pub fn rateboost(&mut self) -> RATEBOOST_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event RATEBOOST
pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>
pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>
Bit 23 - Write ‘1’ to enable interrupt for event MHRMATCH
pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>
pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>
Bit 28 - Write ‘1’ to enable interrupt for event CTEPRESENT
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn disabled(&mut self) -> DISABLED_W<'_>
pub fn disabled(&mut self) -> DISABLED_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event DISABLED
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event DEVMATCH
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
Bit 13 - Write ‘1’ to disable interrupt for event CRCERROR
pub fn framestart(&mut self) -> FRAMESTART_W<'_>
pub fn framestart(&mut self) -> FRAMESTART_W<'_>
Bit 14 - Write ‘1’ to disable interrupt for event FRAMESTART
pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>
pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>
Bit 16 - Write ‘1’ to disable interrupt for event EDSTOPPED
pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>
pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event CCASTOPPED
pub fn rateboost(&mut self) -> RATEBOOST_W<'_>
pub fn rateboost(&mut self) -> RATEBOOST_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event RATEBOOST
pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>
pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>
Bit 23 - Write ‘1’ to disable interrupt for event MHRMATCH
pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>
pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>
Bit 28 - Write ‘1’ to disable interrupt for event CTEPRESENT
impl W<u32, Reg<u32, _PACKETPTR>>
impl W<u32, Reg<u32, _PACKETPTR>>
pub fn packetptr(&mut self) -> PACKETPTR_W<'_>
pub fn packetptr(&mut self) -> PACKETPTR_W<'_>
Bits 0:31 - Packet pointer
impl W<u32, Reg<u32, _FREQUENCY>>
impl W<u32, Reg<u32, _FREQUENCY>>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
Bits 0:6 - Radio channel frequency
impl W<u32, Reg<u32, _PCNF0>>
impl W<u32, Reg<u32, _PCNF0>>
impl W<u32, Reg<u32, _PCNF1>>
impl W<u32, Reg<u32, _PCNF1>>
pub fn maxlen(&mut self) -> MAXLEN_W<'_>
pub fn maxlen(&mut self) -> MAXLEN_W<'_>
Bits 0:7 - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
impl W<u32, Reg<u32, _TXADDRESS>>
impl W<u32, Reg<u32, _TXADDRESS>>
pub fn txaddress(&mut self) -> TXADDRESS_W<'_>
pub fn txaddress(&mut self) -> TXADDRESS_W<'_>
Bits 0:2 - Transmit address select
impl W<u32, Reg<u32, _CRCCNF>>
impl W<u32, Reg<u32, _CRCCNF>>
pub fn skipaddr(&mut self) -> SKIPADDR_W<'_>
pub fn skipaddr(&mut self) -> SKIPADDR_W<'_>
Bits 8:9 - Include or exclude packet address field out of CRC calculation.
impl W<u32, Reg<u32, _DATAWHITEIV>>
impl W<u32, Reg<u32, _DATAWHITEIV>>
pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>
pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>
Bits 0:6 - Data whitening initial value. Bit 6 is hardwired to ‘1’, writing ‘0’ to it has no effect, and it will always be read back and used by the device as ‘1’.
impl W<u32, Reg<u32, _DACNF>>
impl W<u32, Reg<u32, _DACNF>>
pub fn ena0(&mut self) -> ENA0_W<'_>
pub fn ena0(&mut self) -> ENA0_W<'_>
Bit 0 - Enable or disable device address matching using device address 0
pub fn ena1(&mut self) -> ENA1_W<'_>
pub fn ena1(&mut self) -> ENA1_W<'_>
Bit 1 - Enable or disable device address matching using device address 1
pub fn ena2(&mut self) -> ENA2_W<'_>
pub fn ena2(&mut self) -> ENA2_W<'_>
Bit 2 - Enable or disable device address matching using device address 2
pub fn ena3(&mut self) -> ENA3_W<'_>
pub fn ena3(&mut self) -> ENA3_W<'_>
Bit 3 - Enable or disable device address matching using device address 3
pub fn ena4(&mut self) -> ENA4_W<'_>
pub fn ena4(&mut self) -> ENA4_W<'_>
Bit 4 - Enable or disable device address matching using device address 4
pub fn ena5(&mut self) -> ENA5_W<'_>
pub fn ena5(&mut self) -> ENA5_W<'_>
Bit 5 - Enable or disable device address matching using device address 5
pub fn ena6(&mut self) -> ENA6_W<'_>
pub fn ena6(&mut self) -> ENA6_W<'_>
Bit 6 - Enable or disable device address matching using device address 6
impl W<u32, Reg<u32, _MHRMATCHCONF>>
impl W<u32, Reg<u32, _MHRMATCHCONF>>
pub fn mhrmatchconf(&mut self) -> MHRMATCHCONF_W<'_>
pub fn mhrmatchconf(&mut self) -> MHRMATCHCONF_W<'_>
Bits 0:31 - Search pattern configuration
impl W<u32, Reg<u32, _MHRMATCHMAS>>
impl W<u32, Reg<u32, _MHRMATCHMAS>>
pub fn mhrmatchmas(&mut self) -> MHRMATCHMAS_W<'_>
pub fn mhrmatchmas(&mut self) -> MHRMATCHMAS_W<'_>
Bits 0:31 - Pattern mask
impl W<u32, Reg<u32, _CCACTRL>>
impl W<u32, Reg<u32, _CCACTRL>>
pub fn ccaedthres(&mut self) -> CCAEDTHRES_W<'_>
pub fn ccaedthres(&mut self) -> CCAEDTHRES_W<'_>
Bits 8:15 - CCA energy busy threshold. Used in all the CCA modes except CarrierMode.
pub fn ccacorrthres(&mut self) -> CCACORRTHRES_W<'_>
pub fn ccacorrthres(&mut self) -> CCACORRTHRES_W<'_>
Bits 16:23 - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
pub fn ccacorrcnt(&mut self) -> CCACORRCNT_W<'_>
pub fn ccacorrcnt(&mut self) -> CCACORRCNT_W<'_>
Bits 24:31 - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.
impl W<u32, Reg<u32, _DFEMODE>>
impl W<u32, Reg<u32, _DFEMODE>>
pub fn dfeopmode(&mut self) -> DFEOPMODE_W<'_>
pub fn dfeopmode(&mut self) -> DFEOPMODE_W<'_>
Bits 0:1 - Direction finding operation mode
impl W<u32, Reg<u32, _CTEINLINECONF>>
impl W<u32, Reg<u32, _CTEINLINECONF>>
pub fn cteinlinectrlen(&mut self) -> CTEINLINECTRLEN_W<'_>
pub fn cteinlinectrlen(&mut self) -> CTEINLINECTRLEN_W<'_>
Bit 0 - Enable parsing of CTEInfo from received packet in BLE modes
pub fn cteinfoins1(&mut self) -> CTEINFOINS1_W<'_>
pub fn cteinfoins1(&mut self) -> CTEINFOINS1_W<'_>
Bit 3 - CTEInfo is S1 byte or not
pub fn cteerrorhandling(&mut self) -> CTEERRORHANDLING_W<'_>
pub fn cteerrorhandling(&mut self) -> CTEERRORHANDLING_W<'_>
Bit 4 - Sampling/switching if CRC is not OK
pub fn ctetimevalidrange(&mut self) -> CTETIMEVALIDRANGE_W<'_>
pub fn ctetimevalidrange(&mut self) -> CTETIMEVALIDRANGE_W<'_>
Bits 6:7 - Max range of CTETime
pub fn cteinlinerxmode1us(&mut self) -> CTEINLINERXMODE1US_W<'_>
pub fn cteinlinerxmode1us(&mut self) -> CTEINLINERXMODE1US_W<'_>
Bits 10:12 - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
pub fn cteinlinerxmode2us(&mut self) -> CTEINLINERXMODE2US_W<'_>
pub fn cteinlinerxmode2us(&mut self) -> CTEINLINERXMODE2US_W<'_>
Bits 13:15 - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
impl W<u32, Reg<u32, _DFECTRL1>>
impl W<u32, Reg<u32, _DFECTRL1>>
pub fn numberof8us(&mut self) -> NUMBEROF8US_W<'_>
pub fn numberof8us(&mut self) -> NUMBEROF8US_W<'_>
Bits 0:5 - Length of the AoA/AoD procedure in number of 8 us units
pub fn dfeinextension(&mut self) -> DFEINEXTENSION_W<'_>
pub fn dfeinextension(&mut self) -> DFEINEXTENSION_W<'_>
Bit 7 - Add CTE extension and do antenna switching/sampling in this extension
pub fn tswitchspacing(&mut self) -> TSWITCHSPACING_W<'_>
pub fn tswitchspacing(&mut self) -> TSWITCHSPACING_W<'_>
Bits 8:10 - Interval between every time the antenna is changed in the SWITCHING state
pub fn tsamplespacingref(&mut self) -> TSAMPLESPACINGREF_W<'_>
pub fn tsamplespacingref(&mut self) -> TSAMPLESPACINGREF_W<'_>
Bits 12:14 - Interval between samples in the REFERENCE period
pub fn sampletype(&mut self) -> SAMPLETYPE_W<'_>
pub fn sampletype(&mut self) -> SAMPLETYPE_W<'_>
Bit 15 - Whether to sample I/Q or magnitude/phase
pub fn tsamplespacing(&mut self) -> TSAMPLESPACING_W<'_>
pub fn tsamplespacing(&mut self) -> TSAMPLESPACING_W<'_>
Bits 16:18 - Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0
pub fn repeatpattern(&mut self) -> REPEATPATTERN_W<'_>
pub fn repeatpattern(&mut self) -> REPEATPATTERN_W<'_>
Bits 20:23 - Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc.
pub fn agcbackoffgain(&mut self) -> AGCBACKOFFGAIN_W<'_>
pub fn agcbackoffgain(&mut self) -> AGCBACKOFFGAIN_W<'_>
Bits 24:27 - Gain will be lowered by the specified number of gain steps at the start of CTE
impl W<u32, Reg<u32, _DFECTRL2>>
impl W<u32, Reg<u32, _DFECTRL2>>
pub fn tswitchoffset(&mut self) -> TSWITCHOFFSET_W<'_>
pub fn tswitchoffset(&mut self) -> TSWITCHOFFSET_W<'_>
Bits 0:12 - Signed value offset after the end of the CRC before starting switching in number of 16M cycles
pub fn tsampleoffset(&mut self) -> TSAMPLEOFFSET_W<'_>
pub fn tsampleoffset(&mut self) -> TSAMPLEOFFSET_W<'_>
Bits 16:27 - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start
impl W<u32, Reg<u32, _SWITCHPATTERN>>
impl W<u32, Reg<u32, _SWITCHPATTERN>>
pub fn switchpattern(&mut self) -> SWITCHPATTERN_W<'_>
pub fn switchpattern(&mut self) -> SWITCHPATTERN_W<'_>
Bits 0:7 - Fill array of GPIO patterns for antenna control
impl W<u32, Reg<u32, _CLEARPATTERN>>
impl W<u32, Reg<u32, _CLEARPATTERN>>
pub fn clearpattern(&mut self) -> CLEARPATTERN_W<'_>
pub fn clearpattern(&mut self) -> CLEARPATTERN_W<'_>
Bit 0 - Clears GPIO pattern array for antenna control
impl W<u32, Reg<u32, _TASKS_STARTRX>>
impl W<u32, Reg<u32, _TASKS_STARTRX>>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
Bit 0 - Start UART receiver
impl W<u32, Reg<u32, _TASKS_STOPRX>>
impl W<u32, Reg<u32, _TASKS_STOPRX>>
pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>
pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>
Bit 0 - Stop UART receiver
impl W<u32, Reg<u32, _TASKS_STARTTX>>
impl W<u32, Reg<u32, _TASKS_STARTTX>>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
Bit 0 - Start UART transmitter
impl W<u32, Reg<u32, _TASKS_STOPTX>>
impl W<u32, Reg<u32, _TASKS_STOPTX>>
pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>
pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>
Bit 0 - Stop UART transmitter
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
Bit 0 - Suspend UART
impl W<u32, Reg<u32, _EVENTS_CTS>>
impl W<u32, Reg<u32, _EVENTS_CTS>>
pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>
pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>
Bit 0 - CTS is activated (set low). Clear To Send.
impl W<u32, Reg<u32, _EVENTS_NCTS>>
impl W<u32, Reg<u32, _EVENTS_NCTS>>
pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>
pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>
Bit 0 - CTS is deactivated (set high). Not Clear To Send.
impl W<u32, Reg<u32, _EVENTS_RXDRDY>>
impl W<u32, Reg<u32, _EVENTS_RXDRDY>>
pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>
pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>
Bit 0 - Data received in RXD
impl W<u32, Reg<u32, _EVENTS_TXDRDY>>
impl W<u32, Reg<u32, _EVENTS_TXDRDY>>
pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>
pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>
Bit 0 - Data sent from TXD
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - Error detected
impl W<u32, Reg<u32, _EVENTS_RXTO>>
impl W<u32, Reg<u32, _EVENTS_RXTO>>
pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>
pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>
Bit 0 - Receiver timeout
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>
pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>
Bit 3 - Shortcut between event CTS and task STARTRX
pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>
pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>
Bit 4 - Shortcut between event NCTS and task STOPRX
impl W<u32, Reg<u32, _BAUDRATE>>
impl W<u32, Reg<u32, _BAUDRATE>>
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _CONFIG>>
pub fn paritytype(&mut self) -> PARITYTYPE_W<'_>
pub fn paritytype(&mut self) -> PARITYTYPE_W<'_>
Bit 8 - Even or odd parity type
impl W<u32, Reg<u32, _TASKS_STARTRX>>
impl W<u32, Reg<u32, _TASKS_STARTRX>>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
Bit 0 - Start UART receiver
impl W<u32, Reg<u32, _TASKS_STOPRX>>
impl W<u32, Reg<u32, _TASKS_STOPRX>>
pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>
pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>
Bit 0 - Stop UART receiver
impl W<u32, Reg<u32, _TASKS_STARTTX>>
impl W<u32, Reg<u32, _TASKS_STARTTX>>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
Bit 0 - Start UART transmitter
impl W<u32, Reg<u32, _TASKS_STOPTX>>
impl W<u32, Reg<u32, _TASKS_STOPTX>>
pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>
pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>
Bit 0 - Stop UART transmitter
impl W<u32, Reg<u32, _TASKS_FLUSHRX>>
impl W<u32, Reg<u32, _TASKS_FLUSHRX>>
pub fn tasks_flushrx(&mut self) -> TASKS_FLUSHRX_W<'_>
pub fn tasks_flushrx(&mut self) -> TASKS_FLUSHRX_W<'_>
Bit 0 - Flush RX FIFO into RX buffer
impl W<u32, Reg<u32, _EVENTS_CTS>>
impl W<u32, Reg<u32, _EVENTS_CTS>>
pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>
pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>
Bit 0 - CTS is activated (set low). Clear To Send.
impl W<u32, Reg<u32, _EVENTS_NCTS>>
impl W<u32, Reg<u32, _EVENTS_NCTS>>
pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>
pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>
Bit 0 - CTS is deactivated (set high). Not Clear To Send.
impl W<u32, Reg<u32, _EVENTS_RXDRDY>>
impl W<u32, Reg<u32, _EVENTS_RXDRDY>>
pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>
pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>
Bit 0 - Data received in RXD (but potentially not yet transferred to Data RAM)
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
Bit 0 - Receive buffer is filled up
impl W<u32, Reg<u32, _EVENTS_TXDRDY>>
impl W<u32, Reg<u32, _EVENTS_TXDRDY>>
pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>
pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>
Bit 0 - Data sent from TXD
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
Bit 0 - Last TX byte transmitted
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - Error detected
impl W<u32, Reg<u32, _EVENTS_RXTO>>
impl W<u32, Reg<u32, _EVENTS_RXTO>>
pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>
pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>
Bit 0 - Receiver timeout
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
Bit 0 - UART receiver has started
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
Bit 0 - UART transmitter has started
impl W<u32, Reg<u32, _EVENTS_TXSTOPPED>>
impl W<u32, Reg<u32, _EVENTS_TXSTOPPED>>
pub fn events_txstopped(&mut self) -> EVENTS_TXSTOPPED_W<'_>
pub fn events_txstopped(&mut self) -> EVENTS_TXSTOPPED_W<'_>
Bit 0 - Transmitter stopped
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>
pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>
Bit 5 - Shortcut between event ENDRX and task STARTRX
pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>
pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>
Bit 6 - Shortcut between event ENDRX and task STOPRX
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Enable or disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Enable or disable interrupt for event TXSTARTED
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
Bit 22 - Enable or disable interrupt for event TXSTOPPED
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event TXSTARTED
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
Bit 22 - Write ‘1’ to enable interrupt for event TXSTOPPED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event TXSTARTED
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
Bit 22 - Write ‘1’ to disable interrupt for event TXSTOPPED
impl W<u32, Reg<u32, _BAUDRATE>>
impl W<u32, Reg<u32, _BAUDRATE>>
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _CONFIG>>
pub fn paritytype(&mut self) -> PARITYTYPE_W<'_>
pub fn paritytype(&mut self) -> PARITYTYPE_W<'_>
Bit 8 - Even or odd parity type
impl W<u32, Reg<u32, _EVENTS_READY>>
impl W<u32, Reg<u32, _EVENTS_READY>>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
Bit 0 - TXD byte sent and RXD byte received
impl W<u32, Reg<u32, _FREQUENCY>>
impl W<u32, Reg<u32, _FREQUENCY>>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _RXDELAY>>
impl W<u32, Reg<u32, _RXDELAY>>
pub fn rxdelay(&mut self) -> RXDELAY_W<'_>
pub fn rxdelay(&mut self) -> RXDELAY_W<'_>
Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start SPI transaction
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop SPI transaction
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
Bit 0 - Suspend SPI transaction
impl W<u32, Reg<u32, _TASKS_RESUME>>
impl W<u32, Reg<u32, _TASKS_RESUME>>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
Bit 0 - Resume SPI transaction
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - SPI transaction has stopped
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
Bit 0 - End of RXD buffer reached
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - End of RXD buffer and TXD buffer reached
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
Bit 0 - End of TXD buffer reached
impl W<u32, Reg<u32, _EVENTS_STARTED>>
impl W<u32, Reg<u32, _EVENTS_STARTED>>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
Bit 0 - Transaction started
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn end_start(&mut self) -> END_START_W<'_>
pub fn end_start(&mut self) -> END_START_W<'_>
Bit 17 - Shortcut between event END and task START
impl W<u32, Reg<u32, _FREQUENCY>>
impl W<u32, Reg<u32, _FREQUENCY>>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _TASKS_ACQUIRE>>
impl W<u32, Reg<u32, _TASKS_ACQUIRE>>
pub fn tasks_acquire(&mut self) -> TASKS_ACQUIRE_W<'_>
pub fn tasks_acquire(&mut self) -> TASKS_ACQUIRE_W<'_>
Bit 0 - Acquire SPI semaphore
impl W<u32, Reg<u32, _TASKS_RELEASE>>
impl W<u32, Reg<u32, _TASKS_RELEASE>>
pub fn tasks_release(&mut self) -> TASKS_RELEASE_W<'_>
pub fn tasks_release(&mut self) -> TASKS_RELEASE_W<'_>
Bit 0 - Release SPI semaphore, enabling the SPI slave to acquire it
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - Granted transaction completed
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
Bit 0 - End of RXD buffer reached
impl W<u32, Reg<u32, _EVENTS_ACQUIRED>>
impl W<u32, Reg<u32, _EVENTS_ACQUIRED>>
pub fn events_acquired(&mut self) -> EVENTS_ACQUIRED_W<'_>
pub fn events_acquired(&mut self) -> EVENTS_ACQUIRED_W<'_>
Bit 0 - Semaphore acquired
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>
pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>
Bit 2 - Shortcut between event END and task ACQUIRE
impl W<u32, Reg<u32, _STATUS>>
impl W<u32, Reg<u32, _STATUS>>
pub fn overread(&mut self) -> OVERREAD_W<'_>
pub fn overread(&mut self) -> OVERREAD_W<'_>
Bit 0 - TX buffer over-read detected, and prevented
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
Bit 1 - RX buffer overflow detected, and prevented
impl W<u32, Reg<u32, _TASKS_STARTRX>>
impl W<u32, Reg<u32, _TASKS_STARTRX>>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
Bit 0 - Start TWI receive sequence
impl W<u32, Reg<u32, _TASKS_STARTTX>>
impl W<u32, Reg<u32, _TASKS_STARTTX>>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
Bit 0 - Start TWI transmit sequence
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop TWI transaction
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
Bit 0 - Suspend TWI transaction
impl W<u32, Reg<u32, _TASKS_RESUME>>
impl W<u32, Reg<u32, _TASKS_RESUME>>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
Bit 0 - Resume TWI transaction
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - TWI stopped
impl W<u32, Reg<u32, _EVENTS_RXDREADY>>
impl W<u32, Reg<u32, _EVENTS_RXDREADY>>
pub fn events_rxdready(&mut self) -> EVENTS_RXDREADY_W<'_>
pub fn events_rxdready(&mut self) -> EVENTS_RXDREADY_W<'_>
Bit 0 - TWI RXD byte received
impl W<u32, Reg<u32, _EVENTS_TXDSENT>>
impl W<u32, Reg<u32, _EVENTS_TXDSENT>>
pub fn events_txdsent(&mut self) -> EVENTS_TXDSENT_W<'_>
pub fn events_txdsent(&mut self) -> EVENTS_TXDSENT_W<'_>
Bit 0 - TWI TXD byte sent
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - TWI error
impl W<u32, Reg<u32, _EVENTS_BB>>
impl W<u32, Reg<u32, _EVENTS_BB>>
pub fn events_bb(&mut self) -> EVENTS_BB_W<'_>
pub fn events_bb(&mut self) -> EVENTS_BB_W<'_>
Bit 0 - TWI byte boundary, generated before each byte that is sent or received
impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>
impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>
pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>
pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>
Bit 0 - TWI entered the suspended state
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>
pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>
Bit 0 - Shortcut between event BB and task SUSPEND
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event RXDREADY
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event SUSPENDED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event RXDREADY
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event SUSPENDED
impl W<u32, Reg<u32, _FREQUENCY>>
impl W<u32, Reg<u32, _FREQUENCY>>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _TASKS_STARTRX>>
impl W<u32, Reg<u32, _TASKS_STARTRX>>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>
Bit 0 - Start TWI receive sequence
impl W<u32, Reg<u32, _TASKS_STARTTX>>
impl W<u32, Reg<u32, _TASKS_STARTTX>>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
Bit 0 - Start TWI transmit sequence
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop TWI transaction. Must be issued while the TWI master is not suspended.
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
Bit 0 - Suspend TWI transaction
impl W<u32, Reg<u32, _TASKS_RESUME>>
impl W<u32, Reg<u32, _TASKS_RESUME>>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
Bit 0 - Resume TWI transaction
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - TWI stopped
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - TWI error
impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>
impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>
pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>
pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>
Bit 0 - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
Bit 0 - Receive sequence started
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
Bit 0 - Transmit sequence started
impl W<u32, Reg<u32, _EVENTS_LASTRX>>
impl W<u32, Reg<u32, _EVENTS_LASTRX>>
pub fn events_lastrx(&mut self) -> EVENTS_LASTRX_W<'_>
pub fn events_lastrx(&mut self) -> EVENTS_LASTRX_W<'_>
Bit 0 - Byte boundary, starting to receive the last byte
impl W<u32, Reg<u32, _EVENTS_LASTTX>>
impl W<u32, Reg<u32, _EVENTS_LASTTX>>
pub fn events_lasttx(&mut self) -> EVENTS_LASTTX_W<'_>
pub fn events_lasttx(&mut self) -> EVENTS_LASTTX_W<'_>
Bit 0 - Byte boundary, starting to transmit the last byte
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>
pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>
Bit 7 - Shortcut between event LASTTX and task STARTRX
pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>
pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>
Bit 8 - Shortcut between event LASTTX and task SUSPEND
pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>
pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>
Bit 9 - Shortcut between event LASTTX and task STOP
pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>
pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>
Bit 10 - Shortcut between event LASTRX and task STARTTX
pub fn lastrx_suspend(&mut self) -> LASTRX_SUSPEND_W<'_>
pub fn lastrx_suspend(&mut self) -> LASTRX_SUSPEND_W<'_>
Bit 11 - Shortcut between event LASTRX and task SUSPEND
pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>
pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>
Bit 12 - Shortcut between event LASTRX and task STOP
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
Bit 18 - Enable or disable interrupt for event SUSPENDED
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Enable or disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Enable or disable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event SUSPENDED
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event SUSPENDED
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _FREQUENCY>>
impl W<u32, Reg<u32, _FREQUENCY>>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop TWI transaction
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
impl W<u32, Reg<u32, _TASKS_SUSPEND>>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>
Bit 0 - Suspend TWI transaction
impl W<u32, Reg<u32, _TASKS_RESUME>>
impl W<u32, Reg<u32, _TASKS_RESUME>>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>
Bit 0 - Resume TWI transaction
impl W<u32, Reg<u32, _TASKS_PREPARERX>>
impl W<u32, Reg<u32, _TASKS_PREPARERX>>
pub fn tasks_preparerx(&mut self) -> TASKS_PREPARERX_W<'_>
pub fn tasks_preparerx(&mut self) -> TASKS_PREPARERX_W<'_>
Bit 0 - Prepare the TWI slave to respond to a write command
impl W<u32, Reg<u32, _TASKS_PREPARETX>>
impl W<u32, Reg<u32, _TASKS_PREPARETX>>
pub fn tasks_preparetx(&mut self) -> TASKS_PREPARETX_W<'_>
pub fn tasks_preparetx(&mut self) -> TASKS_PREPARETX_W<'_>
Bit 0 - Prepare the TWI slave to respond to a read command
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - TWI stopped
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - TWI error
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>
Bit 0 - Receive sequence started
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>
Bit 0 - Transmit sequence started
impl W<u32, Reg<u32, _EVENTS_WRITE>>
impl W<u32, Reg<u32, _EVENTS_WRITE>>
pub fn events_write(&mut self) -> EVENTS_WRITE_W<'_>
pub fn events_write(&mut self) -> EVENTS_WRITE_W<'_>
Bit 0 - Write command received
impl W<u32, Reg<u32, _EVENTS_READ>>
impl W<u32, Reg<u32, _EVENTS_READ>>
pub fn events_read(&mut self) -> EVENTS_READ_W<'_>
pub fn events_read(&mut self) -> EVENTS_READ_W<'_>
Bit 0 - Read command received
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>
pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>
Bit 13 - Shortcut between event WRITE and task SUSPEND
pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>
pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>
Bit 14 - Shortcut between event READ and task SUSPEND
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Enable or disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Enable or disable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event RXSTARTED
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event TXSTARTED
impl W<u32, Reg<u32, _ERRORSRC>>
impl W<u32, Reg<u32, _ERRORSRC>>
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
Bit 0 - RX buffer overflow detected, and prevented
pub fn overread(&mut self) -> OVERREAD_W<'_>
pub fn overread(&mut self) -> OVERREAD_W<'_>
Bit 3 - TX buffer over-read detected, and prevented
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _CONFIG>>
pub fn address0(&mut self) -> ADDRESS0_W<'_>
pub fn address0(&mut self) -> ADDRESS0_W<'_>
Bit 0 - Enable or disable address matching on ADDRESS[0]
pub fn address1(&mut self) -> ADDRESS1_W<'_>
pub fn address1(&mut self) -> ADDRESS1_W<'_>
Bit 1 - Enable or disable address matching on ADDRESS[1]
impl W<u32, Reg<u32, _RX>>
impl W<u32, Reg<u32, _RX>>
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
Bit 0 - No valid end of frame (EoF) detected
pub fn paritystatus(&mut self) -> PARITYSTATUS_W<'_>
pub fn paritystatus(&mut self) -> PARITYSTATUS_W<'_>
Bit 2 - Parity status of received frame
impl W<u32, Reg<u32, _FRAMECONFIG>>
impl W<u32, Reg<u32, _FRAMECONFIG>>
pub fn discardmode(&mut self) -> DISCARDMODE_W<'_>
pub fn discardmode(&mut self) -> DISCARDMODE_W<'_>
Bit 1 - Discarding unused bits at start or end of a frame
pub fn crcmodetx(&mut self) -> CRCMODETX_W<'_>
pub fn crcmodetx(&mut self) -> CRCMODETX_W<'_>
Bit 4 - CRC mode for outgoing frames
impl W<u32, Reg<u32, _AMOUNT>>
impl W<u32, Reg<u32, _AMOUNT>>
pub fn txdatabits(&mut self) -> TXDATABITS_W<'_>
pub fn txdatabits(&mut self) -> TXDATABITS_W<'_>
Bits 0:2 - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).
pub fn txdatabytes(&mut self) -> TXDATABYTES_W<'_>
pub fn txdatabytes(&mut self) -> TXDATABYTES_W<'_>
Bits 3:11 - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing
impl W<u32, Reg<u32, _TASKS_ACTIVATE>>
impl W<u32, Reg<u32, _TASKS_ACTIVATE>>
pub fn tasks_activate(&mut self) -> TASKS_ACTIVATE_W<'_>
pub fn tasks_activate(&mut self) -> TASKS_ACTIVATE_W<'_>
Bit 0 - Activate NFCT peripheral for incoming and outgoing frames, change state to activated
impl W<u32, Reg<u32, _TASKS_DISABLE>>
impl W<u32, Reg<u32, _TASKS_DISABLE>>
pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W<'_>
pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W<'_>
Bit 0 - Disable NFCT peripheral
impl W<u32, Reg<u32, _TASKS_SENSE>>
impl W<u32, Reg<u32, _TASKS_SENSE>>
pub fn tasks_sense(&mut self) -> TASKS_SENSE_W<'_>
pub fn tasks_sense(&mut self) -> TASKS_SENSE_W<'_>
Bit 0 - Enable NFC sense field mode, change state to sense mode
impl W<u32, Reg<u32, _TASKS_STARTTX>>
impl W<u32, Reg<u32, _TASKS_STARTTX>>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>
Bit 0 - Start transmission of an outgoing frame, change state to transmit
impl W<u32, Reg<u32, _TASKS_ENABLERXDATA>>
impl W<u32, Reg<u32, _TASKS_ENABLERXDATA>>
pub fn tasks_enablerxdata(&mut self) -> TASKS_ENABLERXDATA_W<'_>
pub fn tasks_enablerxdata(&mut self) -> TASKS_ENABLERXDATA_W<'_>
Bit 0 - Initializes the EasyDMA for receive.
impl W<u32, Reg<u32, _TASKS_GOIDLE>>
impl W<u32, Reg<u32, _TASKS_GOIDLE>>
pub fn tasks_goidle(&mut self) -> TASKS_GOIDLE_W<'_>
pub fn tasks_goidle(&mut self) -> TASKS_GOIDLE_W<'_>
Bit 0 - Force state machine to IDLE state
impl W<u32, Reg<u32, _TASKS_GOSLEEP>>
impl W<u32, Reg<u32, _TASKS_GOSLEEP>>
pub fn tasks_gosleep(&mut self) -> TASKS_GOSLEEP_W<'_>
pub fn tasks_gosleep(&mut self) -> TASKS_GOSLEEP_W<'_>
Bit 0 - Force state machine to SLEEP_A state
impl W<u32, Reg<u32, _EVENTS_READY>>
impl W<u32, Reg<u32, _EVENTS_READY>>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
Bit 0 - The NFCT peripheral is ready to receive and send frames
impl W<u32, Reg<u32, _EVENTS_FIELDDETECTED>>
impl W<u32, Reg<u32, _EVENTS_FIELDDETECTED>>
pub fn events_fielddetected(&mut self) -> EVENTS_FIELDDETECTED_W<'_>
pub fn events_fielddetected(&mut self) -> EVENTS_FIELDDETECTED_W<'_>
Bit 0 - Remote NFC field detected
impl W<u32, Reg<u32, _EVENTS_FIELDLOST>>
impl W<u32, Reg<u32, _EVENTS_FIELDLOST>>
pub fn events_fieldlost(&mut self) -> EVENTS_FIELDLOST_W<'_>
pub fn events_fieldlost(&mut self) -> EVENTS_FIELDLOST_W<'_>
Bit 0 - Remote NFC field lost
impl W<u32, Reg<u32, _EVENTS_TXFRAMESTART>>
impl W<u32, Reg<u32, _EVENTS_TXFRAMESTART>>
pub fn events_txframestart(&mut self) -> EVENTS_TXFRAMESTART_W<'_>
pub fn events_txframestart(&mut self) -> EVENTS_TXFRAMESTART_W<'_>
Bit 0 - Marks the start of the first symbol of a transmitted frame
impl W<u32, Reg<u32, _EVENTS_TXFRAMEEND>>
impl W<u32, Reg<u32, _EVENTS_TXFRAMEEND>>
pub fn events_txframeend(&mut self) -> EVENTS_TXFRAMEEND_W<'_>
pub fn events_txframeend(&mut self) -> EVENTS_TXFRAMEEND_W<'_>
Bit 0 - Marks the end of the last transmitted on-air symbol of a frame
impl W<u32, Reg<u32, _EVENTS_RXFRAMESTART>>
impl W<u32, Reg<u32, _EVENTS_RXFRAMESTART>>
pub fn events_rxframestart(&mut self) -> EVENTS_RXFRAMESTART_W<'_>
pub fn events_rxframestart(&mut self) -> EVENTS_RXFRAMESTART_W<'_>
Bit 0 - Marks the end of the first symbol of a received frame
impl W<u32, Reg<u32, _EVENTS_RXFRAMEEND>>
impl W<u32, Reg<u32, _EVENTS_RXFRAMEEND>>
pub fn events_rxframeend(&mut self) -> EVENTS_RXFRAMEEND_W<'_>
pub fn events_rxframeend(&mut self) -> EVENTS_RXFRAMEEND_W<'_>
Bit 0 - Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - NFC error reported. The ERRORSTATUS register contains details on the source of the error.
impl W<u32, Reg<u32, _EVENTS_RXERROR>>
impl W<u32, Reg<u32, _EVENTS_RXERROR>>
pub fn events_rxerror(&mut self) -> EVENTS_RXERROR_W<'_>
pub fn events_rxerror(&mut self) -> EVENTS_RXERROR_W<'_>
Bit 0 - NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
impl W<u32, Reg<u32, _EVENTS_ENDRX>>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>
Bit 0 - RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
impl W<u32, Reg<u32, _EVENTS_ENDTX>>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>
Bit 0 - Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
impl W<u32, Reg<u32, _EVENTS_AUTOCOLRESSTARTED>>
impl W<u32, Reg<u32, _EVENTS_AUTOCOLRESSTARTED>>
pub fn events_autocolresstarted(&mut self) -> EVENTS_AUTOCOLRESSTARTED_W<'_>
pub fn events_autocolresstarted(&mut self) -> EVENTS_AUTOCOLRESSTARTED_W<'_>
Bit 0 - Auto collision resolution process has started
impl W<u32, Reg<u32, _EVENTS_COLLISION>>
impl W<u32, Reg<u32, _EVENTS_COLLISION>>
pub fn events_collision(&mut self) -> EVENTS_COLLISION_W<'_>
pub fn events_collision(&mut self) -> EVENTS_COLLISION_W<'_>
Bit 0 - NFC auto collision resolution error reported.
impl W<u32, Reg<u32, _EVENTS_SELECTED>>
impl W<u32, Reg<u32, _EVENTS_SELECTED>>
pub fn events_selected(&mut self) -> EVENTS_SELECTED_W<'_>
pub fn events_selected(&mut self) -> EVENTS_SELECTED_W<'_>
Bit 0 - NFC auto collision resolution successfully completed
impl W<u32, Reg<u32, _EVENTS_STARTED>>
impl W<u32, Reg<u32, _EVENTS_STARTED>>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
Bit 0 - EasyDMA is ready to receive or send frames.
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn fielddetected_activate(&mut self) -> FIELDDETECTED_ACTIVATE_W<'_>
pub fn fielddetected_activate(&mut self) -> FIELDDETECTED_ACTIVATE_W<'_>
Bit 0 - Shortcut between event FIELDDETECTED and task ACTIVATE
pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W<'_>
pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W<'_>
Bit 1 - Shortcut between event FIELDLOST and task SENSE
pub fn txframeend_enablerxdata(&mut self) -> TXFRAMEEND_ENABLERXDATA_W<'_>
pub fn txframeend_enablerxdata(&mut self) -> TXFRAMEEND_ENABLERXDATA_W<'_>
Bit 5 - Shortcut between event TXFRAMEEND and task ENABLERXDATA
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
Bit 1 - Enable or disable interrupt for event FIELDDETECTED
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
Bit 2 - Enable or disable interrupt for event FIELDLOST
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
Bit 3 - Enable or disable interrupt for event TXFRAMESTART
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
Bit 4 - Enable or disable interrupt for event TXFRAMEEND
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
Bit 5 - Enable or disable interrupt for event RXFRAMESTART
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
Bit 6 - Enable or disable interrupt for event RXFRAMEEND
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
Bit 14 - Enable or disable interrupt for event AUTOCOLRESSTARTED
pub fn collision(&mut self) -> COLLISION_W<'_>
pub fn collision(&mut self) -> COLLISION_W<'_>
Bit 18 - Enable or disable interrupt for event COLLISION
pub fn selected(&mut self) -> SELECTED_W<'_>
pub fn selected(&mut self) -> SELECTED_W<'_>
Bit 19 - Enable or disable interrupt for event SELECTED
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event FIELDDETECTED
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event FIELDLOST
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event TXFRAMESTART
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event TXFRAMEEND
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event RXFRAMESTART
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event RXFRAMEEND
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
Bit 14 - Write ‘1’ to enable interrupt for event AUTOCOLRESSTARTED
pub fn collision(&mut self) -> COLLISION_W<'_>
pub fn collision(&mut self) -> COLLISION_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event COLLISION
pub fn selected(&mut self) -> SELECTED_W<'_>
pub fn selected(&mut self) -> SELECTED_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event SELECTED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event FIELDDETECTED
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event FIELDLOST
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event TXFRAMESTART
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event TXFRAMEEND
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event RXFRAMESTART
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event RXFRAMEEND
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
Bit 14 - Write ‘1’ to disable interrupt for event AUTOCOLRESSTARTED
pub fn collision(&mut self) -> COLLISION_W<'_>
pub fn collision(&mut self) -> COLLISION_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event COLLISION
pub fn selected(&mut self) -> SELECTED_W<'_>
pub fn selected(&mut self) -> SELECTED_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event SELECTED
impl W<u32, Reg<u32, _ERRORSTATUS>>
impl W<u32, Reg<u32, _ERRORSTATUS>>
pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W<'_>
pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W<'_>
Bit 0 - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
impl W<u32, Reg<u32, _FRAMEDELAYMIN>>
impl W<u32, Reg<u32, _FRAMEDELAYMIN>>
pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W<'_>
pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W<'_>
Bits 0:15 - Minimum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMAX>>
impl W<u32, Reg<u32, _FRAMEDELAYMAX>>
pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W<'_>
pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W<'_>
Bits 0:19 - Maximum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMODE>>
impl W<u32, Reg<u32, _FRAMEDELAYMODE>>
pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W<'_>
pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W<'_>
Bits 0:1 - Configuration register for the Frame Delay Timer
impl W<u32, Reg<u32, _MODULATIONCTRL>>
impl W<u32, Reg<u32, _MODULATIONCTRL>>
pub fn modulationctrl(&mut self) -> MODULATIONCTRL_W<'_>
pub fn modulationctrl(&mut self) -> MODULATIONCTRL_W<'_>
Bits 0:1 - Configuration of modulation control.
impl W<u32, Reg<u32, _NFCID1_LAST>>
impl W<u32, Reg<u32, _NFCID1_LAST>>
pub fn nfcid1_z(&mut self) -> NFCID1_Z_W<'_>
pub fn nfcid1_z(&mut self) -> NFCID1_Z_W<'_>
Bits 0:7 - NFCID1 byte Z (very last byte sent)
pub fn nfcid1_y(&mut self) -> NFCID1_Y_W<'_>
pub fn nfcid1_y(&mut self) -> NFCID1_Y_W<'_>
Bits 8:15 - NFCID1 byte Y
pub fn nfcid1_x(&mut self) -> NFCID1_X_W<'_>
pub fn nfcid1_x(&mut self) -> NFCID1_X_W<'_>
Bits 16:23 - NFCID1 byte X
pub fn nfcid1_w(&mut self) -> NFCID1_W_W<'_>
pub fn nfcid1_w(&mut self) -> NFCID1_W_W<'_>
Bits 24:31 - NFCID1 byte W
impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>
impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>
pub fn nfcid1_v(&mut self) -> NFCID1_V_W<'_>
pub fn nfcid1_v(&mut self) -> NFCID1_V_W<'_>
Bits 0:7 - NFCID1 byte V
pub fn nfcid1_u(&mut self) -> NFCID1_U_W<'_>
pub fn nfcid1_u(&mut self) -> NFCID1_U_W<'_>
Bits 8:15 - NFCID1 byte U
pub fn nfcid1_t(&mut self) -> NFCID1_T_W<'_>
pub fn nfcid1_t(&mut self) -> NFCID1_T_W<'_>
Bits 16:23 - NFCID1 byte T
impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>
impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>
pub fn nfcid1_s(&mut self) -> NFCID1_S_W<'_>
pub fn nfcid1_s(&mut self) -> NFCID1_S_W<'_>
Bits 0:7 - NFCID1 byte S
pub fn nfcid1_r(&mut self) -> NFCID1_R_W<'_>
pub fn nfcid1_r(&mut self) -> NFCID1_R_W<'_>
Bits 8:15 - NFCID1 byte R
pub fn nfcid1_q(&mut self) -> NFCID1_Q_W<'_>
pub fn nfcid1_q(&mut self) -> NFCID1_Q_W<'_>
Bits 16:23 - NFCID1 byte Q
impl W<u32, Reg<u32, _SENSRES>>
impl W<u32, Reg<u32, _SENSRES>>
pub fn bitframesdd(&mut self) -> BITFRAMESDD_W<'_>
pub fn bitframesdd(&mut self) -> BITFRAMESDD_W<'_>
Bits 0:4 - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
pub fn nfcidsize(&mut self) -> NFCIDSIZE_W<'_>
pub fn nfcidsize(&mut self) -> NFCIDSIZE_W<'_>
Bits 6:7 - NFCID1 size. This value is used by the auto collision resolution engine.
pub fn platfconfig(&mut self) -> PLATFCONFIG_W<'_>
pub fn platfconfig(&mut self) -> PLATFCONFIG_W<'_>
Bits 8:11 - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
impl W<u32, Reg<u32, _SELRES>>
impl W<u32, Reg<u32, _SELRES>>
pub fn cascade(&mut self) -> CASCADE_W<'_>
pub fn cascade(&mut self) -> CASCADE_W<'_>
Bit 2 - Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)
pub fn protocol(&mut self) -> PROTOCOL_W<'_>
pub fn protocol(&mut self) -> PROTOCOL_W<'_>
Bits 5:6 - Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
impl W<u32, Reg<u32, _TASKS_OUT>>
impl W<u32, Reg<u32, _TASKS_OUT>>
pub fn tasks_out(&mut self) -> TASKS_OUT_W<'_>
pub fn tasks_out(&mut self) -> TASKS_OUT_W<'_>
Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
impl W<u32, Reg<u32, _TASKS_SET>>
impl W<u32, Reg<u32, _TASKS_SET>>
pub fn tasks_set(&mut self) -> TASKS_SET_W<'_>
pub fn tasks_set(&mut self) -> TASKS_SET_W<'_>
Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
impl W<u32, Reg<u32, _TASKS_CLR>>
impl W<u32, Reg<u32, _TASKS_CLR>>
pub fn tasks_clr(&mut self) -> TASKS_CLR_W<'_>
pub fn tasks_clr(&mut self) -> TASKS_CLR_W<'_>
Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
impl W<u32, Reg<u32, _EVENTS_IN>>
impl W<u32, Reg<u32, _EVENTS_IN>>
pub fn events_in(&mut self) -> EVENTS_IN_W<'_>
pub fn events_in(&mut self) -> EVENTS_IN_W<'_>
Bit 0 - Event generated from pin specified in CONFIG[n].PSEL
impl W<u32, Reg<u32, _EVENTS_PORT>>
impl W<u32, Reg<u32, _EVENTS_PORT>>
pub fn events_port(&mut self) -> EVENTS_PORT_W<'_>
pub fn events_port(&mut self) -> EVENTS_PORT_W<'_>
Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _CONFIG>>
pub fn psel(&mut self) -> PSEL_W<'_>
pub fn psel(&mut self) -> PSEL_W<'_>
Bits 8:12 - GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
pub fn polarity(&mut self) -> POLARITY_W<'_>
pub fn polarity(&mut self) -> POLARITY_W<'_>
Bits 16:17 - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _CONFIG>>
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Starts the SAADC and prepares the result buffer in RAM
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
Bit 0 - Takes one SAADC sample
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stops the SAADC and terminates all on-going conversions
impl W<u32, Reg<u32, _TASKS_CALIBRATEOFFSET>>
impl W<u32, Reg<u32, _TASKS_CALIBRATEOFFSET>>
pub fn tasks_calibrateoffset(&mut self) -> TASKS_CALIBRATEOFFSET_W<'_>
pub fn tasks_calibrateoffset(&mut self) -> TASKS_CALIBRATEOFFSET_W<'_>
Bit 0 - Starts offset auto-calibration
impl W<u32, Reg<u32, _EVENTS_STARTED>>
impl W<u32, Reg<u32, _EVENTS_STARTED>>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
Bit 0 - The SAADC has started
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - The SAADC has filled up the result buffer
impl W<u32, Reg<u32, _EVENTS_DONE>>
impl W<u32, Reg<u32, _EVENTS_DONE>>
pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>
pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>
Bit 0 - A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
impl W<u32, Reg<u32, _EVENTS_RESULTDONE>>
impl W<u32, Reg<u32, _EVENTS_RESULTDONE>>
pub fn events_resultdone(&mut self) -> EVENTS_RESULTDONE_W<'_>
pub fn events_resultdone(&mut self) -> EVENTS_RESULTDONE_W<'_>
Bit 0 - Result ready for transfer to RAM
impl W<u32, Reg<u32, _EVENTS_CALIBRATEDONE>>
impl W<u32, Reg<u32, _EVENTS_CALIBRATEDONE>>
pub fn events_calibratedone(&mut self) -> EVENTS_CALIBRATEDONE_W<'_>
pub fn events_calibratedone(&mut self) -> EVENTS_CALIBRATEDONE_W<'_>
Bit 0 - Calibration is complete
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - The SAADC has stopped
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
Bit 3 - Enable or disable interrupt for event RESULTDONE
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
Bit 4 - Enable or disable interrupt for event CALIBRATEDONE
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
Bit 6 - Enable or disable interrupt for event CH0LIMITH
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
Bit 7 - Enable or disable interrupt for event CH0LIMITL
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
Bit 8 - Enable or disable interrupt for event CH1LIMITH
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
Bit 9 - Enable or disable interrupt for event CH1LIMITL
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
Bit 10 - Enable or disable interrupt for event CH2LIMITH
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
Bit 11 - Enable or disable interrupt for event CH2LIMITL
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
Bit 12 - Enable or disable interrupt for event CH3LIMITH
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
Bit 13 - Enable or disable interrupt for event CH3LIMITL
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
Bit 14 - Enable or disable interrupt for event CH4LIMITH
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
Bit 15 - Enable or disable interrupt for event CH4LIMITL
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
Bit 16 - Enable or disable interrupt for event CH5LIMITH
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
Bit 17 - Enable or disable interrupt for event CH5LIMITL
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
Bit 18 - Enable or disable interrupt for event CH6LIMITH
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
Bit 19 - Enable or disable interrupt for event CH6LIMITL
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
Bit 20 - Enable or disable interrupt for event CH7LIMITH
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
Bit 21 - Enable or disable interrupt for event CH7LIMITL
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event RESULTDONE
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event CALIBRATEDONE
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event CH0LIMITH
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event CH0LIMITL
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
Bit 8 - Write ‘1’ to enable interrupt for event CH1LIMITH
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
Bit 9 - Write ‘1’ to enable interrupt for event CH1LIMITL
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
Bit 10 - Write ‘1’ to enable interrupt for event CH2LIMITH
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
Bit 11 - Write ‘1’ to enable interrupt for event CH2LIMITL
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
Bit 12 - Write ‘1’ to enable interrupt for event CH3LIMITH
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
Bit 13 - Write ‘1’ to enable interrupt for event CH3LIMITL
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
Bit 14 - Write ‘1’ to enable interrupt for event CH4LIMITH
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
Bit 15 - Write ‘1’ to enable interrupt for event CH4LIMITL
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
Bit 16 - Write ‘1’ to enable interrupt for event CH5LIMITH
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
Bit 17 - Write ‘1’ to enable interrupt for event CH5LIMITL
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event CH6LIMITH
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event CH6LIMITL
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event CH7LIMITH
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
Bit 21 - Write ‘1’ to enable interrupt for event CH7LIMITL
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event RESULTDONE
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event CALIBRATEDONE
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event CH0LIMITH
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event CH0LIMITL
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
Bit 8 - Write ‘1’ to disable interrupt for event CH1LIMITH
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
Bit 9 - Write ‘1’ to disable interrupt for event CH1LIMITL
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
Bit 10 - Write ‘1’ to disable interrupt for event CH2LIMITH
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
Bit 11 - Write ‘1’ to disable interrupt for event CH2LIMITL
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
Bit 12 - Write ‘1’ to disable interrupt for event CH3LIMITH
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
Bit 13 - Write ‘1’ to disable interrupt for event CH3LIMITL
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
Bit 14 - Write ‘1’ to disable interrupt for event CH4LIMITH
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
Bit 15 - Write ‘1’ to disable interrupt for event CH4LIMITL
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
Bit 16 - Write ‘1’ to disable interrupt for event CH5LIMITH
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
Bit 17 - Write ‘1’ to disable interrupt for event CH5LIMITL
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event CH6LIMITH
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event CH6LIMITL
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event CH7LIMITH
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
Bit 21 - Write ‘1’ to disable interrupt for event CH7LIMITL
impl W<u32, Reg<u32, _OVERSAMPLE>>
impl W<u32, Reg<u32, _OVERSAMPLE>>
pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>
pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>
Bits 0:3 - Oversample control
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start Timer
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop Timer
impl W<u32, Reg<u32, _TASKS_COUNT>>
impl W<u32, Reg<u32, _TASKS_COUNT>>
pub fn tasks_count(&mut self) -> TASKS_COUNT_W<'_>
pub fn tasks_count(&mut self) -> TASKS_COUNT_W<'_>
Bit 0 - Increment Timer (Counter mode only)
impl W<u32, Reg<u32, _TASKS_CLEAR>>
impl W<u32, Reg<u32, _TASKS_CLEAR>>
pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>
pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>
Bit 0 - Clear time
impl W<u32, Reg<u32, _TASKS_SHUTDOWN>>
impl W<u32, Reg<u32, _TASKS_SHUTDOWN>>
pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W<'_>
pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W<'_>
Bit 0 - Deprecated field - Shut down timer
impl W<u32, Reg<u32, _TASKS_CAPTURE>>
impl W<u32, Reg<u32, _TASKS_CAPTURE>>
pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W<'_>
pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W<'_>
Bit 0 - Capture Timer value to CC[n] register
impl W<u32, Reg<u32, _EVENTS_COMPARE>>
impl W<u32, Reg<u32, _EVENTS_COMPARE>>
pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>
pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>
Bit 0 - Compare event on CC[n] match
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
Bit 0 - Shortcut between event COMPARE[0] and task CLEAR
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
Bit 1 - Shortcut between event COMPARE[1] and task CLEAR
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
Bit 2 - Shortcut between event COMPARE[2] and task CLEAR
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
Bit 3 - Shortcut between event COMPARE[3] and task CLEAR
pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>
pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>
Bit 4 - Shortcut between event COMPARE[4] and task CLEAR
pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>
pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>
Bit 5 - Shortcut between event COMPARE[5] and task CLEAR
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
Bit 8 - Shortcut between event COMPARE[0] and task STOP
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
Bit 9 - Shortcut between event COMPARE[1] and task STOP
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
Bit 10 - Shortcut between event COMPARE[2] and task STOP
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
Bit 11 - Shortcut between event COMPARE[3] and task STOP
pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>
pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>
Bit 12 - Shortcut between event COMPARE[4] and task STOP
pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>
pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>
Bit 13 - Shortcut between event COMPARE[5] and task STOP
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to enable interrupt for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to enable interrupt for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event COMPARE[3]
pub fn compare4(&mut self) -> COMPARE4_W<'_>
pub fn compare4(&mut self) -> COMPARE4_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event COMPARE[4]
pub fn compare5(&mut self) -> COMPARE5_W<'_>
pub fn compare5(&mut self) -> COMPARE5_W<'_>
Bit 21 - Write ‘1’ to enable interrupt for event COMPARE[5]
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to disable interrupt for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to disable interrupt for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event COMPARE[3]
pub fn compare4(&mut self) -> COMPARE4_W<'_>
pub fn compare4(&mut self) -> COMPARE4_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event COMPARE[4]
pub fn compare5(&mut self) -> COMPARE5_W<'_>
pub fn compare5(&mut self) -> COMPARE5_W<'_>
Bit 21 - Write ‘1’ to disable interrupt for event COMPARE[5]
impl W<u32, Reg<u32, _PRESCALER>>
impl W<u32, Reg<u32, _PRESCALER>>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
Bits 0:3 - Prescaler value
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start RTC COUNTER
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop RTC COUNTER
impl W<u32, Reg<u32, _TASKS_CLEAR>>
impl W<u32, Reg<u32, _TASKS_CLEAR>>
pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>
pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>
Bit 0 - Clear RTC COUNTER
impl W<u32, Reg<u32, _TASKS_TRIGOVRFLW>>
impl W<u32, Reg<u32, _TASKS_TRIGOVRFLW>>
pub fn tasks_trigovrflw(&mut self) -> TASKS_TRIGOVRFLW_W<'_>
pub fn tasks_trigovrflw(&mut self) -> TASKS_TRIGOVRFLW_W<'_>
Bit 0 - Set COUNTER to 0xFFFFF0
impl W<u32, Reg<u32, _EVENTS_TICK>>
impl W<u32, Reg<u32, _EVENTS_TICK>>
pub fn events_tick(&mut self) -> EVENTS_TICK_W<'_>
pub fn events_tick(&mut self) -> EVENTS_TICK_W<'_>
Bit 0 - Event on COUNTER increment
impl W<u32, Reg<u32, _EVENTS_OVRFLW>>
impl W<u32, Reg<u32, _EVENTS_OVRFLW>>
pub fn events_ovrflw(&mut self) -> EVENTS_OVRFLW_W<'_>
pub fn events_ovrflw(&mut self) -> EVENTS_OVRFLW_W<'_>
Bit 0 - Event on COUNTER overflow
impl W<u32, Reg<u32, _EVENTS_COMPARE>>
impl W<u32, Reg<u32, _EVENTS_COMPARE>>
pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>
pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>
Bit 0 - Compare event on CC[n] match
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to enable interrupt for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to enable interrupt for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event COMPARE[3]
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to disable interrupt for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to disable interrupt for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event COMPARE[3]
impl W<u32, Reg<u32, _EVTEN>>
impl W<u32, Reg<u32, _EVTEN>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Enable or disable event routing for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Enable or disable event routing for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Enable or disable event routing for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Enable or disable event routing for event COMPARE[3]
impl W<u32, Reg<u32, _EVTENSET>>
impl W<u32, Reg<u32, _EVTENSET>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to enable event routing for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to enable event routing for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to enable event routing for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to enable event routing for event COMPARE[3]
impl W<u32, Reg<u32, _EVTENCLR>>
impl W<u32, Reg<u32, _EVTENCLR>>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
pub fn compare0(&mut self) -> COMPARE0_W<'_>
Bit 16 - Write ‘1’ to disable event routing for event COMPARE[0]
pub fn compare1(&mut self) -> COMPARE1_W<'_>
pub fn compare1(&mut self) -> COMPARE1_W<'_>
Bit 17 - Write ‘1’ to disable event routing for event COMPARE[1]
pub fn compare2(&mut self) -> COMPARE2_W<'_>
pub fn compare2(&mut self) -> COMPARE2_W<'_>
Bit 18 - Write ‘1’ to disable event routing for event COMPARE[2]
pub fn compare3(&mut self) -> COMPARE3_W<'_>
pub fn compare3(&mut self) -> COMPARE3_W<'_>
Bit 19 - Write ‘1’ to disable event routing for event COMPARE[3]
impl W<u32, Reg<u32, _PRESCALER>>
impl W<u32, Reg<u32, _PRESCALER>>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
Bits 0:11 - Prescaler value
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start temperature measurement
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop temperature measurement
impl W<u32, Reg<u32, _EVENTS_DATARDY>>
impl W<u32, Reg<u32, _EVENTS_DATARDY>>
pub fn events_datardy(&mut self) -> EVENTS_DATARDY_W<'_>
pub fn events_datardy(&mut self) -> EVENTS_DATARDY_W<'_>
Bit 0 - Temperature measurement complete, data ready
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Task starting the random number generator
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Task stopping the random number generator
impl W<u32, Reg<u32, _EVENTS_VALRDY>>
impl W<u32, Reg<u32, _EVENTS_VALRDY>>
pub fn events_valrdy(&mut self) -> EVENTS_VALRDY_W<'_>
pub fn events_valrdy(&mut self) -> EVENTS_VALRDY_W<'_>
Bit 0 - Event being generated for every new random number written to the VALUE register
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>
pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>
Bit 0 - Shortcut between event VALRDY and task STOP
impl W<u32, Reg<u32, _TASKS_STARTECB>>
impl W<u32, Reg<u32, _TASKS_STARTECB>>
pub fn tasks_startecb(&mut self) -> TASKS_STARTECB_W<'_>
pub fn tasks_startecb(&mut self) -> TASKS_STARTECB_W<'_>
Bit 0 - Start ECB block encrypt
impl W<u32, Reg<u32, _TASKS_STOPECB>>
impl W<u32, Reg<u32, _TASKS_STOPECB>>
pub fn tasks_stopecb(&mut self) -> TASKS_STOPECB_W<'_>
pub fn tasks_stopecb(&mut self) -> TASKS_STOPECB_W<'_>
Bit 0 - Abort a possible executing ECB operation
impl W<u32, Reg<u32, _EVENTS_ENDECB>>
impl W<u32, Reg<u32, _EVENTS_ENDECB>>
pub fn events_endecb(&mut self) -> EVENTS_ENDECB_W<'_>
pub fn events_endecb(&mut self) -> EVENTS_ENDECB_W<'_>
Bit 0 - ECB block encrypt complete
impl W<u32, Reg<u32, _EVENTS_ERRORECB>>
impl W<u32, Reg<u32, _EVENTS_ERRORECB>>
pub fn events_errorecb(&mut self) -> EVENTS_ERRORECB_W<'_>
pub fn events_errorecb(&mut self) -> EVENTS_ERRORECB_W<'_>
Bit 0 - ECB block encrypt aborted because of a STOPECB task or due to an error
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event ERRORECB
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event ERRORECB
impl W<u32, Reg<u32, _ECBDATAPTR>>
impl W<u32, Reg<u32, _ECBDATAPTR>>
pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>
pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>
Bits 0:31 - Pointer to the ECB data structure (see Table 1 ECB data structure overview)
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start resolving addresses based on IRKs specified in the IRK data structure
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop resolving addresses
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - Address resolution procedure complete
impl W<u32, Reg<u32, _EVENTS_RESOLVED>>
impl W<u32, Reg<u32, _EVENTS_RESOLVED>>
pub fn events_resolved(&mut self) -> EVENTS_RESOLVED_W<'_>
pub fn events_resolved(&mut self) -> EVENTS_RESOLVED_W<'_>
Bit 0 - Address resolved
impl W<u32, Reg<u32, _EVENTS_NOTRESOLVED>>
impl W<u32, Reg<u32, _EVENTS_NOTRESOLVED>>
pub fn events_notresolved(&mut self) -> EVENTS_NOTRESOLVED_W<'_>
pub fn events_notresolved(&mut self) -> EVENTS_NOTRESOLVED_W<'_>
Bit 0 - Address not resolved
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn resolved(&mut self) -> RESOLVED_W<'_>
pub fn resolved(&mut self) -> RESOLVED_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event RESOLVED
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event NOTRESOLVED
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn resolved(&mut self) -> RESOLVED_W<'_>
pub fn resolved(&mut self) -> RESOLVED_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event RESOLVED
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event NOTRESOLVED
impl W<u32, Reg<u32, _SCRATCHPTR>>
impl W<u32, Reg<u32, _SCRATCHPTR>>
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
Bits 0:31 - Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
impl W<u32, Reg<u32, _TASKS_KSGEN>>
impl W<u32, Reg<u32, _TASKS_KSGEN>>
pub fn tasks_ksgen(&mut self) -> TASKS_KSGEN_W<'_>
pub fn tasks_ksgen(&mut self) -> TASKS_KSGEN_W<'_>
Bit 0 - Start generation of key-stream. This operation will stop by itself when completed.
impl W<u32, Reg<u32, _TASKS_CRYPT>>
impl W<u32, Reg<u32, _TASKS_CRYPT>>
pub fn tasks_crypt(&mut self) -> TASKS_CRYPT_W<'_>
pub fn tasks_crypt(&mut self) -> TASKS_CRYPT_W<'_>
Bit 0 - Start encryption/decryption. This operation will stop by itself when completed.
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop encryption/decryption
impl W<u32, Reg<u32, _TASKS_RATEOVERRIDE>>
impl W<u32, Reg<u32, _TASKS_RATEOVERRIDE>>
pub fn tasks_rateoverride(&mut self) -> TASKS_RATEOVERRIDE_W<'_>
pub fn tasks_rateoverride(&mut self) -> TASKS_RATEOVERRIDE_W<'_>
Bit 0 - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
impl W<u32, Reg<u32, _EVENTS_ENDKSGEN>>
impl W<u32, Reg<u32, _EVENTS_ENDKSGEN>>
pub fn events_endksgen(&mut self) -> EVENTS_ENDKSGEN_W<'_>
pub fn events_endksgen(&mut self) -> EVENTS_ENDKSGEN_W<'_>
Bit 0 - Key-stream generation complete
impl W<u32, Reg<u32, _EVENTS_ENDCRYPT>>
impl W<u32, Reg<u32, _EVENTS_ENDCRYPT>>
pub fn events_endcrypt(&mut self) -> EVENTS_ENDCRYPT_W<'_>
pub fn events_endcrypt(&mut self) -> EVENTS_ENDCRYPT_W<'_>
Bit 0 - Encrypt/decrypt complete
impl W<u32, Reg<u32, _EVENTS_ERROR>>
impl W<u32, Reg<u32, _EVENTS_ERROR>>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>
Bit 0 - Deprecated field - CCM error event
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>
pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>
Bit 0 - Shortcut between event ENDKSGEN and task CRYPT
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event ENDKSGEN
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event ENDCRYPT
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event ENDKSGEN
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event ENDCRYPT
impl W<u32, Reg<u32, _MODE>>
impl W<u32, Reg<u32, _MODE>>
pub fn mode(&mut self) -> MODE_W<'_>
pub fn mode(&mut self) -> MODE_W<'_>
Bit 0 - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.
pub fn datarate(&mut self) -> DATARATE_W<'_>
pub fn datarate(&mut self) -> DATARATE_W<'_>
Bits 16:17 - Radio data rate that the CCM shall run synchronous with
impl W<u32, Reg<u32, _SCRATCHPTR>>
impl W<u32, Reg<u32, _SCRATCHPTR>>
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
Bits 0:31 - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
impl W<u32, Reg<u32, _MAXPACKETSIZE>>
impl W<u32, Reg<u32, _MAXPACKETSIZE>>
pub fn maxpacketsize(&mut self) -> MAXPACKETSIZE_W<'_>
pub fn maxpacketsize(&mut self) -> MAXPACKETSIZE_W<'_>
Bits 0:7 - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.
impl W<u32, Reg<u32, _RATEOVERRIDE>>
impl W<u32, Reg<u32, _RATEOVERRIDE>>
pub fn rateoverride(&mut self) -> RATEOVERRIDE_W<'_>
pub fn rateoverride(&mut self) -> RATEOVERRIDE_W<'_>
Bits 0:1 - Data rate override setting.
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start the watchdog
impl W<u32, Reg<u32, _EVENTS_TIMEOUT>>
impl W<u32, Reg<u32, _EVENTS_TIMEOUT>>
pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W<'_>
pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W<'_>
Bit 0 - Watchdog timeout
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Task starting the quadrature decoder
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Task stopping the quadrature decoder
impl W<u32, Reg<u32, _TASKS_READCLRACC>>
impl W<u32, Reg<u32, _TASKS_READCLRACC>>
pub fn tasks_readclracc(&mut self) -> TASKS_READCLRACC_W<'_>
pub fn tasks_readclracc(&mut self) -> TASKS_READCLRACC_W<'_>
Bit 0 - Read and clear ACC and ACCDBL
impl W<u32, Reg<u32, _TASKS_RDCLRACC>>
impl W<u32, Reg<u32, _TASKS_RDCLRACC>>
pub fn tasks_rdclracc(&mut self) -> TASKS_RDCLRACC_W<'_>
pub fn tasks_rdclracc(&mut self) -> TASKS_RDCLRACC_W<'_>
Bit 0 - Read and clear ACC
impl W<u32, Reg<u32, _TASKS_RDCLRDBL>>
impl W<u32, Reg<u32, _TASKS_RDCLRDBL>>
pub fn tasks_rdclrdbl(&mut self) -> TASKS_RDCLRDBL_W<'_>
pub fn tasks_rdclrdbl(&mut self) -> TASKS_RDCLRDBL_W<'_>
Bit 0 - Read and clear ACCDBL
impl W<u32, Reg<u32, _EVENTS_SAMPLERDY>>
impl W<u32, Reg<u32, _EVENTS_SAMPLERDY>>
pub fn events_samplerdy(&mut self) -> EVENTS_SAMPLERDY_W<'_>
pub fn events_samplerdy(&mut self) -> EVENTS_SAMPLERDY_W<'_>
Bit 0 - Event being generated for every new sample value written to the SAMPLE register
impl W<u32, Reg<u32, _EVENTS_REPORTRDY>>
impl W<u32, Reg<u32, _EVENTS_REPORTRDY>>
pub fn events_reportrdy(&mut self) -> EVENTS_REPORTRDY_W<'_>
pub fn events_reportrdy(&mut self) -> EVENTS_REPORTRDY_W<'_>
Bit 0 - Non-null report ready
impl W<u32, Reg<u32, _EVENTS_ACCOF>>
impl W<u32, Reg<u32, _EVENTS_ACCOF>>
pub fn events_accof(&mut self) -> EVENTS_ACCOF_W<'_>
pub fn events_accof(&mut self) -> EVENTS_ACCOF_W<'_>
Bit 0 - ACC or ACCDBL register overflow
impl W<u32, Reg<u32, _EVENTS_DBLRDY>>
impl W<u32, Reg<u32, _EVENTS_DBLRDY>>
pub fn events_dblrdy(&mut self) -> EVENTS_DBLRDY_W<'_>
pub fn events_dblrdy(&mut self) -> EVENTS_DBLRDY_W<'_>
Bit 0 - Double displacement(s) detected
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - QDEC has been stopped
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>
pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>
Bit 0 - Shortcut between event REPORTRDY and task READCLRACC
pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>
pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>
Bit 1 - Shortcut between event SAMPLERDY and task STOP
pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>
pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>
Bit 2 - Shortcut between event REPORTRDY and task RDCLRACC
pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>
pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>
Bit 3 - Shortcut between event REPORTRDY and task STOP
pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>
pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>
Bit 4 - Shortcut between event DBLRDY and task RDCLRDBL
pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>
pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>
Bit 5 - Shortcut between event DBLRDY and task STOP
pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>
pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>
Bit 6 - Shortcut between event SAMPLERDY and task READCLRACC
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event SAMPLERDY
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event REPORTRDY
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event SAMPLERDY
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event REPORTRDY
impl W<u32, Reg<u32, _SAMPLEPER>>
impl W<u32, Reg<u32, _SAMPLEPER>>
pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>
pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>
Bits 0:3 - Sample period. The SAMPLE register will be updated for every new sample
impl W<u32, Reg<u32, _REPORTPER>>
impl W<u32, Reg<u32, _REPORTPER>>
pub fn reportper(&mut self) -> REPORTPER_W<'_>
pub fn reportper(&mut self) -> REPORTPER_W<'_>
Bits 0:3 - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start comparator
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop comparator
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
Bit 0 - Sample comparator value
impl W<u32, Reg<u32, _EVENTS_READY>>
impl W<u32, Reg<u32, _EVENTS_READY>>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
Bit 0 - COMP is ready and output is valid
impl W<u32, Reg<u32, _EVENTS_DOWN>>
impl W<u32, Reg<u32, _EVENTS_DOWN>>
pub fn events_down(&mut self) -> EVENTS_DOWN_W<'_>
pub fn events_down(&mut self) -> EVENTS_DOWN_W<'_>
Bit 0 - Downward crossing
impl W<u32, Reg<u32, _EVENTS_UP>>
impl W<u32, Reg<u32, _EVENTS_UP>>
pub fn events_up(&mut self) -> EVENTS_UP_W<'_>
pub fn events_up(&mut self) -> EVENTS_UP_W<'_>
Bit 0 - Upward crossing
impl W<u32, Reg<u32, _EVENTS_CROSS>>
impl W<u32, Reg<u32, _EVENTS_CROSS>>
pub fn events_cross(&mut self) -> EVENTS_CROSS_W<'_>
pub fn events_cross(&mut self) -> EVENTS_CROSS_W<'_>
Bit 0 - Downward or upward crossing
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
Bit 0 - Shortcut between event READY and task SAMPLE
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
Bit 1 - Shortcut between event READY and task STOP
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
Bit 2 - Shortcut between event DOWN and task STOP
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
Bit 4 - Shortcut between event CROSS and task STOP
impl W<u32, Reg<u32, _EXTREFSEL>>
impl W<u32, Reg<u32, _EXTREFSEL>>
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
Bits 0:2 - External analog reference select
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Start comparator
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stop comparator
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
impl W<u32, Reg<u32, _TASKS_SAMPLE>>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>
Bit 0 - Sample comparator value
impl W<u32, Reg<u32, _EVENTS_READY>>
impl W<u32, Reg<u32, _EVENTS_READY>>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>
Bit 0 - LPCOMP is ready and output is valid
impl W<u32, Reg<u32, _EVENTS_DOWN>>
impl W<u32, Reg<u32, _EVENTS_DOWN>>
pub fn events_down(&mut self) -> EVENTS_DOWN_W<'_>
pub fn events_down(&mut self) -> EVENTS_DOWN_W<'_>
Bit 0 - Downward crossing
impl W<u32, Reg<u32, _EVENTS_UP>>
impl W<u32, Reg<u32, _EVENTS_UP>>
pub fn events_up(&mut self) -> EVENTS_UP_W<'_>
pub fn events_up(&mut self) -> EVENTS_UP_W<'_>
Bit 0 - Upward crossing
impl W<u32, Reg<u32, _EVENTS_CROSS>>
impl W<u32, Reg<u32, _EVENTS_CROSS>>
pub fn events_cross(&mut self) -> EVENTS_CROSS_W<'_>
pub fn events_cross(&mut self) -> EVENTS_CROSS_W<'_>
Bit 0 - Downward or upward crossing
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
Bit 0 - Shortcut between event READY and task SAMPLE
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
Bit 1 - Shortcut between event READY and task STOP
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
Bit 2 - Shortcut between event DOWN and task STOP
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
Bit 4 - Shortcut between event CROSS and task STOP
impl W<u32, Reg<u32, _EXTREFSEL>>
impl W<u32, Reg<u32, _EXTREFSEL>>
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
Bit 0 - External analog reference select
impl W<u32, Reg<u32, _ANADETECT>>
impl W<u32, Reg<u32, _ANADETECT>>
pub fn anadetect(&mut self) -> ANADETECT_W<'_>
pub fn anadetect(&mut self) -> ANADETECT_W<'_>
Bits 0:1 - Analog detect configuration
impl W<u32, Reg<u32, _TASKS_TRIGGER>>
impl W<u32, Reg<u32, _TASKS_TRIGGER>>
pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W<'_>
pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W<'_>
Bit 0 - Trigger n for triggering the corresponding TRIGGERED[n] event
impl W<u32, Reg<u32, _EVENTS_TRIGGERED>>
impl W<u32, Reg<u32, _EVENTS_TRIGGERED>>
pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W<'_>
pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W<'_>
Bit 0 - Event number n generated by triggering the corresponding TRIGGER[n] task
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
Bit 0 - Enable or disable interrupt for event TRIGGERED[0]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
Bit 1 - Enable or disable interrupt for event TRIGGERED[1]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
Bit 2 - Enable or disable interrupt for event TRIGGERED[2]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
Bit 3 - Enable or disable interrupt for event TRIGGERED[3]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
Bit 4 - Enable or disable interrupt for event TRIGGERED[4]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
Bit 5 - Enable or disable interrupt for event TRIGGERED[5]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
Bit 6 - Enable or disable interrupt for event TRIGGERED[6]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
Bit 7 - Enable or disable interrupt for event TRIGGERED[7]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
Bit 8 - Enable or disable interrupt for event TRIGGERED[8]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
Bit 9 - Enable or disable interrupt for event TRIGGERED[9]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
Bit 10 - Enable or disable interrupt for event TRIGGERED[10]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
Bit 11 - Enable or disable interrupt for event TRIGGERED[11]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
Bit 12 - Enable or disable interrupt for event TRIGGERED[12]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
Bit 13 - Enable or disable interrupt for event TRIGGERED[13]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
Bit 14 - Enable or disable interrupt for event TRIGGERED[14]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
Bit 15 - Enable or disable interrupt for event TRIGGERED[15]
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event TRIGGERED[0]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event TRIGGERED[1]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event TRIGGERED[2]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event TRIGGERED[3]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event TRIGGERED[4]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event TRIGGERED[5]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event TRIGGERED[6]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event TRIGGERED[7]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
Bit 8 - Write ‘1’ to enable interrupt for event TRIGGERED[8]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
Bit 9 - Write ‘1’ to enable interrupt for event TRIGGERED[9]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
Bit 10 - Write ‘1’ to enable interrupt for event TRIGGERED[10]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
Bit 11 - Write ‘1’ to enable interrupt for event TRIGGERED[11]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
Bit 12 - Write ‘1’ to enable interrupt for event TRIGGERED[12]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
Bit 13 - Write ‘1’ to enable interrupt for event TRIGGERED[13]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
Bit 14 - Write ‘1’ to enable interrupt for event TRIGGERED[14]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
Bit 15 - Write ‘1’ to enable interrupt for event TRIGGERED[15]
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event TRIGGERED[0]
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event TRIGGERED[1]
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event TRIGGERED[2]
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event TRIGGERED[3]
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event TRIGGERED[4]
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event TRIGGERED[5]
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event TRIGGERED[6]
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event TRIGGERED[7]
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
Bit 8 - Write ‘1’ to disable interrupt for event TRIGGERED[8]
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
Bit 9 - Write ‘1’ to disable interrupt for event TRIGGERED[9]
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
Bit 10 - Write ‘1’ to disable interrupt for event TRIGGERED[10]
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
Bit 11 - Write ‘1’ to disable interrupt for event TRIGGERED[11]
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
Bit 12 - Write ‘1’ to disable interrupt for event TRIGGERED[12]
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
Bit 13 - Write ‘1’ to disable interrupt for event TRIGGERED[13]
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
Bit 14 - Write ‘1’ to disable interrupt for event TRIGGERED[14]
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
Bit 15 - Write ‘1’ to disable interrupt for event TRIGGERED[15]
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
impl W<u32, Reg<u32, _TASKS_SEQSTART>>
impl W<u32, Reg<u32, _TASKS_SEQSTART>>
pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W<'_>
pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W<'_>
Bit 0 - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
impl W<u32, Reg<u32, _TASKS_NEXTSTEP>>
impl W<u32, Reg<u32, _TASKS_NEXTSTEP>>
pub fn tasks_nextstep(&mut self) -> TASKS_NEXTSTEP_W<'_>
pub fn tasks_nextstep(&mut self) -> TASKS_NEXTSTEP_W<'_>
Bit 0 - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - Response to STOP task, emitted when PWM pulses are no longer generated
impl W<u32, Reg<u32, _EVENTS_SEQSTARTED>>
impl W<u32, Reg<u32, _EVENTS_SEQSTARTED>>
pub fn events_seqstarted(&mut self) -> EVENTS_SEQSTARTED_W<'_>
pub fn events_seqstarted(&mut self) -> EVENTS_SEQSTARTED_W<'_>
Bit 0 - First PWM period started on sequence n
impl W<u32, Reg<u32, _EVENTS_SEQEND>>
impl W<u32, Reg<u32, _EVENTS_SEQEND>>
pub fn events_seqend(&mut self) -> EVENTS_SEQEND_W<'_>
pub fn events_seqend(&mut self) -> EVENTS_SEQEND_W<'_>
Bit 0 - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
impl W<u32, Reg<u32, _EVENTS_PWMPERIODEND>>
impl W<u32, Reg<u32, _EVENTS_PWMPERIODEND>>
pub fn events_pwmperiodend(&mut self) -> EVENTS_PWMPERIODEND_W<'_>
pub fn events_pwmperiodend(&mut self) -> EVENTS_PWMPERIODEND_W<'_>
Bit 0 - Emitted at the end of each PWM period
impl W<u32, Reg<u32, _EVENTS_LOOPSDONE>>
impl W<u32, Reg<u32, _EVENTS_LOOPSDONE>>
pub fn events_loopsdone(&mut self) -> EVENTS_LOOPSDONE_W<'_>
pub fn events_loopsdone(&mut self) -> EVENTS_LOOPSDONE_W<'_>
Bit 0 - Concatenated sequences have been played the amount of times defined in LOOP.CNT
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>
pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>
Bit 0 - Shortcut between event SEQEND[0] and task STOP
pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>
pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>
Bit 1 - Shortcut between event SEQEND[1] and task STOP
pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>
pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>
Bit 2 - Shortcut between event LOOPSDONE and task SEQSTART[0]
pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>
pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>
Bit 3 - Shortcut between event LOOPSDONE and task SEQSTART[1]
pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>
pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>
Bit 4 - Shortcut between event LOOPSDONE and task STOP
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
Bit 2 - Enable or disable interrupt for event SEQSTARTED[0]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
Bit 3 - Enable or disable interrupt for event SEQSTARTED[1]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
Bit 6 - Enable or disable interrupt for event PWMPERIODEND
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
Bit 7 - Enable or disable interrupt for event LOOPSDONE
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event SEQSTARTED[0]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event SEQSTARTED[1]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event PWMPERIODEND
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event LOOPSDONE
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event SEQSTARTED[0]
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event SEQSTARTED[1]
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event SEQEND[0]
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event SEQEND[1]
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event PWMPERIODEND
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event LOOPSDONE
impl W<u32, Reg<u32, _COUNTERTOP>>
impl W<u32, Reg<u32, _COUNTERTOP>>
pub fn countertop(&mut self) -> COUNTERTOP_W<'_>
pub fn countertop(&mut self) -> COUNTERTOP_W<'_>
Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.
impl W<u32, Reg<u32, _PRESCALER>>
impl W<u32, Reg<u32, _PRESCALER>>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
Bits 0:2 - Prescaler of PWM_CLK
impl W<u32, Reg<u32, _PTR>>
impl W<u32, Reg<u32, _PTR>>
pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>
pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>
Bits 0:31 - Address to write PDM samples to over DMA
impl W<u32, Reg<u32, _MAXCNT>>
impl W<u32, Reg<u32, _MAXCNT>>
pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>
pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>
Bits 0:14 - Length of DMA RAM allocation in number of samples
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Starts continuous PDM transfer
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stops PDM transfer
impl W<u32, Reg<u32, _EVENTS_STARTED>>
impl W<u32, Reg<u32, _EVENTS_STARTED>>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
Bit 0 - PDM transfer has started
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - PDM transfer has finished
impl W<u32, Reg<u32, _EVENTS_END>>
impl W<u32, Reg<u32, _EVENTS_END>>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
pub fn events_end(&mut self) -> EVENTS_END_W<'_>
Bit 0 - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
impl W<u32, Reg<u32, _MODE>>
impl W<u32, Reg<u32, _MODE>>
pub fn operation(&mut self) -> OPERATION_W<'_>
pub fn operation(&mut self) -> OPERATION_W<'_>
Bit 0 - Mono or stereo operation
impl W<u32, Reg<u32, _GAINL>>
impl W<u32, Reg<u32, _GAINL>>
pub fn gainl(&mut self) -> GAINL_W<'_>
pub fn gainl(&mut self) -> GAINL_W<'_>
Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (…) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (…) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
impl W<u32, Reg<u32, _ERASEPAGE>>
impl W<u32, Reg<u32, _ERASEPAGE>>
pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>
pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>
Bits 0:31 - Register for starting erase of a page in code area
impl W<u32, Reg<u32, _ERASEPCR1>>
impl W<u32, Reg<u32, _ERASEPCR1>>
pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>
pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>
Bits 0:31 - Register for erasing a page in code area, equivalent to ERASEPAGE
impl W<u32, Reg<u32, _ERASEALL>>
impl W<u32, Reg<u32, _ERASEALL>>
pub fn eraseall(&mut self) -> ERASEALL_W<'_>
pub fn eraseall(&mut self) -> ERASEALL_W<'_>
Bit 0 - Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
impl W<u32, Reg<u32, _ERASEPCR0>>
impl W<u32, Reg<u32, _ERASEPCR0>>
pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>
pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>
Bits 0:31 - Register for starting erase of a page in code area, equivalent to ERASEPAGE
impl W<u32, Reg<u32, _ERASEUICR>>
impl W<u32, Reg<u32, _ERASEUICR>>
pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>
pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>
Bit 0 - Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased.
impl W<u32, Reg<u32, _ERASEPAGEPARTIAL>>
impl W<u32, Reg<u32, _ERASEPAGEPARTIAL>>
pub fn erasepagepartial(&mut self) -> ERASEPAGEPARTIAL_W<'_>
pub fn erasepagepartial(&mut self) -> ERASEPAGEPARTIAL_W<'_>
Bits 0:31 - Register for starting partial erase of a page in code area
impl W<u32, Reg<u32, _ERASEPAGEPARTIALCFG>>
impl W<u32, Reg<u32, _ERASEPAGEPARTIALCFG>>
pub fn duration(&mut self) -> DURATION_W<'_>
pub fn duration(&mut self) -> DURATION_W<'_>
Bits 0:6 - Duration of the partial erase in milliseconds
impl W<u32, Reg<u32, _ICACHECNF>>
impl W<u32, Reg<u32, _ICACHECNF>>
pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<'_>
pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<'_>
Bit 8 - Cache profiling enable
impl W<u32, Reg<u32, _CHENSET>>
impl W<u32, Reg<u32, _CHENSET>>
pub fn ch10(&mut self) -> CH10_W<'_>
pub fn ch10(&mut self) -> CH10_W<'_>
Bit 10 - Channel 10 enable set register. Writing ‘0’ has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
pub fn ch11(&mut self) -> CH11_W<'_>
Bit 11 - Channel 11 enable set register. Writing ‘0’ has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
pub fn ch12(&mut self) -> CH12_W<'_>
Bit 12 - Channel 12 enable set register. Writing ‘0’ has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
pub fn ch13(&mut self) -> CH13_W<'_>
Bit 13 - Channel 13 enable set register. Writing ‘0’ has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
pub fn ch14(&mut self) -> CH14_W<'_>
Bit 14 - Channel 14 enable set register. Writing ‘0’ has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
pub fn ch15(&mut self) -> CH15_W<'_>
Bit 15 - Channel 15 enable set register. Writing ‘0’ has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
pub fn ch16(&mut self) -> CH16_W<'_>
Bit 16 - Channel 16 enable set register. Writing ‘0’ has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
pub fn ch17(&mut self) -> CH17_W<'_>
Bit 17 - Channel 17 enable set register. Writing ‘0’ has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
pub fn ch18(&mut self) -> CH18_W<'_>
Bit 18 - Channel 18 enable set register. Writing ‘0’ has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
pub fn ch19(&mut self) -> CH19_W<'_>
Bit 19 - Channel 19 enable set register. Writing ‘0’ has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
pub fn ch20(&mut self) -> CH20_W<'_>
Bit 20 - Channel 20 enable set register. Writing ‘0’ has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
pub fn ch21(&mut self) -> CH21_W<'_>
Bit 21 - Channel 21 enable set register. Writing ‘0’ has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
pub fn ch22(&mut self) -> CH22_W<'_>
Bit 22 - Channel 22 enable set register. Writing ‘0’ has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
pub fn ch23(&mut self) -> CH23_W<'_>
Bit 23 - Channel 23 enable set register. Writing ‘0’ has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
pub fn ch24(&mut self) -> CH24_W<'_>
Bit 24 - Channel 24 enable set register. Writing ‘0’ has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
pub fn ch25(&mut self) -> CH25_W<'_>
Bit 25 - Channel 25 enable set register. Writing ‘0’ has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
pub fn ch26(&mut self) -> CH26_W<'_>
Bit 26 - Channel 26 enable set register. Writing ‘0’ has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
pub fn ch27(&mut self) -> CH27_W<'_>
Bit 27 - Channel 27 enable set register. Writing ‘0’ has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
pub fn ch28(&mut self) -> CH28_W<'_>
Bit 28 - Channel 28 enable set register. Writing ‘0’ has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
pub fn ch29(&mut self) -> CH29_W<'_>
Bit 29 - Channel 29 enable set register. Writing ‘0’ has no effect
impl W<u32, Reg<u32, _CHENCLR>>
impl W<u32, Reg<u32, _CHENCLR>>
pub fn ch0(&mut self) -> CH0_W<'_>
pub fn ch0(&mut self) -> CH0_W<'_>
Bit 0 - Channel 0 enable clear register. Writing ‘0’ has no effect
pub fn ch1(&mut self) -> CH1_W<'_>
pub fn ch1(&mut self) -> CH1_W<'_>
Bit 1 - Channel 1 enable clear register. Writing ‘0’ has no effect
pub fn ch2(&mut self) -> CH2_W<'_>
pub fn ch2(&mut self) -> CH2_W<'_>
Bit 2 - Channel 2 enable clear register. Writing ‘0’ has no effect
pub fn ch3(&mut self) -> CH3_W<'_>
pub fn ch3(&mut self) -> CH3_W<'_>
Bit 3 - Channel 3 enable clear register. Writing ‘0’ has no effect
pub fn ch4(&mut self) -> CH4_W<'_>
pub fn ch4(&mut self) -> CH4_W<'_>
Bit 4 - Channel 4 enable clear register. Writing ‘0’ has no effect
pub fn ch5(&mut self) -> CH5_W<'_>
pub fn ch5(&mut self) -> CH5_W<'_>
Bit 5 - Channel 5 enable clear register. Writing ‘0’ has no effect
pub fn ch6(&mut self) -> CH6_W<'_>
pub fn ch6(&mut self) -> CH6_W<'_>
Bit 6 - Channel 6 enable clear register. Writing ‘0’ has no effect
pub fn ch7(&mut self) -> CH7_W<'_>
pub fn ch7(&mut self) -> CH7_W<'_>
Bit 7 - Channel 7 enable clear register. Writing ‘0’ has no effect
pub fn ch8(&mut self) -> CH8_W<'_>
pub fn ch8(&mut self) -> CH8_W<'_>
Bit 8 - Channel 8 enable clear register. Writing ‘0’ has no effect
pub fn ch9(&mut self) -> CH9_W<'_>
pub fn ch9(&mut self) -> CH9_W<'_>
Bit 9 - Channel 9 enable clear register. Writing ‘0’ has no effect
pub fn ch10(&mut self) -> CH10_W<'_>
pub fn ch10(&mut self) -> CH10_W<'_>
Bit 10 - Channel 10 enable clear register. Writing ‘0’ has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
pub fn ch11(&mut self) -> CH11_W<'_>
Bit 11 - Channel 11 enable clear register. Writing ‘0’ has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
pub fn ch12(&mut self) -> CH12_W<'_>
Bit 12 - Channel 12 enable clear register. Writing ‘0’ has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
pub fn ch13(&mut self) -> CH13_W<'_>
Bit 13 - Channel 13 enable clear register. Writing ‘0’ has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
pub fn ch14(&mut self) -> CH14_W<'_>
Bit 14 - Channel 14 enable clear register. Writing ‘0’ has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
pub fn ch15(&mut self) -> CH15_W<'_>
Bit 15 - Channel 15 enable clear register. Writing ‘0’ has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
pub fn ch16(&mut self) -> CH16_W<'_>
Bit 16 - Channel 16 enable clear register. Writing ‘0’ has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
pub fn ch17(&mut self) -> CH17_W<'_>
Bit 17 - Channel 17 enable clear register. Writing ‘0’ has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
pub fn ch18(&mut self) -> CH18_W<'_>
Bit 18 - Channel 18 enable clear register. Writing ‘0’ has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
pub fn ch19(&mut self) -> CH19_W<'_>
Bit 19 - Channel 19 enable clear register. Writing ‘0’ has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
pub fn ch20(&mut self) -> CH20_W<'_>
Bit 20 - Channel 20 enable clear register. Writing ‘0’ has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
pub fn ch21(&mut self) -> CH21_W<'_>
Bit 21 - Channel 21 enable clear register. Writing ‘0’ has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
pub fn ch22(&mut self) -> CH22_W<'_>
Bit 22 - Channel 22 enable clear register. Writing ‘0’ has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
pub fn ch23(&mut self) -> CH23_W<'_>
Bit 23 - Channel 23 enable clear register. Writing ‘0’ has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
pub fn ch24(&mut self) -> CH24_W<'_>
Bit 24 - Channel 24 enable clear register. Writing ‘0’ has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
pub fn ch25(&mut self) -> CH25_W<'_>
Bit 25 - Channel 25 enable clear register. Writing ‘0’ has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
pub fn ch26(&mut self) -> CH26_W<'_>
Bit 26 - Channel 26 enable clear register. Writing ‘0’ has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
pub fn ch27(&mut self) -> CH27_W<'_>
Bit 27 - Channel 27 enable clear register. Writing ‘0’ has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
pub fn ch28(&mut self) -> CH28_W<'_>
Bit 28 - Channel 28 enable clear register. Writing ‘0’ has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
pub fn ch29(&mut self) -> CH29_W<'_>
Bit 29 - Channel 29 enable clear register. Writing ‘0’ has no effect
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Enable or disable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Enable or disable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Enable or disable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Enable or disable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Enable or disable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Enable or disable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Enable or disable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Enable or disable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Enable or disable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Enable or disable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Enable or disable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Enable or disable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Write ‘1’ to enable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Write ‘1’ to enable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Write ‘1’ to enable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Write ‘1’ to enable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Write ‘1’ to disable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Write ‘1’ to disable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Write ‘1’ to disable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Write ‘1’ to disable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _NMIEN>>
impl W<u32, Reg<u32, _NMIEN>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Enable or disable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Enable or disable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Enable or disable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Enable or disable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Enable or disable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Enable or disable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Enable or disable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Enable or disable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Enable or disable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Enable or disable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Enable or disable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Enable or disable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _NMIENSET>>
impl W<u32, Reg<u32, _NMIENSET>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Write ‘1’ to enable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Write ‘1’ to enable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Write ‘1’ to enable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Write ‘1’ to enable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _NMIENCLR>>
impl W<u32, Reg<u32, _NMIENCLR>>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event REGION0WA
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event REGION0RA
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event REGION1WA
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event REGION1RA
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event REGION2WA
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event REGION2RA
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event REGION3WA
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event REGION3RA
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
Bit 24 - Write ‘1’ to disable interrupt for event PREGION0WA
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
Bit 25 - Write ‘1’ to disable interrupt for event PREGION0RA
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
Bit 26 - Write ‘1’ to disable interrupt for event PREGION1WA
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
Bit 27 - Write ‘1’ to disable interrupt for event PREGION1RA
impl W<u32, Reg<u32, _CHANNELS>>
impl W<u32, Reg<u32, _CHANNELS>>
pub fn channels(&mut self) -> CHANNELS_W<'_>
pub fn channels(&mut self) -> CHANNELS_W<'_>
Bits 0:1 - Enable channels.
impl W<u32, Reg<u32, _TASKS_START>>
impl W<u32, Reg<u32, _TASKS_START>>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
pub fn tasks_start(&mut self) -> TASKS_START_W<'_>
Bit 0 - Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
impl W<u32, Reg<u32, _TASKS_STOP>>
impl W<u32, Reg<u32, _TASKS_STOP>>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>
Bit 0 - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
impl W<u32, Reg<u32, _EVENTS_RXPTRUPD>>
impl W<u32, Reg<u32, _EVENTS_RXPTRUPD>>
pub fn events_rxptrupd(&mut self) -> EVENTS_RXPTRUPD_W<'_>
pub fn events_rxptrupd(&mut self) -> EVENTS_RXPTRUPD_W<'_>
Bit 0 - The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
impl W<u32, Reg<u32, _EVENTS_STOPPED>>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>
Bit 0 - I2S transfer stopped.
impl W<u32, Reg<u32, _EVENTS_TXPTRUPD>>
impl W<u32, Reg<u32, _EVENTS_TXPTRUPD>>
pub fn events_txptrupd(&mut self) -> EVENTS_TXPTRUPD_W<'_>
pub fn events_txptrupd(&mut self) -> EVENTS_TXPTRUPD_W<'_>
Bit 0 - The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
Bit 1 - Enable or disable interrupt for event RXPTRUPD
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
Bit 5 - Enable or disable interrupt for event TXPTRUPD
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
Bit 1 - Write ‘1’ to enable interrupt for event RXPTRUPD
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event TXPTRUPD
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
Bit 1 - Write ‘1’ to disable interrupt for event RXPTRUPD
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event TXPTRUPD
impl W<u32, Reg<u32, _TASKS_STARTEPIN>>
impl W<u32, Reg<u32, _TASKS_STARTEPIN>>
pub fn tasks_startepin(&mut self) -> TASKS_STARTEPIN_W<'_>
pub fn tasks_startepin(&mut self) -> TASKS_STARTEPIN_W<'_>
Bit 0 - Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
impl W<u32, Reg<u32, _TASKS_STARTISOIN>>
impl W<u32, Reg<u32, _TASKS_STARTISOIN>>
pub fn tasks_startisoin(&mut self) -> TASKS_STARTISOIN_W<'_>
pub fn tasks_startisoin(&mut self) -> TASKS_STARTISOIN_W<'_>
Bit 0 - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
impl W<u32, Reg<u32, _TASKS_STARTEPOUT>>
impl W<u32, Reg<u32, _TASKS_STARTEPOUT>>
pub fn tasks_startepout(&mut self) -> TASKS_STARTEPOUT_W<'_>
pub fn tasks_startepout(&mut self) -> TASKS_STARTEPOUT_W<'_>
Bit 0 - Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
impl W<u32, Reg<u32, _TASKS_STARTISOOUT>>
impl W<u32, Reg<u32, _TASKS_STARTISOOUT>>
pub fn tasks_startisoout(&mut self) -> TASKS_STARTISOOUT_W<'_>
pub fn tasks_startisoout(&mut self) -> TASKS_STARTISOOUT_W<'_>
Bit 0 - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
impl W<u32, Reg<u32, _TASKS_EP0RCVOUT>>
impl W<u32, Reg<u32, _TASKS_EP0RCVOUT>>
pub fn tasks_ep0rcvout(&mut self) -> TASKS_EP0RCVOUT_W<'_>
pub fn tasks_ep0rcvout(&mut self) -> TASKS_EP0RCVOUT_W<'_>
Bit 0 - Allows OUT data stage on control endpoint 0
impl W<u32, Reg<u32, _TASKS_EP0STATUS>>
impl W<u32, Reg<u32, _TASKS_EP0STATUS>>
pub fn tasks_ep0status(&mut self) -> TASKS_EP0STATUS_W<'_>
pub fn tasks_ep0status(&mut self) -> TASKS_EP0STATUS_W<'_>
Bit 0 - Allows status stage on control endpoint 0
impl W<u32, Reg<u32, _TASKS_EP0STALL>>
impl W<u32, Reg<u32, _TASKS_EP0STALL>>
pub fn tasks_ep0stall(&mut self) -> TASKS_EP0STALL_W<'_>
pub fn tasks_ep0stall(&mut self) -> TASKS_EP0STALL_W<'_>
Bit 0 - Stalls data and status stage on control endpoint 0
impl W<u32, Reg<u32, _TASKS_DPDMDRIVE>>
impl W<u32, Reg<u32, _TASKS_DPDMDRIVE>>
pub fn tasks_dpdmdrive(&mut self) -> TASKS_DPDMDRIVE_W<'_>
pub fn tasks_dpdmdrive(&mut self) -> TASKS_DPDMDRIVE_W<'_>
Bit 0 - Forces D+ and D- lines into the state defined in the DPDMVALUE register
impl W<u32, Reg<u32, _TASKS_DPDMNODRIVE>>
impl W<u32, Reg<u32, _TASKS_DPDMNODRIVE>>
pub fn tasks_dpdmnodrive(&mut self) -> TASKS_DPDMNODRIVE_W<'_>
pub fn tasks_dpdmnodrive(&mut self) -> TASKS_DPDMNODRIVE_W<'_>
Bit 0 - Stops forcing D+ and D- lines into any state (USB engine takes control)
impl W<u32, Reg<u32, _EVENTS_USBRESET>>
impl W<u32, Reg<u32, _EVENTS_USBRESET>>
pub fn events_usbreset(&mut self) -> EVENTS_USBRESET_W<'_>
pub fn events_usbreset(&mut self) -> EVENTS_USBRESET_W<'_>
Bit 0 - Signals that a USB reset condition has been detected on USB lines
impl W<u32, Reg<u32, _EVENTS_STARTED>>
impl W<u32, Reg<u32, _EVENTS_STARTED>>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>
Bit 0 - Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
impl W<u32, Reg<u32, _EVENTS_ENDEPIN>>
impl W<u32, Reg<u32, _EVENTS_ENDEPIN>>
pub fn events_endepin(&mut self) -> EVENTS_ENDEPIN_W<'_>
pub fn events_endepin(&mut self) -> EVENTS_ENDEPIN_W<'_>
Bit 0 - The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software.
impl W<u32, Reg<u32, _EVENTS_EP0DATADONE>>
impl W<u32, Reg<u32, _EVENTS_EP0DATADONE>>
pub fn events_ep0datadone(&mut self) -> EVENTS_EP0DATADONE_W<'_>
pub fn events_ep0datadone(&mut self) -> EVENTS_EP0DATADONE_W<'_>
Bit 0 - An acknowledged data transfer has taken place on the control endpoint
impl W<u32, Reg<u32, _EVENTS_ENDISOIN>>
impl W<u32, Reg<u32, _EVENTS_ENDISOIN>>
pub fn events_endisoin(&mut self) -> EVENTS_ENDISOIN_W<'_>
pub fn events_endisoin(&mut self) -> EVENTS_ENDISOIN_W<'_>
Bit 0 - The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software.
impl W<u32, Reg<u32, _EVENTS_ENDEPOUT>>
impl W<u32, Reg<u32, _EVENTS_ENDEPOUT>>
pub fn events_endepout(&mut self) -> EVENTS_ENDEPOUT_W<'_>
pub fn events_endepout(&mut self) -> EVENTS_ENDEPOUT_W<'_>
Bit 0 - The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software.
impl W<u32, Reg<u32, _EVENTS_ENDISOOUT>>
impl W<u32, Reg<u32, _EVENTS_ENDISOOUT>>
pub fn events_endisoout(&mut self) -> EVENTS_ENDISOOUT_W<'_>
pub fn events_endisoout(&mut self) -> EVENTS_ENDISOOUT_W<'_>
Bit 0 - The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software.
impl W<u32, Reg<u32, _EVENTS_SOF>>
impl W<u32, Reg<u32, _EVENTS_SOF>>
pub fn events_sof(&mut self) -> EVENTS_SOF_W<'_>
pub fn events_sof(&mut self) -> EVENTS_SOF_W<'_>
Bit 0 - Signals that a SOF (start of frame) condition has been detected on USB lines
impl W<u32, Reg<u32, _EVENTS_USBEVENT>>
impl W<u32, Reg<u32, _EVENTS_USBEVENT>>
pub fn events_usbevent(&mut self) -> EVENTS_USBEVENT_W<'_>
pub fn events_usbevent(&mut self) -> EVENTS_USBEVENT_W<'_>
Bit 0 - An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
impl W<u32, Reg<u32, _EVENTS_EP0SETUP>>
impl W<u32, Reg<u32, _EVENTS_EP0SETUP>>
pub fn events_ep0setup(&mut self) -> EVENTS_EP0SETUP_W<'_>
pub fn events_ep0setup(&mut self) -> EVENTS_EP0SETUP_W<'_>
Bit 0 - A valid SETUP token has been received (and acknowledged) on the control endpoint
impl W<u32, Reg<u32, _EVENTS_EPDATA>>
impl W<u32, Reg<u32, _EVENTS_EPDATA>>
pub fn events_epdata(&mut self) -> EVENTS_EPDATA_W<'_>
pub fn events_epdata(&mut self) -> EVENTS_EPDATA_W<'_>
Bit 0 - A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
impl W<u32, Reg<u32, _SHORTS>>
impl W<u32, Reg<u32, _SHORTS>>
pub fn ep0datadone_startepin0(&mut self) -> EP0DATADONE_STARTEPIN0_W<'_>
pub fn ep0datadone_startepin0(&mut self) -> EP0DATADONE_STARTEPIN0_W<'_>
Bit 0 - Shortcut between event EP0DATADONE and task STARTEPIN[0]
pub fn ep0datadone_startepout0(&mut self) -> EP0DATADONE_STARTEPOUT0_W<'_>
pub fn ep0datadone_startepout0(&mut self) -> EP0DATADONE_STARTEPOUT0_W<'_>
Bit 1 - Shortcut between event EP0DATADONE and task STARTEPOUT[0]
pub fn ep0datadone_ep0status(&mut self) -> EP0DATADONE_EP0STATUS_W<'_>
pub fn ep0datadone_ep0status(&mut self) -> EP0DATADONE_EP0STATUS_W<'_>
Bit 2 - Shortcut between event EP0DATADONE and task EP0STATUS
pub fn endepout0_ep0status(&mut self) -> ENDEPOUT0_EP0STATUS_W<'_>
pub fn endepout0_ep0status(&mut self) -> ENDEPOUT0_EP0STATUS_W<'_>
Bit 3 - Shortcut between event ENDEPOUT[0] and task EP0STATUS
pub fn endepout0_ep0rcvout(&mut self) -> ENDEPOUT0_EP0RCVOUT_W<'_>
pub fn endepout0_ep0rcvout(&mut self) -> ENDEPOUT0_EP0RCVOUT_W<'_>
Bit 4 - Shortcut between event ENDEPOUT[0] and task EP0RCVOUT
impl W<u32, Reg<u32, _INTEN>>
impl W<u32, Reg<u32, _INTEN>>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
Bit 0 - Enable or disable interrupt for event USBRESET
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
Bit 2 - Enable or disable interrupt for event ENDEPIN[0]
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
Bit 3 - Enable or disable interrupt for event ENDEPIN[1]
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
Bit 4 - Enable or disable interrupt for event ENDEPIN[2]
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
Bit 5 - Enable or disable interrupt for event ENDEPIN[3]
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
Bit 6 - Enable or disable interrupt for event ENDEPIN[4]
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
Bit 7 - Enable or disable interrupt for event ENDEPIN[5]
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
Bit 8 - Enable or disable interrupt for event ENDEPIN[6]
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
Bit 9 - Enable or disable interrupt for event ENDEPIN[7]
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
Bit 10 - Enable or disable interrupt for event EP0DATADONE
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
Bit 11 - Enable or disable interrupt for event ENDISOIN
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
Bit 12 - Enable or disable interrupt for event ENDEPOUT[0]
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
Bit 13 - Enable or disable interrupt for event ENDEPOUT[1]
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
Bit 14 - Enable or disable interrupt for event ENDEPOUT[2]
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
Bit 15 - Enable or disable interrupt for event ENDEPOUT[3]
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
Bit 16 - Enable or disable interrupt for event ENDEPOUT[4]
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
Bit 17 - Enable or disable interrupt for event ENDEPOUT[5]
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
Bit 18 - Enable or disable interrupt for event ENDEPOUT[6]
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
Bit 19 - Enable or disable interrupt for event ENDEPOUT[7]
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
Bit 20 - Enable or disable interrupt for event ENDISOOUT
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
Bit 22 - Enable or disable interrupt for event USBEVENT
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
Bit 23 - Enable or disable interrupt for event EP0SETUP
impl W<u32, Reg<u32, _INTENSET>>
impl W<u32, Reg<u32, _INTENSET>>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
Bit 0 - Write ‘1’ to enable interrupt for event USBRESET
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
Bit 2 - Write ‘1’ to enable interrupt for event ENDEPIN[0]
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
Bit 3 - Write ‘1’ to enable interrupt for event ENDEPIN[1]
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
Bit 4 - Write ‘1’ to enable interrupt for event ENDEPIN[2]
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
Bit 5 - Write ‘1’ to enable interrupt for event ENDEPIN[3]
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
Bit 6 - Write ‘1’ to enable interrupt for event ENDEPIN[4]
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
Bit 7 - Write ‘1’ to enable interrupt for event ENDEPIN[5]
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
Bit 8 - Write ‘1’ to enable interrupt for event ENDEPIN[6]
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
Bit 9 - Write ‘1’ to enable interrupt for event ENDEPIN[7]
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
Bit 10 - Write ‘1’ to enable interrupt for event EP0DATADONE
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
Bit 11 - Write ‘1’ to enable interrupt for event ENDISOIN
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
Bit 12 - Write ‘1’ to enable interrupt for event ENDEPOUT[0]
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
Bit 13 - Write ‘1’ to enable interrupt for event ENDEPOUT[1]
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
Bit 14 - Write ‘1’ to enable interrupt for event ENDEPOUT[2]
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
Bit 15 - Write ‘1’ to enable interrupt for event ENDEPOUT[3]
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
Bit 16 - Write ‘1’ to enable interrupt for event ENDEPOUT[4]
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
Bit 17 - Write ‘1’ to enable interrupt for event ENDEPOUT[5]
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
Bit 18 - Write ‘1’ to enable interrupt for event ENDEPOUT[6]
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
Bit 19 - Write ‘1’ to enable interrupt for event ENDEPOUT[7]
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
Bit 20 - Write ‘1’ to enable interrupt for event ENDISOOUT
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
Bit 22 - Write ‘1’ to enable interrupt for event USBEVENT
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
Bit 23 - Write ‘1’ to enable interrupt for event EP0SETUP
impl W<u32, Reg<u32, _INTENCLR>>
impl W<u32, Reg<u32, _INTENCLR>>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
pub fn usbreset(&mut self) -> USBRESET_W<'_>
Bit 0 - Write ‘1’ to disable interrupt for event USBRESET
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
pub fn endepin0(&mut self) -> ENDEPIN0_W<'_>
Bit 2 - Write ‘1’ to disable interrupt for event ENDEPIN[0]
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
pub fn endepin1(&mut self) -> ENDEPIN1_W<'_>
Bit 3 - Write ‘1’ to disable interrupt for event ENDEPIN[1]
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
pub fn endepin2(&mut self) -> ENDEPIN2_W<'_>
Bit 4 - Write ‘1’ to disable interrupt for event ENDEPIN[2]
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
pub fn endepin3(&mut self) -> ENDEPIN3_W<'_>
Bit 5 - Write ‘1’ to disable interrupt for event ENDEPIN[3]
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
pub fn endepin4(&mut self) -> ENDEPIN4_W<'_>
Bit 6 - Write ‘1’ to disable interrupt for event ENDEPIN[4]
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
pub fn endepin5(&mut self) -> ENDEPIN5_W<'_>
Bit 7 - Write ‘1’ to disable interrupt for event ENDEPIN[5]
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
pub fn endepin6(&mut self) -> ENDEPIN6_W<'_>
Bit 8 - Write ‘1’ to disable interrupt for event ENDEPIN[6]
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
pub fn endepin7(&mut self) -> ENDEPIN7_W<'_>
Bit 9 - Write ‘1’ to disable interrupt for event ENDEPIN[7]
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
pub fn ep0datadone(&mut self) -> EP0DATADONE_W<'_>
Bit 10 - Write ‘1’ to disable interrupt for event EP0DATADONE
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
pub fn endisoin(&mut self) -> ENDISOIN_W<'_>
Bit 11 - Write ‘1’ to disable interrupt for event ENDISOIN
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
pub fn endepout0(&mut self) -> ENDEPOUT0_W<'_>
Bit 12 - Write ‘1’ to disable interrupt for event ENDEPOUT[0]
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
pub fn endepout1(&mut self) -> ENDEPOUT1_W<'_>
Bit 13 - Write ‘1’ to disable interrupt for event ENDEPOUT[1]
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
pub fn endepout2(&mut self) -> ENDEPOUT2_W<'_>
Bit 14 - Write ‘1’ to disable interrupt for event ENDEPOUT[2]
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
pub fn endepout3(&mut self) -> ENDEPOUT3_W<'_>
Bit 15 - Write ‘1’ to disable interrupt for event ENDEPOUT[3]
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
pub fn endepout4(&mut self) -> ENDEPOUT4_W<'_>
Bit 16 - Write ‘1’ to disable interrupt for event ENDEPOUT[4]
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
pub fn endepout5(&mut self) -> ENDEPOUT5_W<'_>
Bit 17 - Write ‘1’ to disable interrupt for event ENDEPOUT[5]
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
pub fn endepout6(&mut self) -> ENDEPOUT6_W<'_>
Bit 18 - Write ‘1’ to disable interrupt for event ENDEPOUT[6]
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
pub fn endepout7(&mut self) -> ENDEPOUT7_W<'_>
Bit 19 - Write ‘1’ to disable interrupt for event ENDEPOUT[7]
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
pub fn endisoout(&mut self) -> ENDISOOUT_W<'_>
Bit 20 - Write ‘1’ to disable interrupt for event ENDISOOUT
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
pub fn usbevent(&mut self) -> USBEVENT_W<'_>
Bit 22 - Write ‘1’ to disable interrupt for event USBEVENT
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
pub fn ep0setup(&mut self) -> EP0SETUP_W<'_>
Bit 23 - Write ‘1’ to disable interrupt for event EP0SETUP
impl W<u32, Reg<u32, _EVENTCAUSE>>
impl W<u32, Reg<u32, _EVENTCAUSE>>
pub fn isooutcrc(&mut self) -> ISOOUTCRC_W<'_>
pub fn isooutcrc(&mut self) -> ISOOUTCRC_W<'_>
Bit 0 - CRC error was detected on isochronous OUT endpoint 8. Write ‘1’ to clear.
pub fn suspend(&mut self) -> SUSPEND_W<'_>
pub fn suspend(&mut self) -> SUSPEND_W<'_>
Bit 8 - Signals that USB lines have been idle long enough for the device to enter suspend. Write ‘1’ to clear.
pub fn resume(&mut self) -> RESUME_W<'_>
pub fn resume(&mut self) -> RESUME_W<'_>
Bit 9 - Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write ‘1’ to clear.
pub fn usbwuallowed(&mut self) -> USBWUALLOWED_W<'_>
pub fn usbwuallowed(&mut self) -> USBWUALLOWED_W<'_>
Bit 10 - USB MAC has been woken up and operational. Write ‘1’ to clear.
impl W<u32, Reg<u32, _EPSTATUS>>
impl W<u32, Reg<u32, _EPSTATUS>>
pub fn epin0(&mut self) -> EPIN0_W<'_>
pub fn epin0(&mut self) -> EPIN0_W<'_>
Bit 0 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin1(&mut self) -> EPIN1_W<'_>
pub fn epin1(&mut self) -> EPIN1_W<'_>
Bit 1 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin2(&mut self) -> EPIN2_W<'_>
pub fn epin2(&mut self) -> EPIN2_W<'_>
Bit 2 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin3(&mut self) -> EPIN3_W<'_>
pub fn epin3(&mut self) -> EPIN3_W<'_>
Bit 3 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin4(&mut self) -> EPIN4_W<'_>
pub fn epin4(&mut self) -> EPIN4_W<'_>
Bit 4 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin5(&mut self) -> EPIN5_W<'_>
pub fn epin5(&mut self) -> EPIN5_W<'_>
Bit 5 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin6(&mut self) -> EPIN6_W<'_>
pub fn epin6(&mut self) -> EPIN6_W<'_>
Bit 6 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin7(&mut self) -> EPIN7_W<'_>
pub fn epin7(&mut self) -> EPIN7_W<'_>
Bit 7 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epin8(&mut self) -> EPIN8_W<'_>
pub fn epin8(&mut self) -> EPIN8_W<'_>
Bit 8 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout0(&mut self) -> EPOUT0_W<'_>
pub fn epout0(&mut self) -> EPOUT0_W<'_>
Bit 16 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout1(&mut self) -> EPOUT1_W<'_>
pub fn epout1(&mut self) -> EPOUT1_W<'_>
Bit 17 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout2(&mut self) -> EPOUT2_W<'_>
pub fn epout2(&mut self) -> EPOUT2_W<'_>
Bit 18 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout3(&mut self) -> EPOUT3_W<'_>
pub fn epout3(&mut self) -> EPOUT3_W<'_>
Bit 19 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout4(&mut self) -> EPOUT4_W<'_>
pub fn epout4(&mut self) -> EPOUT4_W<'_>
Bit 20 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout5(&mut self) -> EPOUT5_W<'_>
pub fn epout5(&mut self) -> EPOUT5_W<'_>
Bit 21 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
pub fn epout6(&mut self) -> EPOUT6_W<'_>
pub fn epout6(&mut self) -> EPOUT6_W<'_>
Bit 22 - Captured state of endpoint’s EasyDMA registers. Write ‘1’ to clear.
impl W<u32, Reg<u32, _EPDATASTATUS>>
impl W<u32, Reg<u32, _EPDATASTATUS>>
pub fn epin1(&mut self) -> EPIN1_W<'_>
pub fn epin1(&mut self) -> EPIN1_W<'_>
Bit 1 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin2(&mut self) -> EPIN2_W<'_>
pub fn epin2(&mut self) -> EPIN2_W<'_>
Bit 2 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin3(&mut self) -> EPIN3_W<'_>
pub fn epin3(&mut self) -> EPIN3_W<'_>
Bit 3 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin4(&mut self) -> EPIN4_W<'_>
pub fn epin4(&mut self) -> EPIN4_W<'_>
Bit 4 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin5(&mut self) -> EPIN5_W<'_>
pub fn epin5(&mut self) -> EPIN5_W<'_>
Bit 5 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin6(&mut self) -> EPIN6_W<'_>
pub fn epin6(&mut self) -> EPIN6_W<'_>
Bit 6 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epin7(&mut self) -> EPIN7_W<'_>
pub fn epin7(&mut self) -> EPIN7_W<'_>
Bit 7 - Acknowledged data transfer on this IN endpoint. Write ‘1’ to clear.
pub fn epout1(&mut self) -> EPOUT1_W<'_>
pub fn epout1(&mut self) -> EPOUT1_W<'_>
Bit 17 - Acknowledged data transfer on this OUT endpoint. Write ‘1’ to clear.
pub fn epout2(&mut self) -> EPOUT2_W<'_>
pub fn epout2(&mut self) -> EPOUT2_W<'_>
Bit 18 - Acknowledged data transfer on this OUT endpoint. Write ‘1’ to clear.
pub fn epout3(&mut self) -> EPOUT3_W<'_>
pub fn epout3(&mut self) -> EPOUT3_W<'_>
Bit 19 - Acknowledged data transfer on this OUT endpoint. Write ‘1’ to clear.
pub fn epout4(&mut self) -> EPOUT4_W<'_>
pub fn epout4(&mut self) -> EPOUT4_W<'_>
Bit 20 - Acknowledged data transfer on this OUT endpoint. Write ‘1’ to clear.
pub fn epout5(&mut self) -> EPOUT5_W<'_>
pub fn epout5(&mut self) -> EPOUT5_W<'_>
Bit 21 - Acknowledged data transfer on this OUT endpoint. Write ‘1’ to clear.
impl W<u32, Reg<u32, _LOWPOWER>>
impl W<u32, Reg<u32, _LOWPOWER>>
pub fn lowpower(&mut self) -> LOWPOWER_W<'_>
pub fn lowpower(&mut self) -> LOWPOWER_W<'_>
Bit 0 - Controls USBD peripheral low-power mode during USB suspend
impl W<u32, Reg<u32, _ISOINCONFIG>>
impl W<u32, Reg<u32, _ISOINCONFIG>>
pub fn response(&mut self) -> RESPONSE_W<'_>
pub fn response(&mut self) -> RESPONSE_W<'_>
Bit 0 - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]pub fn borrow_mut(&mut self) -> &mut T
[src]
pub fn borrow_mut(&mut self) -> &mut T
[src]Mutably borrows from an owned value. Read more
impl<T> CheckedAs for T
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impl<T> CheckedAs for T
[src]pub fn checked_as<Dst>(self) -> Option<Dst> where
T: CheckedCast<Dst>,
[src]
pub fn checked_as<Dst>(self) -> Option<Dst> where
T: CheckedCast<Dst>,
[src]Casts the value.
impl<Src, Dst> LosslessTryInto<Dst> for Src where
Dst: LosslessTryFrom<Src>,
[src]
impl<Src, Dst> LosslessTryInto<Dst> for Src where
Dst: LosslessTryFrom<Src>,
[src]pub fn lossless_try_into(self) -> Option<Dst>
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pub fn lossless_try_into(self) -> Option<Dst>
[src]Performs the conversion.
impl<Src, Dst> LossyInto<Dst> for Src where
Dst: LossyFrom<Src>,
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impl<Src, Dst> LossyInto<Dst> for Src where
Dst: LossyFrom<Src>,
[src]pub fn lossy_into(self) -> Dst
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pub fn lossy_into(self) -> Dst
[src]Performs the conversion.
impl<T> OverflowingAs for T
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impl<T> OverflowingAs for T
[src]pub fn overflowing_as<Dst>(self) -> (Dst, bool) where
T: OverflowingCast<Dst>,
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pub fn overflowing_as<Dst>(self) -> (Dst, bool) where
T: OverflowingCast<Dst>,
[src]Casts the value.
impl<T> Same<T> for T
impl<T> Same<T> for T
type Output = T
type Output = T
Should always be Self
impl<T> SaturatingAs for T
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impl<T> SaturatingAs for T
[src]pub fn saturating_as<Dst>(self) -> Dst where
T: SaturatingCast<Dst>,
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pub fn saturating_as<Dst>(self) -> Dst where
T: SaturatingCast<Dst>,
[src]Casts the value.
impl<T> UnwrappedAs for T
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impl<T> UnwrappedAs for T
[src]pub fn unwrapped_as<Dst>(self) -> Dst where
T: UnwrappedCast<Dst>,
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pub fn unwrapped_as<Dst>(self) -> Dst where
T: UnwrappedCast<Dst>,
[src]Casts the value.
impl<T> WrappingAs for T
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impl<T> WrappingAs for T
[src]pub fn wrapping_as<Dst>(self) -> Dst where
T: WrappingCast<Dst>,
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pub fn wrapping_as<Dst>(self) -> Dst where
T: WrappingCast<Dst>,
[src]Casts the value.