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Peripheral access API (generated using chiptool v0.1.0 (6a8c2aa 2026-01-27))

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ACPI_EC0: The ACPI-ECI provides a four byte full duplex data interface.
ACPI_EC1
ACPI_EC2
ACPI_EC3
ADC: This block is designed to convert external analog voltage readings into digital values.
CCT: This is a 16-bit auto-reloading timer/counter.
DMA_CHAN00: DMA Channel 00 Registers
DMA_CHAN01: DMA Channel 01 Registers
DMA_CHAN02: DMA Channel 02 Registers
DMA_CHAN03
DMA_CHAN04
DMA_CHAN05
DMA_CHAN06
DMA_CHAN07
DMA_CHAN08
DMA_CHAN09
DMA_CHAN10
DMA_CHAN11
DMA_MAIN: DMA Main Registers
ECIA: The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
EC_REG_BANK: This block is designed to be accessed internally by the EC via the register interface.
EMI0: The EMI provides a communication between system host and Embedded Controller
EMI1
ESPI_IO: The ESPI is used by the system host to configure the chip and communicate with the logical devices implemented in the design
ESPI_MEMORY: The eSPI Memory Component is one of two Logical Devices (along with the I/O Component) that provide access to all the registers in the device.
ESPI_MSVW00_06: The ESPI VW Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC
ESPI_MSVW07_10: The ESPI VW Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC
ESPI_SCRATCH: 32 Byte ESPI Test Register
ESPI_SMVW00_10: The ESPI VW Channel permits the System to emulate a set of wires that interconnect the system Core Logic with the EC
GCR: The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
GPIO: GPIO Pin Control Registers
HDMI_CEC: The HDMI-CEC provides high-level control functions between all the various audiovisual products in a users environment.
HTM0: The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode
HTM1
I2C0: The I2C interface can handle standard I2C interface.
I2C1
I2C2
KBC: The Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042 behavior
KMS: The Keyboard Scan Interface block provides a register interface to directly scan an external keyboard matrix of size up to 18x8.
LED0: The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
LED1
LED2
MBX: The Mailbox provides a standard run-time mechanism for the host to communicate with the Embedded Controller (EC).
NVIC: Nested Vectored Interrupt Controller
OTP: OTP Programming registers.
PCR: The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip
PECI: The PECI Interface allows the EC to retrieve temperature readings from PECI-compliant devices.
PHOT: This block monitors the PROCHOT# signal generated by the host processor. It is designed to detect single assertions and monitor cumulative PROCHOT active time.
PM1: These features comply with the ACPI Specification through a combination of hardware and EC software
PORT92: The registers listed in the Configuration Register Summary table are for a single instance of the Legacy Port92/GATEA20 logic.
PORT_80_DEBUG0: Diagnostic data is written by the Host Interface to the Port 80 BIOS Debug Port
PORT_80_DEBUG1
PS2_0: The four PS/2 Ports implementation eliminates the need to bit bang I/O ports to generate PS/2 traffic
PS2_1
PWM0: The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
QMSPI: The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface
RTC: This is the set of registers that are automatically counted by hardware every 1 second while the block is enabled
RTOS: RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
SAFBC: SAF BRIDGE COMPONENT
SAFCOMM: This region contains one register “SAF Communication Mode” that may (and should) be set for optimal SAFS operation
SMB0: The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
SMB1
SMB2
SMB3
SMB4
SPI_SLAVE: SPI Slave Register.
SYSTEMCONTROL: System Control Registers
SYSTICK: System timer
TACH0: This block monitors TACH output signals from various types of fans, and determines their speed.
TACH1
TACH2
TACH3
TFDP: The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
TIMER16_0: This 16-bit timer block offers a simple mechanism for firmware to maintain a time base
TIMER16_1
TIMER32_0: This 32-bit timer block offers a simple mechanism for firmware to maintain a time base
TIMER32_1
UART0: The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
UART1
UART2
VBAT: The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers
VBAT_RAM: The VBAT RAM is operational while the main power rail is operational, and will retain its values powered by battery power while the main rail is unpowered.
VCI: The VBAT-Powered Control Interfaces with the RTC With Date and DST Adjustment as well as the Week Alarm.
WDT: The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
WEEK: The Week Timer and the Sub-Week Timer assert the Power-Up Event Output which automatically powers-up the system from the G3 state

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