mcxn947_pac/i3c0/
mwmsg_ddr_mwmsg_ddr_control2.rs

1#[doc = "Register `MWMSG_DDR_CONTROL2` writer"]
2pub type W = crate::W<MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC>;
3#[doc = "Field `LEN` writer - Length of Message"]
4pub type LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
5#[doc = "End of message\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum END_AW {
8    #[doc = "0: Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message)."]
9    NOT_END = 0,
10    #[doc = "1: End. DDR message ends on HDR Exit."]
11    END = 1,
12}
13impl From<END_AW> for bool {
14    #[inline(always)]
15    fn from(variant: END_AW) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `END` writer - End of message"]
20pub type END_W<'a, REG> = crate::BitWriter<'a, REG, END_AW>;
21impl<'a, REG> END_W<'a, REG>
22where
23    REG: crate::Writable + crate::RegisterSpec,
24{
25    #[doc = "Not the end. DDR message ends waiting for a new DDR message (will issue a HDR Restart for the new message)."]
26    #[inline(always)]
27    pub fn not_end(self) -> &'a mut crate::W<REG> {
28        self.variant(END_AW::NOT_END)
29    }
30    #[doc = "End. DDR message ends on HDR Exit."]
31    #[inline(always)]
32    pub fn end(self) -> &'a mut crate::W<REG> {
33        self.variant(END_AW::END)
34    }
35}
36impl W {
37    #[doc = "Bits 0:9 - Length of Message"]
38    #[inline(always)]
39    #[must_use]
40    pub fn len(&mut self) -> LEN_W<MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC> {
41        LEN_W::new(self, 0)
42    }
43    #[doc = "Bit 14 - End of message"]
44    #[inline(always)]
45    #[must_use]
46    pub fn end(&mut self) -> END_W<MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC> {
47        END_W::new(self, 14)
48    }
49    #[doc = r" Writes raw bits to the register."]
50    #[doc = r""]
51    #[doc = r" # Safety"]
52    #[doc = r""]
53    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
54    #[inline(always)]
55    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
56        self.bits = bits;
57        self
58    }
59}
60#[doc = "Controller Write Message in DDR mode Control 2\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mwmsg_ddr_mwmsg_ddr_control2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC;
62impl crate::RegisterSpec for MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC {
63    type Ux = u32;
64}
65#[doc = "`write(|w| ..)` method takes [`mwmsg_ddr_mwmsg_ddr_control2::W`](W) writer structure"]
66impl crate::Writable for MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC {
67    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69}
70#[doc = "`reset()` method sets MWMSG_DDR_CONTROL2 to value 0"]
71impl crate::Resettable for MWMSG_DDR_MWMSG_DDR_CONTROL2_SPEC {
72    const RESET_VALUE: u32 = 0;
73}
mcxn947_pac/i3c0/mwmsg_ddr_mwmsg_ddr_control2.rs

mcxn947_pac/i3c0/
mwmsg_ddr_mwmsg_ddr_control2.rs
