Module mcxn947_pac::ahbsc
source · Expand description
AHBSC
Re-exports§
pub use self::flexspi0_region1_6_mem_rule::FLEXSPI0_REGION1_6_MEM_RULE;
pub use self::flexspi0_region8_13_mem_rule::FLEXSPI0_REGION8_13_MEM_RULE;
Modules§
- AHB Peripheral 0 Slave Port 12 Slave Rule 0
- AHB Peripheral 0 Slave Port 12 Slave Rule 1
- AHB Peripheral 0 Slave Port 12 Slave Rule 2
- AHB Peripheral 1 Slave Port 13 Slave Rule 0
- AHB Peripheral 1 Slave Port 13 Slave Rule 1
- AHB Peripheral 1 Slave Port 13 Slave Rule 2
- AHB Secure Control Peripheral Rule 0
- AIPS Bridge Group 0 Memory Rule 0
- AIPS Bridge Group 0 Memory Rule 1
- AIPS Bridge Group 0 Memory Rule 2
- AIPS Bridge Group 0 Memory Rule 3
- AIPS Bridge Group 1 Rule 0
- AIPS Bridge Group 1 Rule 1
- AIPS Bridge Group 2 Rule 0
- AIPS Bridge Group 2 Memory Rule 1
- AIPS Bridge Group 3 Rule 0
- AIPS Bridge Group 3 Memory Rule 1
- AIPS Bridge Group 3 Rule 2
- AIPS Bridge Group 3 Rule 3
- AIPS Bridge Group 4 Rule 0
- AIPS Bridge Group 4 Rule 1
- AIPS Bridge Group 4 Rule 2
- AIPS Bridge Group 4 Rule 3
- APB Bridge Group 0 Memory Rule 0
- APB Bridge Group 0 Memory Rule 1
- APB Bridge Group 0 Rule 2
- APB Bridge Group 0 Memory Rule 3
- APB Bridge Group 1 Memory Rule 0
- APB Bridge Group 1 Memory Rule 1
- APB Bridge Group 1 Memory Rule 2
- Miscellaneous CPU0 Control Signals
- Miscellaneous CPU1 Control Signals
- Flash Memory Rule
- Flash Memory Rule
- Flash Memory Rule
- Flash Memory Rule
- FLEXSPI0 Region 0 Memory Rule
- Cluster no description available
- FLEXSPI0 Region 7 Memory Rule
- Cluster no description available
- Master Secure Level
- Master Secure Level
- Secure Control Duplicate
- Secure Control
- RAMA Memory Rule 0
- RAMB Memory Rule
- RAMC Memory Rule
- RAMD Memory Rule
- RAME Memory Rule
- RAMF Memory Rule
- RAMG Memory Rule
- RAMH Memory Rule
- RAMX Memory Rule
- ROM Memory Rule
- Secure Interrupt Mask 0 for CPU1
- Secure Interrupt Mask 1 for CPU1
- Secure Interrupt Mask 2 for CPU1
- Secure Interrupt Mask 3 for CPU1
- Secure Interrupt Mask 4 for CPU1
- Secure Mask Lock
- GPIO Mask for Port index
- Security Violation Address
- Security Violation Info Validity for Address
- Security Violation Miscellaneous Information at Address
Structs§
- Register block
Type Aliases§
- AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 0
- AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 1
- AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 2
- AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 0
- AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 1
- AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 2
- AHB_SECURE_CTRL_PERIPHERAL_RULE0 (rw) register accessor: AHB Secure Control Peripheral Rule 0
- AIPS_BRIDGE_GROUP0_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 0
- AIPS_BRIDGE_GROUP0_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 1
- AIPS_BRIDGE_GROUP0_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 2
- AIPS_BRIDGE_GROUP0_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 3
- AIPS_BRIDGE_GROUP1_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 1 Rule 0
- AIPS_BRIDGE_GROUP1_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 1 Rule 1
- AIPS_BRIDGE_GROUP2_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 2 Rule 0
- AIPS_BRIDGE_GROUP2_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 2 Memory Rule 1
- AIPS_BRIDGE_GROUP3_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 3 Rule 0
- AIPS_BRIDGE_GROUP3_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 3 Memory Rule 1
- AIPS_BRIDGE_GROUP3_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 3 Rule 2
- AIPS_BRIDGE_GROUP3_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 3 Rule 3
- AIPS_BRIDGE_GROUP4_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 4 Rule 0
- AIPS_BRIDGE_GROUP4_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 4 Rule 1
- AIPS_BRIDGE_GROUP4_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 4 Rule 2
- AIPS_BRIDGE_GROUP4_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 4 Rule 3
- APB_PERIPHERAL_GROUP0_MEM_RULE0 (rw) register accessor: APB Bridge Group 0 Memory Rule 0
- APB_PERIPHERAL_GROUP0_MEM_RULE1 (rw) register accessor: APB Bridge Group 0 Memory Rule 1
- APB_PERIPHERAL_GROUP0_MEM_RULE2 (rw) register accessor: APB Bridge Group 0 Rule 2
- APB_PERIPHERAL_GROUP0_MEM_RULE3 (rw) register accessor: APB Bridge Group 0 Memory Rule 3
- APB_PERIPHERAL_GROUP1_MEM_RULE0 (rw) register accessor: APB Bridge Group 1 Memory Rule 0
- APB_PERIPHERAL_GROUP1_MEM_RULE1 (rw) register accessor: APB Bridge Group 1 Memory Rule 1
- APB_PERIPHERAL_GROUP1_MEM_RULE2 (rw) register accessor: APB Bridge Group 1 Memory Rule 2
- CPU0_LOCK_REG (rw) register accessor: Miscellaneous CPU0 Control Signals
- CPU1_LOCK_REG (rw) register accessor: Miscellaneous CPU1 Control Signals
- FLASH00_MEM_RULE (rw) register accessor: Flash Memory Rule
- FLASH01_MEM_RULE (rw) register accessor: Flash Memory Rule
- FLASH02_MEM_RULE (rw) register accessor: Flash Memory Rule
- FLASH03_MEM_RULE (rw) register accessor: Flash Memory Rule
- FLEXSPI0_REGION0_MEM_RULE (rw) register accessor: FLEXSPI0 Region 0 Memory Rule
- FLEXSPI0_REGION7_MEM_RULE (rw) register accessor: FLEXSPI0 Region 7 Memory Rule
- MASTER_SEC_ANTI_POL_REG (rw) register accessor: Master Secure Level
- MASTER_SEC_LEVEL (rw) register accessor: Master Secure Level
- MISC_CTRL_DP_REG (rw) register accessor: Secure Control Duplicate
- MISC_CTRL_REG (rw) register accessor: Secure Control
- RAMA_MEM_RULE (rw) register accessor: RAMA Memory Rule 0
- RAMB_MEM_RULE (rw) register accessor: RAMB Memory Rule
- RAMC_MEM_RULE (rw) register accessor: RAMC Memory Rule
- RAMD_MEM_RULE (rw) register accessor: RAMD Memory Rule
- RAME_MEM_RULE (rw) register accessor: RAME Memory Rule
- RAMF_MEM_RULE (rw) register accessor: RAMF Memory Rule
- RAMG_MEM_RULE (rw) register accessor: RAMG Memory Rule
- RAMH_MEM_RULE (rw) register accessor: RAMH Memory Rule
- RAMX_MEM_RULE (rw) register accessor: RAMX Memory Rule
- ROM_MEM_RULE (rw) register accessor: ROM Memory Rule
- SEC_CPU1_INT_MASK0 (rw) register accessor: Secure Interrupt Mask 0 for CPU1
- SEC_CPU1_INT_MASK1 (rw) register accessor: Secure Interrupt Mask 1 for CPU1
- SEC_CPU1_INT_MASK2 (rw) register accessor: Secure Interrupt Mask 2 for CPU1
- SEC_CPU1_INT_MASK3 (rw) register accessor: Secure Interrupt Mask 3 for CPU1
- SEC_CPU1_INT_MASK4 (rw) register accessor: Secure Interrupt Mask 4 for CPU1
- SEC_GPIO_MASK (rw) register accessor: GPIO Mask for Port index
- SEC_GP_REG_LOCK (rw) register accessor: Secure Mask Lock
- SEC_VIO_ADDR (r) register accessor: Security Violation Address
- SEC_VIO_INFO_VALID (rw) register accessor: Security Violation Info Validity for Address
- SEC_VIO_MISC_INFO (r) register accessor: Security Violation Miscellaneous Information at Address