Module mcxn947_pac::lpspi0
source · Expand description
LPSPI
Modules§
- Clock Configuration
- Clock Configuration 1
- Configuration 0
- Configuration 1
- Control
- DMA Enable
- Data Match 0
- Data Match 1
- FIFO Control
- FIFO Status
- Interrupt Enable
- Parameter
- Receive Data Burst
- Receive Data
- Receive Data Read Only
- Receive Status
- Status
- Transmit Command Burst
- Transmit Command
- Transmit Data Burst
- Transmit Data
- Version ID
Structs§
- Register block
Type Aliases§
- CCR (rw) register accessor: Clock Configuration
- CCR1 (rw) register accessor: Clock Configuration 1
- CFGR0 (rw) register accessor: Configuration 0
- CFGR1 (rw) register accessor: Configuration 1
- CR (rw) register accessor: Control
- DER (rw) register accessor: DMA Enable
- DMR0 (rw) register accessor: Data Match 0
- DMR1 (rw) register accessor: Data Match 1
- FCR (rw) register accessor: FIFO Control
- FSR (r) register accessor: FIFO Status
- IER (rw) register accessor: Interrupt Enable
- PARAM (r) register accessor: Parameter
- RDBR (r) register accessor: Receive Data Burst
- RDR (r) register accessor: Receive Data
- RDROR (r) register accessor: Receive Data Read Only
- RSR (r) register accessor: Receive Status
- SR (rw) register accessor: Status
- TCBR (w) register accessor: Transmit Command Burst
- TCR (rw) register accessor: Transmit Command
- TDBR (w) register accessor: Transmit Data Burst
- TDR (w) register accessor: Transmit Data
- VERID (r) register accessor: Version ID