mcxa_pac/usb0/
otgicr.rs

1#[doc = "Register `OTGICR` reader"]
2pub type R = crate::R<OtgicrSpec>;
3#[doc = "Register `OTGICR` writer"]
4pub type W = crate::W<OtgicrSpec>;
5#[doc = "Line State Change Interrupt Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Linestateen {
9    #[doc = "0: Disable"]
10    DisLinestInt = 0,
11    #[doc = "1: Enable"]
12    EnLinestInt = 1,
13}
14impl From<Linestateen> for bool {
15    #[inline(always)]
16    fn from(variant: Linestateen) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `LINESTATEEN` reader - Line State Change Interrupt Enable"]
21pub type LinestateenR = crate::BitReader<Linestateen>;
22impl LinestateenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Linestateen {
26        match self.bits {
27            false => Linestateen::DisLinestInt,
28            true => Linestateen::EnLinestInt,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_dis_linest_int(&self) -> bool {
34        *self == Linestateen::DisLinestInt
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_en_linest_int(&self) -> bool {
39        *self == Linestateen::EnLinestInt
40    }
41}
42#[doc = "Field `LINESTATEEN` writer - Line State Change Interrupt Enable"]
43pub type LinestateenW<'a, REG> = crate::BitWriter<'a, REG, Linestateen>;
44impl<'a, REG> LinestateenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn dis_linest_int(self) -> &'a mut crate::W<REG> {
51        self.variant(Linestateen::DisLinestInt)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn en_linest_int(self) -> &'a mut crate::W<REG> {
56        self.variant(Linestateen::EnLinestInt)
57    }
58}
59#[doc = "1-Millisecond Interrupt Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Onemsecen {
63    #[doc = "0: Disable"]
64    DisTimerInt = 0,
65    #[doc = "1: Enable"]
66    EnTimerInt = 1,
67}
68impl From<Onemsecen> for bool {
69    #[inline(always)]
70    fn from(variant: Onemsecen) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ONEMSECEN` reader - 1-Millisecond Interrupt Enable"]
75pub type OnemsecenR = crate::BitReader<Onemsecen>;
76impl OnemsecenR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Onemsecen {
80        match self.bits {
81            false => Onemsecen::DisTimerInt,
82            true => Onemsecen::EnTimerInt,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_dis_timer_int(&self) -> bool {
88        *self == Onemsecen::DisTimerInt
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_en_timer_int(&self) -> bool {
93        *self == Onemsecen::EnTimerInt
94    }
95}
96#[doc = "Field `ONEMSECEN` writer - 1-Millisecond Interrupt Enable"]
97pub type OnemsecenW<'a, REG> = crate::BitWriter<'a, REG, Onemsecen>;
98impl<'a, REG> OnemsecenW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn dis_timer_int(self) -> &'a mut crate::W<REG> {
105        self.variant(Onemsecen::DisTimerInt)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn en_timer_int(self) -> &'a mut crate::W<REG> {
110        self.variant(Onemsecen::EnTimerInt)
111    }
112}
113impl R {
114    #[doc = "Bit 5 - Line State Change Interrupt Enable"]
115    #[inline(always)]
116    pub fn linestateen(&self) -> LinestateenR {
117        LinestateenR::new(((self.bits >> 5) & 1) != 0)
118    }
119    #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"]
120    #[inline(always)]
121    pub fn onemsecen(&self) -> OnemsecenR {
122        OnemsecenR::new(((self.bits >> 6) & 1) != 0)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("OTGICR")
129            .field("linestateen", &self.linestateen())
130            .field("onemsecen", &self.onemsecen())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 5 - Line State Change Interrupt Enable"]
136    #[inline(always)]
137    pub fn linestateen(&mut self) -> LinestateenW<'_, OtgicrSpec> {
138        LinestateenW::new(self, 5)
139    }
140    #[doc = "Bit 6 - 1-Millisecond Interrupt Enable"]
141    #[inline(always)]
142    pub fn onemsecen(&mut self) -> OnemsecenW<'_, OtgicrSpec> {
143        OnemsecenW::new(self, 6)
144    }
145}
146#[doc = "OTG Interrupt Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct OtgicrSpec;
148impl crate::RegisterSpec for OtgicrSpec {
149    type Ux = u8;
150}
151#[doc = "`read()` method returns [`otgicr::R`](R) reader structure"]
152impl crate::Readable for OtgicrSpec {}
153#[doc = "`write(|w| ..)` method takes [`otgicr::W`](W) writer structure"]
154impl crate::Writable for OtgicrSpec {
155    type Safety = crate::Unsafe;
156}
157#[doc = "`reset()` method sets OTGICR to value 0"]
158impl crate::Resettable for OtgicrSpec {}
mcxa_pac/usb0/otgicr.rs

mcxa_pac/usb0/
otgicr.rs
