mcxa_pac/trng0/
sblim.rs

1#[doc = "Register `SBLIM` reader"]
2pub type R = crate::R<SblimSpec>;
3#[doc = "Register `SBLIM` writer"]
4pub type W = crate::W<SblimSpec>;
5#[doc = "Field `SB_LIM` reader - Sparse Bit Limit"]
6pub type SbLimR = crate::FieldReader<u16>;
7#[doc = "Field `SB_LIM` writer - Sparse Bit Limit"]
8pub type SbLimW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9impl R {
10    #[doc = "Bits 0:9 - Sparse Bit Limit"]
11    #[inline(always)]
12    pub fn sb_lim(&self) -> SbLimR {
13        SbLimR::new((self.bits & 0x03ff) as u16)
14    }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("SBLIM").field("sb_lim", &self.sb_lim()).finish()
20    }
21}
22impl W {
23    #[doc = "Bits 0:9 - Sparse Bit Limit"]
24    #[inline(always)]
25    pub fn sb_lim(&mut self) -> SbLimW<'_, SblimSpec> {
26        SbLimW::new(self, 0)
27    }
28}
29#[doc = "Sparse Bit Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sblim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sblim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct SblimSpec;
31impl crate::RegisterSpec for SblimSpec {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`sblim::R`](R) reader structure"]
35impl crate::Readable for SblimSpec {}
36#[doc = "`write(|w| ..)` method takes [`sblim::W`](W) writer structure"]
37impl crate::Writable for SblimSpec {
38    type Safety = crate::Unsafe;
39}
40#[doc = "`reset()` method sets SBLIM to value 0x3f"]
41impl crate::Resettable for SblimSpec {
42    const RESET_VALUE: u32 = 0x3f;
43}
mcxa_pac/trng0/sblim.rs

mcxa_pac/trng0/
sblim.rs
