mcxa_pac/trng0/
osc2_ctl.rs

1#[doc = "Register `OSC2_CTL` reader"]
2pub type R = crate::R<Osc2CtlSpec>;
3#[doc = "Register `OSC2_CTL` writer"]
4pub type W = crate::W<Osc2CtlSpec>;
5#[doc = "TRNG entropy generation control.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum TrngEntCtl {
10    #[doc = "0: Single oscillator mode, using OSC1 (default)"]
11    TrngEntCtlSingleOsc1 = 0,
12    #[doc = "1: Dual oscillator mode"]
13    TrngEntCtlDualOscs = 1,
14    #[doc = "2: Single oscillator mode, using OSC2"]
15    TrngEntCtlSingleOsc2 = 2,
16    #[doc = "3: Unused, (bit field cannot be written to this value)"]
17    Osc2DivDiv8 = 3,
18}
19impl From<TrngEntCtl> for u8 {
20    #[inline(always)]
21    fn from(variant: TrngEntCtl) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for TrngEntCtl {
26    type Ux = u8;
27}
28impl crate::IsEnum for TrngEntCtl {}
29#[doc = "Field `TRNG_ENT_CTL` reader - TRNG entropy generation control."]
30pub type TrngEntCtlR = crate::FieldReader<TrngEntCtl>;
31impl TrngEntCtlR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> TrngEntCtl {
35        match self.bits {
36            0 => TrngEntCtl::TrngEntCtlSingleOsc1,
37            1 => TrngEntCtl::TrngEntCtlDualOscs,
38            2 => TrngEntCtl::TrngEntCtlSingleOsc2,
39            3 => TrngEntCtl::Osc2DivDiv8,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "Single oscillator mode, using OSC1 (default)"]
44    #[inline(always)]
45    pub fn is_trng_ent_ctl_single_osc1(&self) -> bool {
46        *self == TrngEntCtl::TrngEntCtlSingleOsc1
47    }
48    #[doc = "Dual oscillator mode"]
49    #[inline(always)]
50    pub fn is_trng_ent_ctl_dual_oscs(&self) -> bool {
51        *self == TrngEntCtl::TrngEntCtlDualOscs
52    }
53    #[doc = "Single oscillator mode, using OSC2"]
54    #[inline(always)]
55    pub fn is_trng_ent_ctl_single_osc2(&self) -> bool {
56        *self == TrngEntCtl::TrngEntCtlSingleOsc2
57    }
58    #[doc = "Unused, (bit field cannot be written to this value)"]
59    #[inline(always)]
60    pub fn is_osc2_div_div8(&self) -> bool {
61        *self == TrngEntCtl::Osc2DivDiv8
62    }
63}
64#[doc = "Field `TRNG_ENT_CTL` writer - TRNG entropy generation control."]
65pub type TrngEntCtlW<'a, REG> = crate::FieldWriter<'a, REG, 2, TrngEntCtl, crate::Safe>;
66impl<'a, REG> TrngEntCtlW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "Single oscillator mode, using OSC1 (default)"]
72    #[inline(always)]
73    pub fn trng_ent_ctl_single_osc1(self) -> &'a mut crate::W<REG> {
74        self.variant(TrngEntCtl::TrngEntCtlSingleOsc1)
75    }
76    #[doc = "Dual oscillator mode"]
77    #[inline(always)]
78    pub fn trng_ent_ctl_dual_oscs(self) -> &'a mut crate::W<REG> {
79        self.variant(TrngEntCtl::TrngEntCtlDualOscs)
80    }
81    #[doc = "Single oscillator mode, using OSC2"]
82    #[inline(always)]
83    pub fn trng_ent_ctl_single_osc2(self) -> &'a mut crate::W<REG> {
84        self.variant(TrngEntCtl::TrngEntCtlSingleOsc2)
85    }
86    #[doc = "Unused, (bit field cannot be written to this value)"]
87    #[inline(always)]
88    pub fn osc2_div_div8(self) -> &'a mut crate::W<REG> {
89        self.variant(TrngEntCtl::Osc2DivDiv8)
90    }
91}
92#[doc = "Oscillator 2 Divide.\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum Osc2Div {
97    #[doc = "0: Use ring oscillator 2 with no divide"]
98    Osc2DivDiv1 = 0,
99    #[doc = "1: Use ring oscillator 2 divided-by-2"]
100    Osc2DivDiv2 = 1,
101    #[doc = "2: Use ring oscillator 2 divided-by-4"]
102    Osc2DivDiv4 = 2,
103    #[doc = "3: Use ring oscillator 2 divided-by-8"]
104    Osc2DivDiv8 = 3,
105}
106impl From<Osc2Div> for u8 {
107    #[inline(always)]
108    fn from(variant: Osc2Div) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for Osc2Div {
113    type Ux = u8;
114}
115impl crate::IsEnum for Osc2Div {}
116#[doc = "Field `OSC2_DIV` reader - Oscillator 2 Divide."]
117pub type Osc2DivR = crate::FieldReader<Osc2Div>;
118impl Osc2DivR {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> Osc2Div {
122        match self.bits {
123            0 => Osc2Div::Osc2DivDiv1,
124            1 => Osc2Div::Osc2DivDiv2,
125            2 => Osc2Div::Osc2DivDiv4,
126            3 => Osc2Div::Osc2DivDiv8,
127            _ => unreachable!(),
128        }
129    }
130    #[doc = "Use ring oscillator 2 with no divide"]
131    #[inline(always)]
132    pub fn is_osc2_div_div1(&self) -> bool {
133        *self == Osc2Div::Osc2DivDiv1
134    }
135    #[doc = "Use ring oscillator 2 divided-by-2"]
136    #[inline(always)]
137    pub fn is_osc2_div_div2(&self) -> bool {
138        *self == Osc2Div::Osc2DivDiv2
139    }
140    #[doc = "Use ring oscillator 2 divided-by-4"]
141    #[inline(always)]
142    pub fn is_osc2_div_div4(&self) -> bool {
143        *self == Osc2Div::Osc2DivDiv4
144    }
145    #[doc = "Use ring oscillator 2 divided-by-8"]
146    #[inline(always)]
147    pub fn is_osc2_div_div8(&self) -> bool {
148        *self == Osc2Div::Osc2DivDiv8
149    }
150}
151#[doc = "Field `OSC2_DIV` writer - Oscillator 2 Divide."]
152pub type Osc2DivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Osc2Div, crate::Safe>;
153impl<'a, REG> Osc2DivW<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "Use ring oscillator 2 with no divide"]
159    #[inline(always)]
160    pub fn osc2_div_div1(self) -> &'a mut crate::W<REG> {
161        self.variant(Osc2Div::Osc2DivDiv1)
162    }
163    #[doc = "Use ring oscillator 2 divided-by-2"]
164    #[inline(always)]
165    pub fn osc2_div_div2(self) -> &'a mut crate::W<REG> {
166        self.variant(Osc2Div::Osc2DivDiv2)
167    }
168    #[doc = "Use ring oscillator 2 divided-by-4"]
169    #[inline(always)]
170    pub fn osc2_div_div4(self) -> &'a mut crate::W<REG> {
171        self.variant(Osc2Div::Osc2DivDiv4)
172    }
173    #[doc = "Use ring oscillator 2 divided-by-8"]
174    #[inline(always)]
175    pub fn osc2_div_div8(self) -> &'a mut crate::W<REG> {
176        self.variant(Osc2Div::Osc2DivDiv8)
177    }
178}
179#[doc = "Oscillator 2 Clock Output Enable\n\nValue on reset: 0"]
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182pub enum Osc2OutEn {
183    #[doc = "0: Ring oscillator 2 output is gated to an output pad."]
184    Osc2OutEn0 = 0,
185    #[doc = "1: Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."]
186    Osc2OutEn1 = 1,
187}
188impl From<Osc2OutEn> for bool {
189    #[inline(always)]
190    fn from(variant: Osc2OutEn) -> Self {
191        variant as u8 != 0
192    }
193}
194#[doc = "Field `OSC2_OUT_EN` reader - Oscillator 2 Clock Output Enable"]
195pub type Osc2OutEnR = crate::BitReader<Osc2OutEn>;
196impl Osc2OutEnR {
197    #[doc = "Get enumerated values variant"]
198    #[inline(always)]
199    pub const fn variant(&self) -> Osc2OutEn {
200        match self.bits {
201            false => Osc2OutEn::Osc2OutEn0,
202            true => Osc2OutEn::Osc2OutEn1,
203        }
204    }
205    #[doc = "Ring oscillator 2 output is gated to an output pad."]
206    #[inline(always)]
207    pub fn is_osc2_out_en_0(&self) -> bool {
208        *self == Osc2OutEn::Osc2OutEn0
209    }
210    #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."]
211    #[inline(always)]
212    pub fn is_osc2_out_en_1(&self) -> bool {
213        *self == Osc2OutEn::Osc2OutEn1
214    }
215}
216#[doc = "Field `OSC2_OUT_EN` writer - Oscillator 2 Clock Output Enable"]
217pub type Osc2OutEnW<'a, REG> = crate::BitWriter<'a, REG, Osc2OutEn>;
218impl<'a, REG> Osc2OutEnW<'a, REG>
219where
220    REG: crate::Writable + crate::RegisterSpec,
221{
222    #[doc = "Ring oscillator 2 output is gated to an output pad."]
223    #[inline(always)]
224    pub fn osc2_out_en_0(self) -> &'a mut crate::W<REG> {
225        self.variant(Osc2OutEn::Osc2OutEn0)
226    }
227    #[doc = "Allows external viewing of divided-by-2 ring oscillator 2 if MCTL\\[PRGM\\] = 1 mode is also selected, else ring oscillator 2 output is gated to an output pad."]
228    #[inline(always)]
229    pub fn osc2_out_en_1(self) -> &'a mut crate::W<REG> {
230        self.variant(Osc2OutEn::Osc2OutEn1)
231    }
232}
233#[doc = "TRNG Oscillator 2 Frequency Count Valid\n\nValue on reset: 0"]
234#[cfg_attr(feature = "defmt", derive(defmt::Format))]
235#[derive(Clone, Copy, Debug, PartialEq, Eq)]
236pub enum Osc2FctVal {
237    #[doc = "0: Frequency count is invalid."]
238    Disable = 0,
239    #[doc = "1: If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."]
240    Enable = 1,
241}
242impl From<Osc2FctVal> for bool {
243    #[inline(always)]
244    fn from(variant: Osc2FctVal) -> Self {
245        variant as u8 != 0
246    }
247}
248#[doc = "Field `OSC2_FCT_VAL` reader - TRNG Oscillator 2 Frequency Count Valid"]
249pub type Osc2FctValR = crate::BitReader<Osc2FctVal>;
250impl Osc2FctValR {
251    #[doc = "Get enumerated values variant"]
252    #[inline(always)]
253    pub const fn variant(&self) -> Osc2FctVal {
254        match self.bits {
255            false => Osc2FctVal::Disable,
256            true => Osc2FctVal::Enable,
257        }
258    }
259    #[doc = "Frequency count is invalid."]
260    #[inline(always)]
261    pub fn is_disable(&self) -> bool {
262        *self == Osc2FctVal::Disable
263    }
264    #[doc = "If TRNG_ENT_CTL = 10b, valid frequency count may be read from OSC2_FRQCNT."]
265    #[inline(always)]
266    pub fn is_enable(&self) -> bool {
267        *self == Osc2FctVal::Enable
268    }
269}
270#[doc = "Oscillator fail safe limit.\n\nValue on reset: 1"]
271#[cfg_attr(feature = "defmt", derive(defmt::Format))]
272#[derive(Clone, Copy, Debug, PartialEq, Eq)]
273#[repr(u8)]
274pub enum OscFailsafeLmt {
275    #[doc = "0: The limit N is 4096 (2^12) system clocks."]
276    OscFailsafeLmt4k = 0,
277    #[doc = "1: The limit N is 65536 (2^16) system clocks. (default)"]
278    OscFailsafeLmt64k = 1,
279    #[doc = "2: N is 2^20 system clocks."]
280    OscFailsafeLmt1m = 2,
281    #[doc = "3: N is 2^22 system clocks (full range of the counter being used)."]
282    OscFailsafeLmt4m = 3,
283}
284impl From<OscFailsafeLmt> for u8 {
285    #[inline(always)]
286    fn from(variant: OscFailsafeLmt) -> Self {
287        variant as _
288    }
289}
290impl crate::FieldSpec for OscFailsafeLmt {
291    type Ux = u8;
292}
293impl crate::IsEnum for OscFailsafeLmt {}
294#[doc = "Field `OSC_FAILSAFE_LMT` reader - Oscillator fail safe limit."]
295pub type OscFailsafeLmtR = crate::FieldReader<OscFailsafeLmt>;
296impl OscFailsafeLmtR {
297    #[doc = "Get enumerated values variant"]
298    #[inline(always)]
299    pub const fn variant(&self) -> OscFailsafeLmt {
300        match self.bits {
301            0 => OscFailsafeLmt::OscFailsafeLmt4k,
302            1 => OscFailsafeLmt::OscFailsafeLmt64k,
303            2 => OscFailsafeLmt::OscFailsafeLmt1m,
304            3 => OscFailsafeLmt::OscFailsafeLmt4m,
305            _ => unreachable!(),
306        }
307    }
308    #[doc = "The limit N is 4096 (2^12) system clocks."]
309    #[inline(always)]
310    pub fn is_osc_failsafe_lmt_4k(&self) -> bool {
311        *self == OscFailsafeLmt::OscFailsafeLmt4k
312    }
313    #[doc = "The limit N is 65536 (2^16) system clocks. (default)"]
314    #[inline(always)]
315    pub fn is_osc_failsafe_lmt_64k(&self) -> bool {
316        *self == OscFailsafeLmt::OscFailsafeLmt64k
317    }
318    #[doc = "N is 2^20 system clocks."]
319    #[inline(always)]
320    pub fn is_osc_failsafe_lmt_1m(&self) -> bool {
321        *self == OscFailsafeLmt::OscFailsafeLmt1m
322    }
323    #[doc = "N is 2^22 system clocks (full range of the counter being used)."]
324    #[inline(always)]
325    pub fn is_osc_failsafe_lmt_4m(&self) -> bool {
326        *self == OscFailsafeLmt::OscFailsafeLmt4m
327    }
328}
329#[doc = "Field `OSC_FAILSAFE_LMT` writer - Oscillator fail safe limit."]
330pub type OscFailsafeLmtW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscFailsafeLmt, crate::Safe>;
331impl<'a, REG> OscFailsafeLmtW<'a, REG>
332where
333    REG: crate::Writable + crate::RegisterSpec,
334    REG::Ux: From<u8>,
335{
336    #[doc = "The limit N is 4096 (2^12) system clocks."]
337    #[inline(always)]
338    pub fn osc_failsafe_lmt_4k(self) -> &'a mut crate::W<REG> {
339        self.variant(OscFailsafeLmt::OscFailsafeLmt4k)
340    }
341    #[doc = "The limit N is 65536 (2^16) system clocks. (default)"]
342    #[inline(always)]
343    pub fn osc_failsafe_lmt_64k(self) -> &'a mut crate::W<REG> {
344        self.variant(OscFailsafeLmt::OscFailsafeLmt64k)
345    }
346    #[doc = "N is 2^20 system clocks."]
347    #[inline(always)]
348    pub fn osc_failsafe_lmt_1m(self) -> &'a mut crate::W<REG> {
349        self.variant(OscFailsafeLmt::OscFailsafeLmt1m)
350    }
351    #[doc = "N is 2^22 system clocks (full range of the counter being used)."]
352    #[inline(always)]
353    pub fn osc_failsafe_lmt_4m(self) -> &'a mut crate::W<REG> {
354        self.variant(OscFailsafeLmt::OscFailsafeLmt4m)
355    }
356}
357#[doc = "Oscillator fail safe test.\n\nValue on reset: 0"]
358#[cfg_attr(feature = "defmt", derive(defmt::Format))]
359#[derive(Clone, Copy, Debug, PartialEq, Eq)]
360pub enum OscFailsafeTest {
361    #[doc = "0: No impact."]
362    Disable = 0,
363    #[doc = "1: Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."]
364    Enable = 1,
365}
366impl From<OscFailsafeTest> for bool {
367    #[inline(always)]
368    fn from(variant: OscFailsafeTest) -> Self {
369        variant as u8 != 0
370    }
371}
372#[doc = "Field `OSC_FAILSAFE_TEST` reader - Oscillator fail safe test."]
373pub type OscFailsafeTestR = crate::BitReader<OscFailsafeTest>;
374impl OscFailsafeTestR {
375    #[doc = "Get enumerated values variant"]
376    #[inline(always)]
377    pub const fn variant(&self) -> OscFailsafeTest {
378        match self.bits {
379            false => OscFailsafeTest::Disable,
380            true => OscFailsafeTest::Enable,
381        }
382    }
383    #[doc = "No impact."]
384    #[inline(always)]
385    pub fn is_disable(&self) -> bool {
386        *self == OscFailsafeTest::Disable
387    }
388    #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."]
389    #[inline(always)]
390    pub fn is_enable(&self) -> bool {
391        *self == OscFailsafeTest::Enable
392    }
393}
394#[doc = "Field `OSC_FAILSAFE_TEST` writer - Oscillator fail safe test."]
395pub type OscFailsafeTestW<'a, REG> = crate::BitWriter<'a, REG, OscFailsafeTest>;
396impl<'a, REG> OscFailsafeTestW<'a, REG>
397where
398    REG: crate::Writable + crate::RegisterSpec,
399{
400    #[doc = "No impact."]
401    #[inline(always)]
402    pub fn disable(self) -> &'a mut crate::W<REG> {
403        self.variant(OscFailsafeTest::Disable)
404    }
405    #[doc = "Disables oscillator 2 while in dual-oscillator mode (TRNG_ENT_CTL = 01b)."]
406    #[inline(always)]
407    pub fn enable(self) -> &'a mut crate::W<REG> {
408        self.variant(OscFailsafeTest::Enable)
409    }
410}
411impl R {
412    #[doc = "Bits 0:1 - TRNG entropy generation control."]
413    #[inline(always)]
414    pub fn trng_ent_ctl(&self) -> TrngEntCtlR {
415        TrngEntCtlR::new((self.bits & 3) as u8)
416    }
417    #[doc = "Bits 2:3 - Oscillator 2 Divide."]
418    #[inline(always)]
419    pub fn osc2_div(&self) -> Osc2DivR {
420        Osc2DivR::new(((self.bits >> 2) & 3) as u8)
421    }
422    #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"]
423    #[inline(always)]
424    pub fn osc2_out_en(&self) -> Osc2OutEnR {
425        Osc2OutEnR::new(((self.bits >> 4) & 1) != 0)
426    }
427    #[doc = "Bit 9 - TRNG Oscillator 2 Frequency Count Valid"]
428    #[inline(always)]
429    pub fn osc2_fct_val(&self) -> Osc2FctValR {
430        Osc2FctValR::new(((self.bits >> 9) & 1) != 0)
431    }
432    #[doc = "Bits 12:13 - Oscillator fail safe limit."]
433    #[inline(always)]
434    pub fn osc_failsafe_lmt(&self) -> OscFailsafeLmtR {
435        OscFailsafeLmtR::new(((self.bits >> 12) & 3) as u8)
436    }
437    #[doc = "Bit 14 - Oscillator fail safe test."]
438    #[inline(always)]
439    pub fn osc_failsafe_test(&self) -> OscFailsafeTestR {
440        OscFailsafeTestR::new(((self.bits >> 14) & 1) != 0)
441    }
442}
443#[cfg(feature = "debug")]
444impl core::fmt::Debug for R {
445    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
446        f.debug_struct("OSC2_CTL")
447            .field("trng_ent_ctl", &self.trng_ent_ctl())
448            .field("osc2_div", &self.osc2_div())
449            .field("osc2_out_en", &self.osc2_out_en())
450            .field("osc2_fct_val", &self.osc2_fct_val())
451            .field("osc_failsafe_lmt", &self.osc_failsafe_lmt())
452            .field("osc_failsafe_test", &self.osc_failsafe_test())
453            .finish()
454    }
455}
456impl W {
457    #[doc = "Bits 0:1 - TRNG entropy generation control."]
458    #[inline(always)]
459    pub fn trng_ent_ctl(&mut self) -> TrngEntCtlW<'_, Osc2CtlSpec> {
460        TrngEntCtlW::new(self, 0)
461    }
462    #[doc = "Bits 2:3 - Oscillator 2 Divide."]
463    #[inline(always)]
464    pub fn osc2_div(&mut self) -> Osc2DivW<'_, Osc2CtlSpec> {
465        Osc2DivW::new(self, 2)
466    }
467    #[doc = "Bit 4 - Oscillator 2 Clock Output Enable"]
468    #[inline(always)]
469    pub fn osc2_out_en(&mut self) -> Osc2OutEnW<'_, Osc2CtlSpec> {
470        Osc2OutEnW::new(self, 4)
471    }
472    #[doc = "Bits 12:13 - Oscillator fail safe limit."]
473    #[inline(always)]
474    pub fn osc_failsafe_lmt(&mut self) -> OscFailsafeLmtW<'_, Osc2CtlSpec> {
475        OscFailsafeLmtW::new(self, 12)
476    }
477    #[doc = "Bit 14 - Oscillator fail safe test."]
478    #[inline(always)]
479    pub fn osc_failsafe_test(&mut self) -> OscFailsafeTestW<'_, Osc2CtlSpec> {
480        OscFailsafeTestW::new(self, 14)
481    }
482}
483#[doc = "TRNG Oscillator 2 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`osc2_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osc2_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
484pub struct Osc2CtlSpec;
485impl crate::RegisterSpec for Osc2CtlSpec {
486    type Ux = u32;
487}
488#[doc = "`read()` method returns [`osc2_ctl::R`](R) reader structure"]
489impl crate::Readable for Osc2CtlSpec {}
490#[doc = "`write(|w| ..)` method takes [`osc2_ctl::W`](W) writer structure"]
491impl crate::Writable for Osc2CtlSpec {
492    type Safety = crate::Unsafe;
493}
494#[doc = "`reset()` method sets OSC2_CTL to value 0x1000"]
495impl crate::Resettable for Osc2CtlSpec {
496    const RESET_VALUE: u32 = 0x1000;
497}
mcxa_pac/trng0/osc2_ctl.rs

mcxa_pac/trng0/
osc2_ctl.rs
