mcxa_pac/trng0/
int_mask.rs

1#[doc = "Register `INT_MASK` reader"]
2pub type R = crate::R<IntMaskSpec>;
3#[doc = "Register `INT_MASK` writer"]
4pub type W = crate::W<IntMaskSpec>;
5#[doc = "Mask the HW_ERR interrupt.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum HwErr {
9    #[doc = "0: HW_ERR interrupt is disabled."]
10    HwErrMasked = 0,
11    #[doc = "1: HW_ERR interrupt is enabled."]
12    HwErrActive = 1,
13}
14impl From<HwErr> for bool {
15    #[inline(always)]
16    fn from(variant: HwErr) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `HW_ERR` reader - Mask the HW_ERR interrupt."]
21pub type HwErrR = crate::BitReader<HwErr>;
22impl HwErrR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> HwErr {
26        match self.bits {
27            false => HwErr::HwErrMasked,
28            true => HwErr::HwErrActive,
29        }
30    }
31    #[doc = "HW_ERR interrupt is disabled."]
32    #[inline(always)]
33    pub fn is_hw_err_masked(&self) -> bool {
34        *self == HwErr::HwErrMasked
35    }
36    #[doc = "HW_ERR interrupt is enabled."]
37    #[inline(always)]
38    pub fn is_hw_err_active(&self) -> bool {
39        *self == HwErr::HwErrActive
40    }
41}
42#[doc = "Field `HW_ERR` writer - Mask the HW_ERR interrupt."]
43pub type HwErrW<'a, REG> = crate::BitWriter<'a, REG, HwErr>;
44impl<'a, REG> HwErrW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "HW_ERR interrupt is disabled."]
49    #[inline(always)]
50    pub fn hw_err_masked(self) -> &'a mut crate::W<REG> {
51        self.variant(HwErr::HwErrMasked)
52    }
53    #[doc = "HW_ERR interrupt is enabled."]
54    #[inline(always)]
55    pub fn hw_err_active(self) -> &'a mut crate::W<REG> {
56        self.variant(HwErr::HwErrActive)
57    }
58}
59#[doc = "Mask the ENT_VAL interrupt.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum EntVal {
63    #[doc = "0: ENT_VAL interrupt is disabled."]
64    EntValMasked = 0,
65    #[doc = "1: ENT_VAL interrupt is enabled."]
66    EntValActive = 1,
67}
68impl From<EntVal> for bool {
69    #[inline(always)]
70    fn from(variant: EntVal) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ENT_VAL` reader - Mask the ENT_VAL interrupt."]
75pub type EntValR = crate::BitReader<EntVal>;
76impl EntValR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> EntVal {
80        match self.bits {
81            false => EntVal::EntValMasked,
82            true => EntVal::EntValActive,
83        }
84    }
85    #[doc = "ENT_VAL interrupt is disabled."]
86    #[inline(always)]
87    pub fn is_ent_val_masked(&self) -> bool {
88        *self == EntVal::EntValMasked
89    }
90    #[doc = "ENT_VAL interrupt is enabled."]
91    #[inline(always)]
92    pub fn is_ent_val_active(&self) -> bool {
93        *self == EntVal::EntValActive
94    }
95}
96#[doc = "Field `ENT_VAL` writer - Mask the ENT_VAL interrupt."]
97pub type EntValW<'a, REG> = crate::BitWriter<'a, REG, EntVal>;
98impl<'a, REG> EntValW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "ENT_VAL interrupt is disabled."]
103    #[inline(always)]
104    pub fn ent_val_masked(self) -> &'a mut crate::W<REG> {
105        self.variant(EntVal::EntValMasked)
106    }
107    #[doc = "ENT_VAL interrupt is enabled."]
108    #[inline(always)]
109    pub fn ent_val_active(self) -> &'a mut crate::W<REG> {
110        self.variant(EntVal::EntValActive)
111    }
112}
113#[doc = "Mask the FRQ_CT_FAIL interrupt.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum FrqCtFail {
117    #[doc = "0: FRQ_CT_FAIL interrupt is disabled."]
118    FrqCtFailMasked = 0,
119    #[doc = "1: FRQ_CT_FAIL interrupt is enabled."]
120    FrqCtFailActive = 1,
121}
122impl From<FrqCtFail> for bool {
123    #[inline(always)]
124    fn from(variant: FrqCtFail) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `FRQ_CT_FAIL` reader - Mask the FRQ_CT_FAIL interrupt."]
129pub type FrqCtFailR = crate::BitReader<FrqCtFail>;
130impl FrqCtFailR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> FrqCtFail {
134        match self.bits {
135            false => FrqCtFail::FrqCtFailMasked,
136            true => FrqCtFail::FrqCtFailActive,
137        }
138    }
139    #[doc = "FRQ_CT_FAIL interrupt is disabled."]
140    #[inline(always)]
141    pub fn is_frq_ct_fail_masked(&self) -> bool {
142        *self == FrqCtFail::FrqCtFailMasked
143    }
144    #[doc = "FRQ_CT_FAIL interrupt is enabled."]
145    #[inline(always)]
146    pub fn is_frq_ct_fail_active(&self) -> bool {
147        *self == FrqCtFail::FrqCtFailActive
148    }
149}
150#[doc = "Field `FRQ_CT_FAIL` writer - Mask the FRQ_CT_FAIL interrupt."]
151pub type FrqCtFailW<'a, REG> = crate::BitWriter<'a, REG, FrqCtFail>;
152impl<'a, REG> FrqCtFailW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "FRQ_CT_FAIL interrupt is disabled."]
157    #[inline(always)]
158    pub fn frq_ct_fail_masked(self) -> &'a mut crate::W<REG> {
159        self.variant(FrqCtFail::FrqCtFailMasked)
160    }
161    #[doc = "FRQ_CT_FAIL interrupt is enabled."]
162    #[inline(always)]
163    pub fn frq_ct_fail_active(self) -> &'a mut crate::W<REG> {
164        self.variant(FrqCtFail::FrqCtFailActive)
165    }
166}
167#[doc = "Mask the INTG_FLT interrupt.\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum IntgFlt {
171    #[doc = "0: INTG_FLT interrupt is disabled."]
172    IntgFltMasked = 0,
173    #[doc = "1: INTG_FLT interrupt is enabled."]
174    IntgFltActive = 1,
175}
176impl From<IntgFlt> for bool {
177    #[inline(always)]
178    fn from(variant: IntgFlt) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `INTG_FLT` reader - Mask the INTG_FLT interrupt."]
183pub type IntgFltR = crate::BitReader<IntgFlt>;
184impl IntgFltR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> IntgFlt {
188        match self.bits {
189            false => IntgFlt::IntgFltMasked,
190            true => IntgFlt::IntgFltActive,
191        }
192    }
193    #[doc = "INTG_FLT interrupt is disabled."]
194    #[inline(always)]
195    pub fn is_intg_flt_masked(&self) -> bool {
196        *self == IntgFlt::IntgFltMasked
197    }
198    #[doc = "INTG_FLT interrupt is enabled."]
199    #[inline(always)]
200    pub fn is_intg_flt_active(&self) -> bool {
201        *self == IntgFlt::IntgFltActive
202    }
203}
204#[doc = "Field `INTG_FLT` writer - Mask the INTG_FLT interrupt."]
205pub type IntgFltW<'a, REG> = crate::BitWriter<'a, REG, IntgFlt>;
206impl<'a, REG> IntgFltW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "INTG_FLT interrupt is disabled."]
211    #[inline(always)]
212    pub fn intg_flt_masked(self) -> &'a mut crate::W<REG> {
213        self.variant(IntgFlt::IntgFltMasked)
214    }
215    #[doc = "INTG_FLT interrupt is enabled."]
216    #[inline(always)]
217    pub fn intg_flt_active(self) -> &'a mut crate::W<REG> {
218        self.variant(IntgFlt::IntgFltActive)
219    }
220}
221impl R {
222    #[doc = "Bit 0 - Mask the HW_ERR interrupt."]
223    #[inline(always)]
224    pub fn hw_err(&self) -> HwErrR {
225        HwErrR::new((self.bits & 1) != 0)
226    }
227    #[doc = "Bit 1 - Mask the ENT_VAL interrupt."]
228    #[inline(always)]
229    pub fn ent_val(&self) -> EntValR {
230        EntValR::new(((self.bits >> 1) & 1) != 0)
231    }
232    #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."]
233    #[inline(always)]
234    pub fn frq_ct_fail(&self) -> FrqCtFailR {
235        FrqCtFailR::new(((self.bits >> 2) & 1) != 0)
236    }
237    #[doc = "Bit 3 - Mask the INTG_FLT interrupt."]
238    #[inline(always)]
239    pub fn intg_flt(&self) -> IntgFltR {
240        IntgFltR::new(((self.bits >> 3) & 1) != 0)
241    }
242}
243#[cfg(feature = "debug")]
244impl core::fmt::Debug for R {
245    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
246        f.debug_struct("INT_MASK")
247            .field("hw_err", &self.hw_err())
248            .field("ent_val", &self.ent_val())
249            .field("frq_ct_fail", &self.frq_ct_fail())
250            .field("intg_flt", &self.intg_flt())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bit 0 - Mask the HW_ERR interrupt."]
256    #[inline(always)]
257    pub fn hw_err(&mut self) -> HwErrW<'_, IntMaskSpec> {
258        HwErrW::new(self, 0)
259    }
260    #[doc = "Bit 1 - Mask the ENT_VAL interrupt."]
261    #[inline(always)]
262    pub fn ent_val(&mut self) -> EntValW<'_, IntMaskSpec> {
263        EntValW::new(self, 1)
264    }
265    #[doc = "Bit 2 - Mask the FRQ_CT_FAIL interrupt."]
266    #[inline(always)]
267    pub fn frq_ct_fail(&mut self) -> FrqCtFailW<'_, IntMaskSpec> {
268        FrqCtFailW::new(self, 2)
269    }
270    #[doc = "Bit 3 - Mask the INTG_FLT interrupt."]
271    #[inline(always)]
272    pub fn intg_flt(&mut self) -> IntgFltW<'_, IntMaskSpec> {
273        IntgFltW::new(self, 3)
274    }
275}
276#[doc = "Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct IntMaskSpec;
278impl crate::RegisterSpec for IntMaskSpec {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`int_mask::R`](R) reader structure"]
282impl crate::Readable for IntMaskSpec {}
283#[doc = "`write(|w| ..)` method takes [`int_mask::W`](W) writer structure"]
284impl crate::Writable for IntMaskSpec {
285    type Safety = crate::Unsafe;
286}
287#[doc = "`reset()` method sets INT_MASK to value 0"]
288impl crate::Resettable for IntMaskSpec {}
mcxa_pac/trng0/int_mask.rs

mcxa_pac/trng0/
int_mask.rs
