mcxa_pac/syscon/
sram_xen.rs

1#[doc = "Register `SRAM_XEN` reader"]
2pub type R = crate::R<SramXenSpec>;
3#[doc = "Register `SRAM_XEN` writer"]
4pub type W = crate::W<SramXenSpec>;
5#[doc = "RAMX0 Execute permission control.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Ramx0Xen {
9    #[doc = "0: Execute permission is disabled, R/W are enabled."]
10    Disable = 0,
11    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
12    Enable = 1,
13}
14impl From<Ramx0Xen> for bool {
15    #[inline(always)]
16    fn from(variant: Ramx0Xen) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `RAMX0_XEN` reader - RAMX0 Execute permission control."]
21pub type Ramx0XenR = crate::BitReader<Ramx0Xen>;
22impl Ramx0XenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Ramx0Xen {
26        match self.bits {
27            false => Ramx0Xen::Disable,
28            true => Ramx0Xen::Enable,
29        }
30    }
31    #[doc = "Execute permission is disabled, R/W are enabled."]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Ramx0Xen::Disable
35    }
36    #[doc = "Execute permission is enabled, R/W/X are enabled."]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Ramx0Xen::Enable
40    }
41}
42#[doc = "Field `RAMX0_XEN` writer - RAMX0 Execute permission control."]
43pub type Ramx0XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx0Xen>;
44impl<'a, REG> Ramx0XenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Execute permission is disabled, R/W are enabled."]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Ramx0Xen::Disable)
52    }
53    #[doc = "Execute permission is enabled, R/W/X are enabled."]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Ramx0Xen::Enable)
57    }
58}
59#[doc = "RAMX1 Execute permission control.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Ramx1Xen {
63    #[doc = "0: Execute permission is disabled, R/W are enabled."]
64    Disable = 0,
65    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
66    Enable = 1,
67}
68impl From<Ramx1Xen> for bool {
69    #[inline(always)]
70    fn from(variant: Ramx1Xen) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `RAMX1_XEN` reader - RAMX1 Execute permission control."]
75pub type Ramx1XenR = crate::BitReader<Ramx1Xen>;
76impl Ramx1XenR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Ramx1Xen {
80        match self.bits {
81            false => Ramx1Xen::Disable,
82            true => Ramx1Xen::Enable,
83        }
84    }
85    #[doc = "Execute permission is disabled, R/W are enabled."]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Ramx1Xen::Disable
89    }
90    #[doc = "Execute permission is enabled, R/W/X are enabled."]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Ramx1Xen::Enable
94    }
95}
96#[doc = "Field `RAMX1_XEN` writer - RAMX1 Execute permission control."]
97pub type Ramx1XenW<'a, REG> = crate::BitWriter<'a, REG, Ramx1Xen>;
98impl<'a, REG> Ramx1XenW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Execute permission is disabled, R/W are enabled."]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Ramx1Xen::Disable)
106    }
107    #[doc = "Execute permission is enabled, R/W/X are enabled."]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Ramx1Xen::Enable)
111    }
112}
113#[doc = "RAMA0 Execute permission control.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Rama0Xen {
117    #[doc = "0: Execute permission is disabled, R/W are enabled."]
118    Disable = 0,
119    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
120    Enable = 1,
121}
122impl From<Rama0Xen> for bool {
123    #[inline(always)]
124    fn from(variant: Rama0Xen) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `RAMA0_XEN` reader - RAMA0 Execute permission control."]
129pub type Rama0XenR = crate::BitReader<Rama0Xen>;
130impl Rama0XenR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Rama0Xen {
134        match self.bits {
135            false => Rama0Xen::Disable,
136            true => Rama0Xen::Enable,
137        }
138    }
139    #[doc = "Execute permission is disabled, R/W are enabled."]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Rama0Xen::Disable
143    }
144    #[doc = "Execute permission is enabled, R/W/X are enabled."]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Rama0Xen::Enable
148    }
149}
150#[doc = "Field `RAMA0_XEN` writer - RAMA0 Execute permission control."]
151pub type Rama0XenW<'a, REG> = crate::BitWriter<'a, REG, Rama0Xen>;
152impl<'a, REG> Rama0XenW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Execute permission is disabled, R/W are enabled."]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Rama0Xen::Disable)
160    }
161    #[doc = "Execute permission is enabled, R/W/X are enabled."]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Rama0Xen::Enable)
165    }
166}
167#[doc = "RAMAx (excepts RAMA0) Execute permission control.\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Rama1Xen {
171    #[doc = "0: Execute permission is disabled, R/W are enabled."]
172    Disable = 0,
173    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
174    Enable = 1,
175}
176impl From<Rama1Xen> for bool {
177    #[inline(always)]
178    fn from(variant: Rama1Xen) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `RAMA1_XEN` reader - RAMAx (excepts RAMA0) Execute permission control."]
183pub type Rama1XenR = crate::BitReader<Rama1Xen>;
184impl Rama1XenR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Rama1Xen {
188        match self.bits {
189            false => Rama1Xen::Disable,
190            true => Rama1Xen::Enable,
191        }
192    }
193    #[doc = "Execute permission is disabled, R/W are enabled."]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Rama1Xen::Disable
197    }
198    #[doc = "Execute permission is enabled, R/W/X are enabled."]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Rama1Xen::Enable
202    }
203}
204#[doc = "Field `RAMA1_XEN` writer - RAMAx (excepts RAMA0) Execute permission control."]
205pub type Rama1XenW<'a, REG> = crate::BitWriter<'a, REG, Rama1Xen>;
206impl<'a, REG> Rama1XenW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Execute permission is disabled, R/W are enabled."]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Rama1Xen::Disable)
214    }
215    #[doc = "Execute permission is enabled, R/W/X are enabled."]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Rama1Xen::Enable)
219    }
220}
221#[doc = "RAMBx Execute permission control.\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum RambXen {
225    #[doc = "0: Execute permission is disabled, R/W are enabled."]
226    Disable = 0,
227    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
228    Enable = 1,
229}
230impl From<RambXen> for bool {
231    #[inline(always)]
232    fn from(variant: RambXen) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `RAMB_XEN` reader - RAMBx Execute permission control."]
237pub type RambXenR = crate::BitReader<RambXen>;
238impl RambXenR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> RambXen {
242        match self.bits {
243            false => RambXen::Disable,
244            true => RambXen::Enable,
245        }
246    }
247    #[doc = "Execute permission is disabled, R/W are enabled."]
248    #[inline(always)]
249    pub fn is_disable(&self) -> bool {
250        *self == RambXen::Disable
251    }
252    #[doc = "Execute permission is enabled, R/W/X are enabled."]
253    #[inline(always)]
254    pub fn is_enable(&self) -> bool {
255        *self == RambXen::Enable
256    }
257}
258#[doc = "Field `RAMB_XEN` writer - RAMBx Execute permission control."]
259pub type RambXenW<'a, REG> = crate::BitWriter<'a, REG, RambXen>;
260impl<'a, REG> RambXenW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Execute permission is disabled, R/W are enabled."]
265    #[inline(always)]
266    pub fn disable(self) -> &'a mut crate::W<REG> {
267        self.variant(RambXen::Disable)
268    }
269    #[doc = "Execute permission is enabled, R/W/X are enabled."]
270    #[inline(always)]
271    pub fn enable(self) -> &'a mut crate::W<REG> {
272        self.variant(RambXen::Enable)
273    }
274}
275#[doc = "RAMCx Execute permission control.\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum RamcXen {
279    #[doc = "0: Execute permission is disabled, R/W are enabled."]
280    Disable = 0,
281    #[doc = "1: Execute permission is enabled, R/W/X are enabled."]
282    Enable = 1,
283}
284impl From<RamcXen> for bool {
285    #[inline(always)]
286    fn from(variant: RamcXen) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `RAMC_XEN` reader - RAMCx Execute permission control."]
291pub type RamcXenR = crate::BitReader<RamcXen>;
292impl RamcXenR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> RamcXen {
296        match self.bits {
297            false => RamcXen::Disable,
298            true => RamcXen::Enable,
299        }
300    }
301    #[doc = "Execute permission is disabled, R/W are enabled."]
302    #[inline(always)]
303    pub fn is_disable(&self) -> bool {
304        *self == RamcXen::Disable
305    }
306    #[doc = "Execute permission is enabled, R/W/X are enabled."]
307    #[inline(always)]
308    pub fn is_enable(&self) -> bool {
309        *self == RamcXen::Enable
310    }
311}
312#[doc = "Field `RAMC_XEN` writer - RAMCx Execute permission control."]
313pub type RamcXenW<'a, REG> = crate::BitWriter<'a, REG, RamcXen>;
314impl<'a, REG> RamcXenW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Execute permission is disabled, R/W are enabled."]
319    #[inline(always)]
320    pub fn disable(self) -> &'a mut crate::W<REG> {
321        self.variant(RamcXen::Disable)
322    }
323    #[doc = "Execute permission is enabled, R/W/X are enabled."]
324    #[inline(always)]
325    pub fn enable(self) -> &'a mut crate::W<REG> {
326        self.variant(RamcXen::Enable)
327    }
328}
329#[doc = "This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Lock {
333    #[doc = "0: This register is not locked and can be altered."]
334    Lock0 = 0,
335    #[doc = "1: This register is locked and cannot be altered."]
336    Lock1 = 1,
337}
338impl From<Lock> for bool {
339    #[inline(always)]
340    fn from(variant: Lock) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."]
345pub type LockR = crate::BitReader<Lock>;
346impl LockR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Lock {
350        match self.bits {
351            false => Lock::Lock0,
352            true => Lock::Lock1,
353        }
354    }
355    #[doc = "This register is not locked and can be altered."]
356    #[inline(always)]
357    pub fn is_lock_0(&self) -> bool {
358        *self == Lock::Lock0
359    }
360    #[doc = "This register is locked and cannot be altered."]
361    #[inline(always)]
362    pub fn is_lock_1(&self) -> bool {
363        *self == Lock::Lock1
364    }
365}
366#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."]
367pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>;
368impl<'a, REG> LockW<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "This register is not locked and can be altered."]
373    #[inline(always)]
374    pub fn lock_0(self) -> &'a mut crate::W<REG> {
375        self.variant(Lock::Lock0)
376    }
377    #[doc = "This register is locked and cannot be altered."]
378    #[inline(always)]
379    pub fn lock_1(self) -> &'a mut crate::W<REG> {
380        self.variant(Lock::Lock1)
381    }
382}
383impl R {
384    #[doc = "Bit 0 - RAMX0 Execute permission control."]
385    #[inline(always)]
386    pub fn ramx0_xen(&self) -> Ramx0XenR {
387        Ramx0XenR::new((self.bits & 1) != 0)
388    }
389    #[doc = "Bit 1 - RAMX1 Execute permission control."]
390    #[inline(always)]
391    pub fn ramx1_xen(&self) -> Ramx1XenR {
392        Ramx1XenR::new(((self.bits >> 1) & 1) != 0)
393    }
394    #[doc = "Bit 2 - RAMA0 Execute permission control."]
395    #[inline(always)]
396    pub fn rama0_xen(&self) -> Rama0XenR {
397        Rama0XenR::new(((self.bits >> 2) & 1) != 0)
398    }
399    #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."]
400    #[inline(always)]
401    pub fn rama1_xen(&self) -> Rama1XenR {
402        Rama1XenR::new(((self.bits >> 3) & 1) != 0)
403    }
404    #[doc = "Bit 4 - RAMBx Execute permission control."]
405    #[inline(always)]
406    pub fn ramb_xen(&self) -> RambXenR {
407        RambXenR::new(((self.bits >> 4) & 1) != 0)
408    }
409    #[doc = "Bit 5 - RAMCx Execute permission control."]
410    #[inline(always)]
411    pub fn ramc_xen(&self) -> RamcXenR {
412        RamcXenR::new(((self.bits >> 5) & 1) != 0)
413    }
414    #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."]
415    #[inline(always)]
416    pub fn lock(&self) -> LockR {
417        LockR::new(((self.bits >> 31) & 1) != 0)
418    }
419}
420#[cfg(feature = "debug")]
421impl core::fmt::Debug for R {
422    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
423        f.debug_struct("SRAM_XEN")
424            .field("ramx0_xen", &self.ramx0_xen())
425            .field("ramx1_xen", &self.ramx1_xen())
426            .field("rama0_xen", &self.rama0_xen())
427            .field("rama1_xen", &self.rama1_xen())
428            .field("ramb_xen", &self.ramb_xen())
429            .field("ramc_xen", &self.ramc_xen())
430            .field("lock", &self.lock())
431            .finish()
432    }
433}
434impl W {
435    #[doc = "Bit 0 - RAMX0 Execute permission control."]
436    #[inline(always)]
437    pub fn ramx0_xen(&mut self) -> Ramx0XenW<'_, SramXenSpec> {
438        Ramx0XenW::new(self, 0)
439    }
440    #[doc = "Bit 1 - RAMX1 Execute permission control."]
441    #[inline(always)]
442    pub fn ramx1_xen(&mut self) -> Ramx1XenW<'_, SramXenSpec> {
443        Ramx1XenW::new(self, 1)
444    }
445    #[doc = "Bit 2 - RAMA0 Execute permission control."]
446    #[inline(always)]
447    pub fn rama0_xen(&mut self) -> Rama0XenW<'_, SramXenSpec> {
448        Rama0XenW::new(self, 2)
449    }
450    #[doc = "Bit 3 - RAMAx (excepts RAMA0) Execute permission control."]
451    #[inline(always)]
452    pub fn rama1_xen(&mut self) -> Rama1XenW<'_, SramXenSpec> {
453        Rama1XenW::new(self, 3)
454    }
455    #[doc = "Bit 4 - RAMBx Execute permission control."]
456    #[inline(always)]
457    pub fn ramb_xen(&mut self) -> RambXenW<'_, SramXenSpec> {
458        RambXenW::new(self, 4)
459    }
460    #[doc = "Bit 5 - RAMCx Execute permission control."]
461    #[inline(always)]
462    pub fn ramc_xen(&mut self) -> RamcXenW<'_, SramXenSpec> {
463        RamcXenW::new(self, 5)
464    }
465    #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset."]
466    #[inline(always)]
467    pub fn lock(&mut self) -> LockW<'_, SramXenSpec> {
468        LockW::new(self, 31)
469    }
470}
471#[doc = "RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
472pub struct SramXenSpec;
473impl crate::RegisterSpec for SramXenSpec {
474    type Ux = u32;
475}
476#[doc = "`read()` method returns [`sram_xen::R`](R) reader structure"]
477impl crate::Readable for SramXenSpec {}
478#[doc = "`write(|w| ..)` method takes [`sram_xen::W`](W) writer structure"]
479impl crate::Writable for SramXenSpec {
480    type Safety = crate::Unsafe;
481}
482#[doc = "`reset()` method sets SRAM_XEN to value 0"]
483impl crate::Resettable for SramXenSpec {}
mcxa_pac/syscon/sram_xen.rs

mcxa_pac/syscon/
sram_xen.rs
