1#[doc = "Register `PROTLVL` reader"]
2pub type R = crate::R<ProtlvlSpec>;
3#[doc = "Register `PROTLVL` writer"]
4pub type W = crate::W<ProtlvlSpec>;
5#[doc = "Control privileged access of EIM, ERM, Flexcan, MBC, SCG.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Priv {
9 #[doc = "0: privileged access is disabled. the peripherals could be access in user mode."]
10 Disable = 0,
11 #[doc = "1: privileged access is enabled. the peripherals could be access in privilege mode."]
12 Enable = 1,
13}
14impl From<Priv> for bool {
15 #[inline(always)]
16 fn from(variant: Priv) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `PRIV` reader - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."]
21pub type PrivR = crate::BitReader<Priv>;
22impl PrivR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Priv {
26 match self.bits {
27 false => Priv::Disable,
28 true => Priv::Enable,
29 }
30 }
31 #[doc = "privileged access is disabled. the peripherals could be access in user mode."]
32 #[inline(always)]
33 pub fn is_disable(&self) -> bool {
34 *self == Priv::Disable
35 }
36 #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."]
37 #[inline(always)]
38 pub fn is_enable(&self) -> bool {
39 *self == Priv::Enable
40 }
41}
42#[doc = "Field `PRIV` writer - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."]
43pub type PrivW<'a, REG> = crate::BitWriter<'a, REG, Priv>;
44impl<'a, REG> PrivW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "privileged access is disabled. the peripherals could be access in user mode."]
49 #[inline(always)]
50 pub fn disable(self) -> &'a mut crate::W<REG> {
51 self.variant(Priv::Disable)
52 }
53 #[doc = "privileged access is enabled. the peripherals could be access in privilege mode."]
54 #[inline(always)]
55 pub fn enable(self) -> &'a mut crate::W<REG> {
56 self.variant(Priv::Enable)
57 }
58}
59#[doc = "Control write access to Nonsecure MPU memory regions.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Locknsmpu {
63 #[doc = "0: Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."]
64 Enable = 0,
65 #[doc = "1: Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."]
66 Disable = 1,
67}
68impl From<Locknsmpu> for bool {
69 #[inline(always)]
70 fn from(variant: Locknsmpu) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `LOCKNSMPU` reader - Control write access to Nonsecure MPU memory regions."]
75pub type LocknsmpuR = crate::BitReader<Locknsmpu>;
76impl LocknsmpuR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Locknsmpu {
80 match self.bits {
81 false => Locknsmpu::Enable,
82 true => Locknsmpu::Disable,
83 }
84 }
85 #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."]
86 #[inline(always)]
87 pub fn is_enable(&self) -> bool {
88 *self == Locknsmpu::Enable
89 }
90 #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."]
91 #[inline(always)]
92 pub fn is_disable(&self) -> bool {
93 *self == Locknsmpu::Disable
94 }
95}
96#[doc = "Field `LOCKNSMPU` writer - Control write access to Nonsecure MPU memory regions."]
97pub type LocknsmpuW<'a, REG> = crate::BitWriter<'a, REG, Locknsmpu>;
98impl<'a, REG> LocknsmpuW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Unlock these registers. privileged access to Nonsecure MPU memory regions is allowed."]
103 #[inline(always)]
104 pub fn enable(self) -> &'a mut crate::W<REG> {
105 self.variant(Locknsmpu::Enable)
106 }
107 #[doc = "Disable writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn. All writes to the registers are ignored."]
108 #[inline(always)]
109 pub fn disable(self) -> &'a mut crate::W<REG> {
110 self.variant(Locknsmpu::Disable)
111 }
112}
113#[doc = "This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Lock {
117 #[doc = "0: This register is not locked and can be altered."]
118 Lock0 = 0,
119 #[doc = "1: This register is locked and cannot be altered until a system reset."]
120 Lock1 = 1,
121}
122impl From<Lock> for bool {
123 #[inline(always)]
124 fn from(variant: Lock) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `LOCK` reader - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
129pub type LockR = crate::BitReader<Lock>;
130impl LockR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Lock {
134 match self.bits {
135 false => Lock::Lock0,
136 true => Lock::Lock1,
137 }
138 }
139 #[doc = "This register is not locked and can be altered."]
140 #[inline(always)]
141 pub fn is_lock_0(&self) -> bool {
142 *self == Lock::Lock0
143 }
144 #[doc = "This register is locked and cannot be altered until a system reset."]
145 #[inline(always)]
146 pub fn is_lock_1(&self) -> bool {
147 *self == Lock::Lock1
148 }
149}
150#[doc = "Field `LOCK` writer - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
151pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>;
152impl<'a, REG> LockW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "This register is not locked and can be altered."]
157 #[inline(always)]
158 pub fn lock_0(self) -> &'a mut crate::W<REG> {
159 self.variant(Lock::Lock0)
160 }
161 #[doc = "This register is locked and cannot be altered until a system reset."]
162 #[inline(always)]
163 pub fn lock_1(self) -> &'a mut crate::W<REG> {
164 self.variant(Lock::Lock1)
165 }
166}
167impl R {
168 #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."]
169 #[inline(always)]
170 pub fn priv_(&self) -> PrivR {
171 PrivR::new((self.bits & 1) != 0)
172 }
173 #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."]
174 #[inline(always)]
175 pub fn locknsmpu(&self) -> LocknsmpuR {
176 LocknsmpuR::new(((self.bits >> 16) & 1) != 0)
177 }
178 #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
179 #[inline(always)]
180 pub fn lock(&self) -> LockR {
181 LockR::new(((self.bits >> 31) & 1) != 0)
182 }
183}
184#[cfg(feature = "debug")]
185impl core::fmt::Debug for R {
186 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187 f.debug_struct("PROTLVL")
188 .field("priv_", &self.priv_())
189 .field("locknsmpu", &self.locknsmpu())
190 .field("lock", &self.lock())
191 .finish()
192 }
193}
194impl W {
195 #[doc = "Bit 0 - Control privileged access of EIM, ERM, Flexcan, MBC, SCG."]
196 #[inline(always)]
197 pub fn priv_(&mut self) -> PrivW<'_, ProtlvlSpec> {
198 PrivW::new(self, 0)
199 }
200 #[doc = "Bit 16 - Control write access to Nonsecure MPU memory regions."]
201 #[inline(always)]
202 pub fn locknsmpu(&mut self) -> LocknsmpuW<'_, ProtlvlSpec> {
203 LocknsmpuW::new(self, 16)
204 }
205 #[doc = "Bit 31 - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset."]
206 #[inline(always)]
207 pub fn lock(&mut self) -> LockW<'_, ProtlvlSpec> {
208 LockW::new(self, 31)
209 }
210}
211#[doc = "Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct ProtlvlSpec;
213impl crate::RegisterSpec for ProtlvlSpec {
214 type Ux = u32;
215}
216#[doc = "`read()` method returns [`protlvl::R`](R) reader structure"]
217impl crate::Readable for ProtlvlSpec {}
218#[doc = "`write(|w| ..)` method takes [`protlvl::W`](W) writer structure"]
219impl crate::Writable for ProtlvlSpec {
220 type Safety = crate::Unsafe;
221}
222#[doc = "`reset()` method sets PROTLVL to value 0"]
223impl crate::Resettable for ProtlvlSpec {}