mcxa_pac/syscon/
lpcac_ctrl.rs

1#[doc = "Register `LPCAC_CTRL` reader"]
2pub type R = crate::R<LpcacCtrlSpec>;
3#[doc = "Register `LPCAC_CTRL` writer"]
4pub type W = crate::W<LpcacCtrlSpec>;
5#[doc = "Disables/enables the cache function.\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum DisLpcac {
9    #[doc = "0: Enabled"]
10    Enable = 0,
11    #[doc = "1: Disabled"]
12    Disable = 1,
13}
14impl From<DisLpcac> for bool {
15    #[inline(always)]
16    fn from(variant: DisLpcac) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `DIS_LPCAC` reader - Disables/enables the cache function."]
21pub type DisLpcacR = crate::BitReader<DisLpcac>;
22impl DisLpcacR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> DisLpcac {
26        match self.bits {
27            false => DisLpcac::Enable,
28            true => DisLpcac::Disable,
29        }
30    }
31    #[doc = "Enabled"]
32    #[inline(always)]
33    pub fn is_enable(&self) -> bool {
34        *self == DisLpcac::Enable
35    }
36    #[doc = "Disabled"]
37    #[inline(always)]
38    pub fn is_disable(&self) -> bool {
39        *self == DisLpcac::Disable
40    }
41}
42#[doc = "Field `DIS_LPCAC` writer - Disables/enables the cache function."]
43pub type DisLpcacW<'a, REG> = crate::BitWriter<'a, REG, DisLpcac>;
44impl<'a, REG> DisLpcacW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Enabled"]
49    #[inline(always)]
50    pub fn enable(self) -> &'a mut crate::W<REG> {
51        self.variant(DisLpcac::Enable)
52    }
53    #[doc = "Disabled"]
54    #[inline(always)]
55    pub fn disable(self) -> &'a mut crate::W<REG> {
56        self.variant(DisLpcac::Disable)
57    }
58}
59#[doc = "Clears the cache function.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ClrLpcac {
63    #[doc = "0: Unclears the cache"]
64    Enable = 0,
65    #[doc = "1: Clears the cache"]
66    Disable = 1,
67}
68impl From<ClrLpcac> for bool {
69    #[inline(always)]
70    fn from(variant: ClrLpcac) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `CLR_LPCAC` reader - Clears the cache function."]
75pub type ClrLpcacR = crate::BitReader<ClrLpcac>;
76impl ClrLpcacR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> ClrLpcac {
80        match self.bits {
81            false => ClrLpcac::Enable,
82            true => ClrLpcac::Disable,
83        }
84    }
85    #[doc = "Unclears the cache"]
86    #[inline(always)]
87    pub fn is_enable(&self) -> bool {
88        *self == ClrLpcac::Enable
89    }
90    #[doc = "Clears the cache"]
91    #[inline(always)]
92    pub fn is_disable(&self) -> bool {
93        *self == ClrLpcac::Disable
94    }
95}
96#[doc = "Field `CLR_LPCAC` writer - Clears the cache function."]
97pub type ClrLpcacW<'a, REG> = crate::BitWriter<'a, REG, ClrLpcac>;
98impl<'a, REG> ClrLpcacW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Unclears the cache"]
103    #[inline(always)]
104    pub fn enable(self) -> &'a mut crate::W<REG> {
105        self.variant(ClrLpcac::Enable)
106    }
107    #[doc = "Clears the cache"]
108    #[inline(always)]
109    pub fn disable(self) -> &'a mut crate::W<REG> {
110        self.variant(ClrLpcac::Disable)
111    }
112}
113#[doc = "Forces no allocation.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum FrcNoAlloc {
117    #[doc = "0: Forces allocation"]
118    Enable = 0,
119    #[doc = "1: Forces no allocation"]
120    Disable = 1,
121}
122impl From<FrcNoAlloc> for bool {
123    #[inline(always)]
124    fn from(variant: FrcNoAlloc) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `FRC_NO_ALLOC` reader - Forces no allocation."]
129pub type FrcNoAllocR = crate::BitReader<FrcNoAlloc>;
130impl FrcNoAllocR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> FrcNoAlloc {
134        match self.bits {
135            false => FrcNoAlloc::Enable,
136            true => FrcNoAlloc::Disable,
137        }
138    }
139    #[doc = "Forces allocation"]
140    #[inline(always)]
141    pub fn is_enable(&self) -> bool {
142        *self == FrcNoAlloc::Enable
143    }
144    #[doc = "Forces no allocation"]
145    #[inline(always)]
146    pub fn is_disable(&self) -> bool {
147        *self == FrcNoAlloc::Disable
148    }
149}
150#[doc = "Field `FRC_NO_ALLOC` writer - Forces no allocation."]
151pub type FrcNoAllocW<'a, REG> = crate::BitWriter<'a, REG, FrcNoAlloc>;
152impl<'a, REG> FrcNoAllocW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Forces allocation"]
157    #[inline(always)]
158    pub fn enable(self) -> &'a mut crate::W<REG> {
159        self.variant(FrcNoAlloc::Enable)
160    }
161    #[doc = "Forces no allocation"]
162    #[inline(always)]
163    pub fn disable(self) -> &'a mut crate::W<REG> {
164        self.variant(FrcNoAlloc::Disable)
165    }
166}
167#[doc = "Disable LPCAC Write Through Buffer.\n\nValue on reset: 1"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum DisLpcacWtbf {
171    #[doc = "0: Enables write through buffer"]
172    Disable = 0,
173    #[doc = "1: Disables write through buffer"]
174    Enable = 1,
175}
176impl From<DisLpcacWtbf> for bool {
177    #[inline(always)]
178    fn from(variant: DisLpcacWtbf) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `DIS_LPCAC_WTBF` reader - Disable LPCAC Write Through Buffer."]
183pub type DisLpcacWtbfR = crate::BitReader<DisLpcacWtbf>;
184impl DisLpcacWtbfR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> DisLpcacWtbf {
188        match self.bits {
189            false => DisLpcacWtbf::Disable,
190            true => DisLpcacWtbf::Enable,
191        }
192    }
193    #[doc = "Enables write through buffer"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == DisLpcacWtbf::Disable
197    }
198    #[doc = "Disables write through buffer"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == DisLpcacWtbf::Enable
202    }
203}
204#[doc = "Field `DIS_LPCAC_WTBF` writer - Disable LPCAC Write Through Buffer."]
205pub type DisLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, DisLpcacWtbf>;
206impl<'a, REG> DisLpcacWtbfW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Enables write through buffer"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(DisLpcacWtbf::Disable)
214    }
215    #[doc = "Disables write through buffer"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(DisLpcacWtbf::Enable)
219    }
220}
221#[doc = "Limit LPCAC Write Through Buffer.\n\nValue on reset: 1"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum LimLpcacWtbf {
225    #[doc = "0: Write buffer enabled when transaction is bufferable."]
226    Disable = 0,
227    #[doc = "1: Write buffer enabled when transaction is cacheable and bufferable"]
228    Enable = 1,
229}
230impl From<LimLpcacWtbf> for bool {
231    #[inline(always)]
232    fn from(variant: LimLpcacWtbf) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `LIM_LPCAC_WTBF` reader - Limit LPCAC Write Through Buffer."]
237pub type LimLpcacWtbfR = crate::BitReader<LimLpcacWtbf>;
238impl LimLpcacWtbfR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> LimLpcacWtbf {
242        match self.bits {
243            false => LimLpcacWtbf::Disable,
244            true => LimLpcacWtbf::Enable,
245        }
246    }
247    #[doc = "Write buffer enabled when transaction is bufferable."]
248    #[inline(always)]
249    pub fn is_disable(&self) -> bool {
250        *self == LimLpcacWtbf::Disable
251    }
252    #[doc = "Write buffer enabled when transaction is cacheable and bufferable"]
253    #[inline(always)]
254    pub fn is_enable(&self) -> bool {
255        *self == LimLpcacWtbf::Enable
256    }
257}
258#[doc = "Field `LIM_LPCAC_WTBF` writer - Limit LPCAC Write Through Buffer."]
259pub type LimLpcacWtbfW<'a, REG> = crate::BitWriter<'a, REG, LimLpcacWtbf>;
260impl<'a, REG> LimLpcacWtbfW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Write buffer enabled when transaction is bufferable."]
265    #[inline(always)]
266    pub fn disable(self) -> &'a mut crate::W<REG> {
267        self.variant(LimLpcacWtbf::Disable)
268    }
269    #[doc = "Write buffer enabled when transaction is cacheable and bufferable"]
270    #[inline(always)]
271    pub fn enable(self) -> &'a mut crate::W<REG> {
272        self.variant(LimLpcacWtbf::Enable)
273    }
274}
275#[doc = "LPCAC XOM(eXecute-Only-Memory) attribute control\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum LpcacXom {
279    #[doc = "0: Disabled."]
280    Disable = 0,
281    #[doc = "1: Enabled."]
282    Enable = 1,
283}
284impl From<LpcacXom> for bool {
285    #[inline(always)]
286    fn from(variant: LpcacXom) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `LPCAC_XOM` reader - LPCAC XOM(eXecute-Only-Memory) attribute control"]
291pub type LpcacXomR = crate::BitReader<LpcacXom>;
292impl LpcacXomR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> LpcacXom {
296        match self.bits {
297            false => LpcacXom::Disable,
298            true => LpcacXom::Enable,
299        }
300    }
301    #[doc = "Disabled."]
302    #[inline(always)]
303    pub fn is_disable(&self) -> bool {
304        *self == LpcacXom::Disable
305    }
306    #[doc = "Enabled."]
307    #[inline(always)]
308    pub fn is_enable(&self) -> bool {
309        *self == LpcacXom::Enable
310    }
311}
312#[doc = "Field `LPCAC_XOM` writer - LPCAC XOM(eXecute-Only-Memory) attribute control"]
313pub type LpcacXomW<'a, REG> = crate::BitWriter<'a, REG, LpcacXom>;
314impl<'a, REG> LpcacXomW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Disabled."]
319    #[inline(always)]
320    pub fn disable(self) -> &'a mut crate::W<REG> {
321        self.variant(LpcacXom::Disable)
322    }
323    #[doc = "Enabled."]
324    #[inline(always)]
325    pub fn enable(self) -> &'a mut crate::W<REG> {
326        self.variant(LpcacXom::Enable)
327    }
328}
329#[doc = "Request LPCAC memories.\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum LpcacMemReq {
333    #[doc = "0: Configure shared memories RAMX1 as general memories."]
334    Disable = 0,
335    #[doc = "1: Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."]
336    Enable = 1,
337}
338impl From<LpcacMemReq> for bool {
339    #[inline(always)]
340    fn from(variant: LpcacMemReq) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `LPCAC_MEM_REQ` reader - Request LPCAC memories."]
345pub type LpcacMemReqR = crate::BitReader<LpcacMemReq>;
346impl LpcacMemReqR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> LpcacMemReq {
350        match self.bits {
351            false => LpcacMemReq::Disable,
352            true => LpcacMemReq::Enable,
353        }
354    }
355    #[doc = "Configure shared memories RAMX1 as general memories."]
356    #[inline(always)]
357    pub fn is_disable(&self) -> bool {
358        *self == LpcacMemReq::Disable
359    }
360    #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."]
361    #[inline(always)]
362    pub fn is_enable(&self) -> bool {
363        *self == LpcacMemReq::Enable
364    }
365}
366#[doc = "Field `LPCAC_MEM_REQ` writer - Request LPCAC memories."]
367pub type LpcacMemReqW<'a, REG> = crate::BitWriter<'a, REG, LpcacMemReq>;
368impl<'a, REG> LpcacMemReqW<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "Configure shared memories RAMX1 as general memories."]
373    #[inline(always)]
374    pub fn disable(self) -> &'a mut crate::W<REG> {
375        self.variant(LpcacMemReq::Disable)
376    }
377    #[doc = "Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset."]
378    #[inline(always)]
379    pub fn enable(self) -> &'a mut crate::W<REG> {
380        self.variant(LpcacMemReq::Enable)
381    }
382}
383impl R {
384    #[doc = "Bit 0 - Disables/enables the cache function."]
385    #[inline(always)]
386    pub fn dis_lpcac(&self) -> DisLpcacR {
387        DisLpcacR::new((self.bits & 1) != 0)
388    }
389    #[doc = "Bit 1 - Clears the cache function."]
390    #[inline(always)]
391    pub fn clr_lpcac(&self) -> ClrLpcacR {
392        ClrLpcacR::new(((self.bits >> 1) & 1) != 0)
393    }
394    #[doc = "Bit 2 - Forces no allocation."]
395    #[inline(always)]
396    pub fn frc_no_alloc(&self) -> FrcNoAllocR {
397        FrcNoAllocR::new(((self.bits >> 2) & 1) != 0)
398    }
399    #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."]
400    #[inline(always)]
401    pub fn dis_lpcac_wtbf(&self) -> DisLpcacWtbfR {
402        DisLpcacWtbfR::new(((self.bits >> 4) & 1) != 0)
403    }
404    #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."]
405    #[inline(always)]
406    pub fn lim_lpcac_wtbf(&self) -> LimLpcacWtbfR {
407        LimLpcacWtbfR::new(((self.bits >> 5) & 1) != 0)
408    }
409    #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"]
410    #[inline(always)]
411    pub fn lpcac_xom(&self) -> LpcacXomR {
412        LpcacXomR::new(((self.bits >> 7) & 1) != 0)
413    }
414    #[doc = "Bit 8 - Request LPCAC memories."]
415    #[inline(always)]
416    pub fn lpcac_mem_req(&self) -> LpcacMemReqR {
417        LpcacMemReqR::new(((self.bits >> 8) & 1) != 0)
418    }
419}
420#[cfg(feature = "debug")]
421impl core::fmt::Debug for R {
422    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
423        f.debug_struct("LPCAC_CTRL")
424            .field("dis_lpcac", &self.dis_lpcac())
425            .field("clr_lpcac", &self.clr_lpcac())
426            .field("frc_no_alloc", &self.frc_no_alloc())
427            .field("dis_lpcac_wtbf", &self.dis_lpcac_wtbf())
428            .field("lim_lpcac_wtbf", &self.lim_lpcac_wtbf())
429            .field("lpcac_xom", &self.lpcac_xom())
430            .field("lpcac_mem_req", &self.lpcac_mem_req())
431            .finish()
432    }
433}
434impl W {
435    #[doc = "Bit 0 - Disables/enables the cache function."]
436    #[inline(always)]
437    pub fn dis_lpcac(&mut self) -> DisLpcacW<'_, LpcacCtrlSpec> {
438        DisLpcacW::new(self, 0)
439    }
440    #[doc = "Bit 1 - Clears the cache function."]
441    #[inline(always)]
442    pub fn clr_lpcac(&mut self) -> ClrLpcacW<'_, LpcacCtrlSpec> {
443        ClrLpcacW::new(self, 1)
444    }
445    #[doc = "Bit 2 - Forces no allocation."]
446    #[inline(always)]
447    pub fn frc_no_alloc(&mut self) -> FrcNoAllocW<'_, LpcacCtrlSpec> {
448        FrcNoAllocW::new(self, 2)
449    }
450    #[doc = "Bit 4 - Disable LPCAC Write Through Buffer."]
451    #[inline(always)]
452    pub fn dis_lpcac_wtbf(&mut self) -> DisLpcacWtbfW<'_, LpcacCtrlSpec> {
453        DisLpcacWtbfW::new(self, 4)
454    }
455    #[doc = "Bit 5 - Limit LPCAC Write Through Buffer."]
456    #[inline(always)]
457    pub fn lim_lpcac_wtbf(&mut self) -> LimLpcacWtbfW<'_, LpcacCtrlSpec> {
458        LimLpcacWtbfW::new(self, 5)
459    }
460    #[doc = "Bit 7 - LPCAC XOM(eXecute-Only-Memory) attribute control"]
461    #[inline(always)]
462    pub fn lpcac_xom(&mut self) -> LpcacXomW<'_, LpcacCtrlSpec> {
463        LpcacXomW::new(self, 7)
464    }
465    #[doc = "Bit 8 - Request LPCAC memories."]
466    #[inline(always)]
467    pub fn lpcac_mem_req(&mut self) -> LpcacMemReqW<'_, LpcacCtrlSpec> {
468        LpcacMemReqW::new(self, 8)
469    }
470}
471#[doc = "LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
472pub struct LpcacCtrlSpec;
473impl crate::RegisterSpec for LpcacCtrlSpec {
474    type Ux = u32;
475}
476#[doc = "`read()` method returns [`lpcac_ctrl::R`](R) reader structure"]
477impl crate::Readable for LpcacCtrlSpec {}
478#[doc = "`write(|w| ..)` method takes [`lpcac_ctrl::W`](W) writer structure"]
479impl crate::Writable for LpcacCtrlSpec {
480    type Safety = crate::Unsafe;
481}
482#[doc = "`reset()` method sets LPCAC_CTRL to value 0x31"]
483impl crate::Resettable for LpcacCtrlSpec {
484    const RESET_VALUE: u32 = 0x31;
485}
mcxa_pac/syscon/lpcac_ctrl.rs

mcxa_pac/syscon/
lpcac_ctrl.rs
