mcxa_pac/syscon/
debug_features_dp.rs

1#[doc = "Register `DEBUG_FEATURES_DP` reader"]
2pub type R = crate::R<DebugFeaturesDpSpec>;
3#[doc = "Register `DEBUG_FEATURES_DP` writer"]
4pub type W = crate::W<DebugFeaturesDpSpec>;
5#[doc = "CPU0 invasive debug control\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Cpu0Dbgen {
10    #[doc = "1: Disables debug"]
11    Disable = 1,
12    #[doc = "2: Enables debug"]
13    Enable = 2,
14}
15impl From<Cpu0Dbgen> for u8 {
16    #[inline(always)]
17    fn from(variant: Cpu0Dbgen) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Cpu0Dbgen {
22    type Ux = u8;
23}
24impl crate::IsEnum for Cpu0Dbgen {}
25#[doc = "Field `CPU0_DBGEN` reader - CPU0 invasive debug control"]
26pub type Cpu0DbgenR = crate::FieldReader<Cpu0Dbgen>;
27impl Cpu0DbgenR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Cpu0Dbgen> {
31        match self.bits {
32            1 => Some(Cpu0Dbgen::Disable),
33            2 => Some(Cpu0Dbgen::Enable),
34            _ => None,
35        }
36    }
37    #[doc = "Disables debug"]
38    #[inline(always)]
39    pub fn is_disable(&self) -> bool {
40        *self == Cpu0Dbgen::Disable
41    }
42    #[doc = "Enables debug"]
43    #[inline(always)]
44    pub fn is_enable(&self) -> bool {
45        *self == Cpu0Dbgen::Enable
46    }
47}
48#[doc = "Field `CPU0_DBGEN` writer - CPU0 invasive debug control"]
49pub type Cpu0DbgenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Dbgen>;
50impl<'a, REG> Cpu0DbgenW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "Disables debug"]
56    #[inline(always)]
57    pub fn disable(self) -> &'a mut crate::W<REG> {
58        self.variant(Cpu0Dbgen::Disable)
59    }
60    #[doc = "Enables debug"]
61    #[inline(always)]
62    pub fn enable(self) -> &'a mut crate::W<REG> {
63        self.variant(Cpu0Dbgen::Enable)
64    }
65}
66#[doc = "CPU0 non-invasive debug control\n\nValue on reset: 0"]
67#[cfg_attr(feature = "defmt", derive(defmt::Format))]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69#[repr(u8)]
70pub enum Cpu0Niden {
71    #[doc = "1: Disables debug"]
72    Disable = 1,
73    #[doc = "2: Enables debug"]
74    Enable = 2,
75}
76impl From<Cpu0Niden> for u8 {
77    #[inline(always)]
78    fn from(variant: Cpu0Niden) -> Self {
79        variant as _
80    }
81}
82impl crate::FieldSpec for Cpu0Niden {
83    type Ux = u8;
84}
85impl crate::IsEnum for Cpu0Niden {}
86#[doc = "Field `CPU0_NIDEN` reader - CPU0 non-invasive debug control"]
87pub type Cpu0NidenR = crate::FieldReader<Cpu0Niden>;
88impl Cpu0NidenR {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<Cpu0Niden> {
92        match self.bits {
93            1 => Some(Cpu0Niden::Disable),
94            2 => Some(Cpu0Niden::Enable),
95            _ => None,
96        }
97    }
98    #[doc = "Disables debug"]
99    #[inline(always)]
100    pub fn is_disable(&self) -> bool {
101        *self == Cpu0Niden::Disable
102    }
103    #[doc = "Enables debug"]
104    #[inline(always)]
105    pub fn is_enable(&self) -> bool {
106        *self == Cpu0Niden::Enable
107    }
108}
109#[doc = "Field `CPU0_NIDEN` writer - CPU0 non-invasive debug control"]
110pub type Cpu0NidenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Niden>;
111impl<'a, REG> Cpu0NidenW<'a, REG>
112where
113    REG: crate::Writable + crate::RegisterSpec,
114    REG::Ux: From<u8>,
115{
116    #[doc = "Disables debug"]
117    #[inline(always)]
118    pub fn disable(self) -> &'a mut crate::W<REG> {
119        self.variant(Cpu0Niden::Disable)
120    }
121    #[doc = "Enables debug"]
122    #[inline(always)]
123    pub fn enable(self) -> &'a mut crate::W<REG> {
124        self.variant(Cpu0Niden::Enable)
125    }
126}
127impl R {
128    #[doc = "Bits 0:1 - CPU0 invasive debug control"]
129    #[inline(always)]
130    pub fn cpu0_dbgen(&self) -> Cpu0DbgenR {
131        Cpu0DbgenR::new((self.bits & 3) as u8)
132    }
133    #[doc = "Bits 2:3 - CPU0 non-invasive debug control"]
134    #[inline(always)]
135    pub fn cpu0_niden(&self) -> Cpu0NidenR {
136        Cpu0NidenR::new(((self.bits >> 2) & 3) as u8)
137    }
138}
139#[cfg(feature = "debug")]
140impl core::fmt::Debug for R {
141    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
142        f.debug_struct("DEBUG_FEATURES_DP")
143            .field("cpu0_dbgen", &self.cpu0_dbgen())
144            .field("cpu0_niden", &self.cpu0_niden())
145            .finish()
146    }
147}
148impl W {
149    #[doc = "Bits 0:1 - CPU0 invasive debug control"]
150    #[inline(always)]
151    pub fn cpu0_dbgen(&mut self) -> Cpu0DbgenW<'_, DebugFeaturesDpSpec> {
152        Cpu0DbgenW::new(self, 0)
153    }
154    #[doc = "Bits 2:3 - CPU0 non-invasive debug control"]
155    #[inline(always)]
156    pub fn cpu0_niden(&mut self) -> Cpu0NidenW<'_, DebugFeaturesDpSpec> {
157        Cpu0NidenW::new(self, 2)
158    }
159}
160#[doc = "Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
161pub struct DebugFeaturesDpSpec;
162impl crate::RegisterSpec for DebugFeaturesDpSpec {
163    type Ux = u32;
164}
165#[doc = "`read()` method returns [`debug_features_dp::R`](R) reader structure"]
166impl crate::Readable for DebugFeaturesDpSpec {}
167#[doc = "`write(|w| ..)` method takes [`debug_features_dp::W`](W) writer structure"]
168impl crate::Writable for DebugFeaturesDpSpec {
169    type Safety = crate::Unsafe;
170}
171#[doc = "`reset()` method sets DEBUG_FEATURES_DP to value 0"]
172impl crate::Resettable for DebugFeaturesDpSpec {}
mcxa_pac/syscon/debug_features_dp.rs

mcxa_pac/syscon/
debug_features_dp.rs
