mcxa_pac/syscon/
ahbmatprio.rs

1#[doc = "Register `AHBMATPRIO` reader"]
2pub type R = crate::R<AhbmatprioSpec>;
3#[doc = "Register `AHBMATPRIO` writer"]
4pub type W = crate::W<AhbmatprioSpec>;
5#[doc = "CPU0 C-AHB bus master priority level\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Cpu0Cbus {
10    #[doc = "0: level 0"]
11    Level0 = 0,
12    #[doc = "1: level 1"]
13    Level1 = 1,
14    #[doc = "2: level 2"]
15    Level2 = 2,
16    #[doc = "3: level 3"]
17    Level3 = 3,
18}
19impl From<Cpu0Cbus> for u8 {
20    #[inline(always)]
21    fn from(variant: Cpu0Cbus) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for Cpu0Cbus {
26    type Ux = u8;
27}
28impl crate::IsEnum for Cpu0Cbus {}
29#[doc = "Field `CPU0_CBUS` reader - CPU0 C-AHB bus master priority level"]
30pub type Cpu0CbusR = crate::FieldReader<Cpu0Cbus>;
31impl Cpu0CbusR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Cpu0Cbus {
35        match self.bits {
36            0 => Cpu0Cbus::Level0,
37            1 => Cpu0Cbus::Level1,
38            2 => Cpu0Cbus::Level2,
39            3 => Cpu0Cbus::Level3,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "level 0"]
44    #[inline(always)]
45    pub fn is_level0(&self) -> bool {
46        *self == Cpu0Cbus::Level0
47    }
48    #[doc = "level 1"]
49    #[inline(always)]
50    pub fn is_level1(&self) -> bool {
51        *self == Cpu0Cbus::Level1
52    }
53    #[doc = "level 2"]
54    #[inline(always)]
55    pub fn is_level2(&self) -> bool {
56        *self == Cpu0Cbus::Level2
57    }
58    #[doc = "level 3"]
59    #[inline(always)]
60    pub fn is_level3(&self) -> bool {
61        *self == Cpu0Cbus::Level3
62    }
63}
64#[doc = "Field `CPU0_CBUS` writer - CPU0 C-AHB bus master priority level"]
65pub type Cpu0CbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Cbus, crate::Safe>;
66impl<'a, REG> Cpu0CbusW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "level 0"]
72    #[inline(always)]
73    pub fn level0(self) -> &'a mut crate::W<REG> {
74        self.variant(Cpu0Cbus::Level0)
75    }
76    #[doc = "level 1"]
77    #[inline(always)]
78    pub fn level1(self) -> &'a mut crate::W<REG> {
79        self.variant(Cpu0Cbus::Level1)
80    }
81    #[doc = "level 2"]
82    #[inline(always)]
83    pub fn level2(self) -> &'a mut crate::W<REG> {
84        self.variant(Cpu0Cbus::Level2)
85    }
86    #[doc = "level 3"]
87    #[inline(always)]
88    pub fn level3(self) -> &'a mut crate::W<REG> {
89        self.variant(Cpu0Cbus::Level3)
90    }
91}
92#[doc = "CPU0 S-AHB bus master priority level\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum Cpu0Sbus {
97    #[doc = "0: level 0"]
98    Level0 = 0,
99    #[doc = "1: level 1"]
100    Level1 = 1,
101    #[doc = "2: level 2"]
102    Level2 = 2,
103    #[doc = "3: level 3"]
104    Level3 = 3,
105}
106impl From<Cpu0Sbus> for u8 {
107    #[inline(always)]
108    fn from(variant: Cpu0Sbus) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for Cpu0Sbus {
113    type Ux = u8;
114}
115impl crate::IsEnum for Cpu0Sbus {}
116#[doc = "Field `CPU0_SBUS` reader - CPU0 S-AHB bus master priority level"]
117pub type Cpu0SbusR = crate::FieldReader<Cpu0Sbus>;
118impl Cpu0SbusR {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> Cpu0Sbus {
122        match self.bits {
123            0 => Cpu0Sbus::Level0,
124            1 => Cpu0Sbus::Level1,
125            2 => Cpu0Sbus::Level2,
126            3 => Cpu0Sbus::Level3,
127            _ => unreachable!(),
128        }
129    }
130    #[doc = "level 0"]
131    #[inline(always)]
132    pub fn is_level0(&self) -> bool {
133        *self == Cpu0Sbus::Level0
134    }
135    #[doc = "level 1"]
136    #[inline(always)]
137    pub fn is_level1(&self) -> bool {
138        *self == Cpu0Sbus::Level1
139    }
140    #[doc = "level 2"]
141    #[inline(always)]
142    pub fn is_level2(&self) -> bool {
143        *self == Cpu0Sbus::Level2
144    }
145    #[doc = "level 3"]
146    #[inline(always)]
147    pub fn is_level3(&self) -> bool {
148        *self == Cpu0Sbus::Level3
149    }
150}
151#[doc = "Field `CPU0_SBUS` writer - CPU0 S-AHB bus master priority level"]
152pub type Cpu0SbusW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu0Sbus, crate::Safe>;
153impl<'a, REG> Cpu0SbusW<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "level 0"]
159    #[inline(always)]
160    pub fn level0(self) -> &'a mut crate::W<REG> {
161        self.variant(Cpu0Sbus::Level0)
162    }
163    #[doc = "level 1"]
164    #[inline(always)]
165    pub fn level1(self) -> &'a mut crate::W<REG> {
166        self.variant(Cpu0Sbus::Level1)
167    }
168    #[doc = "level 2"]
169    #[inline(always)]
170    pub fn level2(self) -> &'a mut crate::W<REG> {
171        self.variant(Cpu0Sbus::Level2)
172    }
173    #[doc = "level 3"]
174    #[inline(always)]
175    pub fn level3(self) -> &'a mut crate::W<REG> {
176        self.variant(Cpu0Sbus::Level3)
177    }
178}
179#[doc = "SmartDMA-I bus master priority level\n\nValue on reset: 0"]
180#[cfg_attr(feature = "defmt", derive(defmt::Format))]
181#[derive(Clone, Copy, Debug, PartialEq, Eq)]
182#[repr(u8)]
183pub enum Cpu1CbusSmartDmaI {
184    #[doc = "0: level 0"]
185    Level0 = 0,
186    #[doc = "1: level 1"]
187    Level1 = 1,
188    #[doc = "2: level 2"]
189    Level2 = 2,
190    #[doc = "3: level 3"]
191    Level3 = 3,
192}
193impl From<Cpu1CbusSmartDmaI> for u8 {
194    #[inline(always)]
195    fn from(variant: Cpu1CbusSmartDmaI) -> Self {
196        variant as _
197    }
198}
199impl crate::FieldSpec for Cpu1CbusSmartDmaI {
200    type Ux = u8;
201}
202impl crate::IsEnum for Cpu1CbusSmartDmaI {}
203#[doc = "Field `CPU1_CBUS_SmartDMA_I` reader - SmartDMA-I bus master priority level"]
204pub type Cpu1CbusSmartDmaIR = crate::FieldReader<Cpu1CbusSmartDmaI>;
205impl Cpu1CbusSmartDmaIR {
206    #[doc = "Get enumerated values variant"]
207    #[inline(always)]
208    pub const fn variant(&self) -> Cpu1CbusSmartDmaI {
209        match self.bits {
210            0 => Cpu1CbusSmartDmaI::Level0,
211            1 => Cpu1CbusSmartDmaI::Level1,
212            2 => Cpu1CbusSmartDmaI::Level2,
213            3 => Cpu1CbusSmartDmaI::Level3,
214            _ => unreachable!(),
215        }
216    }
217    #[doc = "level 0"]
218    #[inline(always)]
219    pub fn is_level0(&self) -> bool {
220        *self == Cpu1CbusSmartDmaI::Level0
221    }
222    #[doc = "level 1"]
223    #[inline(always)]
224    pub fn is_level1(&self) -> bool {
225        *self == Cpu1CbusSmartDmaI::Level1
226    }
227    #[doc = "level 2"]
228    #[inline(always)]
229    pub fn is_level2(&self) -> bool {
230        *self == Cpu1CbusSmartDmaI::Level2
231    }
232    #[doc = "level 3"]
233    #[inline(always)]
234    pub fn is_level3(&self) -> bool {
235        *self == Cpu1CbusSmartDmaI::Level3
236    }
237}
238#[doc = "Field `CPU1_CBUS_SmartDMA_I` writer - SmartDMA-I bus master priority level"]
239pub type Cpu1CbusSmartDmaIW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu1CbusSmartDmaI, crate::Safe>;
240impl<'a, REG> Cpu1CbusSmartDmaIW<'a, REG>
241where
242    REG: crate::Writable + crate::RegisterSpec,
243    REG::Ux: From<u8>,
244{
245    #[doc = "level 0"]
246    #[inline(always)]
247    pub fn level0(self) -> &'a mut crate::W<REG> {
248        self.variant(Cpu1CbusSmartDmaI::Level0)
249    }
250    #[doc = "level 1"]
251    #[inline(always)]
252    pub fn level1(self) -> &'a mut crate::W<REG> {
253        self.variant(Cpu1CbusSmartDmaI::Level1)
254    }
255    #[doc = "level 2"]
256    #[inline(always)]
257    pub fn level2(self) -> &'a mut crate::W<REG> {
258        self.variant(Cpu1CbusSmartDmaI::Level2)
259    }
260    #[doc = "level 3"]
261    #[inline(always)]
262    pub fn level3(self) -> &'a mut crate::W<REG> {
263        self.variant(Cpu1CbusSmartDmaI::Level3)
264    }
265}
266#[doc = "SmartDMA-D bus master priority level\n\nValue on reset: 0"]
267#[cfg_attr(feature = "defmt", derive(defmt::Format))]
268#[derive(Clone, Copy, Debug, PartialEq, Eq)]
269#[repr(u8)]
270pub enum Cpu1SbusSmartDmaD {
271    #[doc = "0: level 0"]
272    Level0 = 0,
273    #[doc = "1: level 1"]
274    Level1 = 1,
275    #[doc = "2: level 2"]
276    Level2 = 2,
277    #[doc = "3: level 3"]
278    Level3 = 3,
279}
280impl From<Cpu1SbusSmartDmaD> for u8 {
281    #[inline(always)]
282    fn from(variant: Cpu1SbusSmartDmaD) -> Self {
283        variant as _
284    }
285}
286impl crate::FieldSpec for Cpu1SbusSmartDmaD {
287    type Ux = u8;
288}
289impl crate::IsEnum for Cpu1SbusSmartDmaD {}
290#[doc = "Field `CPU1_SBUS_SmartDMA_D` reader - SmartDMA-D bus master priority level"]
291pub type Cpu1SbusSmartDmaDR = crate::FieldReader<Cpu1SbusSmartDmaD>;
292impl Cpu1SbusSmartDmaDR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Cpu1SbusSmartDmaD {
296        match self.bits {
297            0 => Cpu1SbusSmartDmaD::Level0,
298            1 => Cpu1SbusSmartDmaD::Level1,
299            2 => Cpu1SbusSmartDmaD::Level2,
300            3 => Cpu1SbusSmartDmaD::Level3,
301            _ => unreachable!(),
302        }
303    }
304    #[doc = "level 0"]
305    #[inline(always)]
306    pub fn is_level0(&self) -> bool {
307        *self == Cpu1SbusSmartDmaD::Level0
308    }
309    #[doc = "level 1"]
310    #[inline(always)]
311    pub fn is_level1(&self) -> bool {
312        *self == Cpu1SbusSmartDmaD::Level1
313    }
314    #[doc = "level 2"]
315    #[inline(always)]
316    pub fn is_level2(&self) -> bool {
317        *self == Cpu1SbusSmartDmaD::Level2
318    }
319    #[doc = "level 3"]
320    #[inline(always)]
321    pub fn is_level3(&self) -> bool {
322        *self == Cpu1SbusSmartDmaD::Level3
323    }
324}
325#[doc = "Field `CPU1_SBUS_SmartDMA_D` writer - SmartDMA-D bus master priority level"]
326pub type Cpu1SbusSmartDmaDW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cpu1SbusSmartDmaD, crate::Safe>;
327impl<'a, REG> Cpu1SbusSmartDmaDW<'a, REG>
328where
329    REG: crate::Writable + crate::RegisterSpec,
330    REG::Ux: From<u8>,
331{
332    #[doc = "level 0"]
333    #[inline(always)]
334    pub fn level0(self) -> &'a mut crate::W<REG> {
335        self.variant(Cpu1SbusSmartDmaD::Level0)
336    }
337    #[doc = "level 1"]
338    #[inline(always)]
339    pub fn level1(self) -> &'a mut crate::W<REG> {
340        self.variant(Cpu1SbusSmartDmaD::Level1)
341    }
342    #[doc = "level 2"]
343    #[inline(always)]
344    pub fn level2(self) -> &'a mut crate::W<REG> {
345        self.variant(Cpu1SbusSmartDmaD::Level2)
346    }
347    #[doc = "level 3"]
348    #[inline(always)]
349    pub fn level3(self) -> &'a mut crate::W<REG> {
350        self.variant(Cpu1SbusSmartDmaD::Level3)
351    }
352}
353#[doc = "DMA0 controller bus master priority level\n\nValue on reset: 0"]
354#[cfg_attr(feature = "defmt", derive(defmt::Format))]
355#[derive(Clone, Copy, Debug, PartialEq, Eq)]
356#[repr(u8)]
357pub enum Dma0 {
358    #[doc = "0: level 0"]
359    Level0 = 0,
360    #[doc = "1: level 1"]
361    Level1 = 1,
362    #[doc = "2: level 2"]
363    Level2 = 2,
364    #[doc = "3: level 3"]
365    Level3 = 3,
366}
367impl From<Dma0> for u8 {
368    #[inline(always)]
369    fn from(variant: Dma0) -> Self {
370        variant as _
371    }
372}
373impl crate::FieldSpec for Dma0 {
374    type Ux = u8;
375}
376impl crate::IsEnum for Dma0 {}
377#[doc = "Field `DMA0` reader - DMA0 controller bus master priority level"]
378pub type Dma0R = crate::FieldReader<Dma0>;
379impl Dma0R {
380    #[doc = "Get enumerated values variant"]
381    #[inline(always)]
382    pub const fn variant(&self) -> Dma0 {
383        match self.bits {
384            0 => Dma0::Level0,
385            1 => Dma0::Level1,
386            2 => Dma0::Level2,
387            3 => Dma0::Level3,
388            _ => unreachable!(),
389        }
390    }
391    #[doc = "level 0"]
392    #[inline(always)]
393    pub fn is_level0(&self) -> bool {
394        *self == Dma0::Level0
395    }
396    #[doc = "level 1"]
397    #[inline(always)]
398    pub fn is_level1(&self) -> bool {
399        *self == Dma0::Level1
400    }
401    #[doc = "level 2"]
402    #[inline(always)]
403    pub fn is_level2(&self) -> bool {
404        *self == Dma0::Level2
405    }
406    #[doc = "level 3"]
407    #[inline(always)]
408    pub fn is_level3(&self) -> bool {
409        *self == Dma0::Level3
410    }
411}
412#[doc = "Field `DMA0` writer - DMA0 controller bus master priority level"]
413pub type Dma0W<'a, REG> = crate::FieldWriter<'a, REG, 2, Dma0, crate::Safe>;
414impl<'a, REG> Dma0W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417    REG::Ux: From<u8>,
418{
419    #[doc = "level 0"]
420    #[inline(always)]
421    pub fn level0(self) -> &'a mut crate::W<REG> {
422        self.variant(Dma0::Level0)
423    }
424    #[doc = "level 1"]
425    #[inline(always)]
426    pub fn level1(self) -> &'a mut crate::W<REG> {
427        self.variant(Dma0::Level1)
428    }
429    #[doc = "level 2"]
430    #[inline(always)]
431    pub fn level2(self) -> &'a mut crate::W<REG> {
432        self.variant(Dma0::Level2)
433    }
434    #[doc = "level 3"]
435    #[inline(always)]
436    pub fn level3(self) -> &'a mut crate::W<REG> {
437        self.variant(Dma0::Level3)
438    }
439}
440#[doc = "PKC and ELS bus master priority level\n\nValue on reset: 0"]
441#[cfg_attr(feature = "defmt", derive(defmt::Format))]
442#[derive(Clone, Copy, Debug, PartialEq, Eq)]
443#[repr(u8)]
444pub enum PkcEls {
445    #[doc = "0: level 0"]
446    Level0 = 0,
447    #[doc = "1: level 1"]
448    Level1 = 1,
449    #[doc = "2: level 2"]
450    Level2 = 2,
451    #[doc = "3: level 3"]
452    Level3 = 3,
453}
454impl From<PkcEls> for u8 {
455    #[inline(always)]
456    fn from(variant: PkcEls) -> Self {
457        variant as _
458    }
459}
460impl crate::FieldSpec for PkcEls {
461    type Ux = u8;
462}
463impl crate::IsEnum for PkcEls {}
464#[doc = "Field `PKC_ELS` reader - PKC and ELS bus master priority level"]
465pub type PkcElsR = crate::FieldReader<PkcEls>;
466impl PkcElsR {
467    #[doc = "Get enumerated values variant"]
468    #[inline(always)]
469    pub const fn variant(&self) -> PkcEls {
470        match self.bits {
471            0 => PkcEls::Level0,
472            1 => PkcEls::Level1,
473            2 => PkcEls::Level2,
474            3 => PkcEls::Level3,
475            _ => unreachable!(),
476        }
477    }
478    #[doc = "level 0"]
479    #[inline(always)]
480    pub fn is_level0(&self) -> bool {
481        *self == PkcEls::Level0
482    }
483    #[doc = "level 1"]
484    #[inline(always)]
485    pub fn is_level1(&self) -> bool {
486        *self == PkcEls::Level1
487    }
488    #[doc = "level 2"]
489    #[inline(always)]
490    pub fn is_level2(&self) -> bool {
491        *self == PkcEls::Level2
492    }
493    #[doc = "level 3"]
494    #[inline(always)]
495    pub fn is_level3(&self) -> bool {
496        *self == PkcEls::Level3
497    }
498}
499#[doc = "Field `PKC_ELS` writer - PKC and ELS bus master priority level"]
500pub type PkcElsW<'a, REG> = crate::FieldWriter<'a, REG, 2, PkcEls, crate::Safe>;
501impl<'a, REG> PkcElsW<'a, REG>
502where
503    REG: crate::Writable + crate::RegisterSpec,
504    REG::Ux: From<u8>,
505{
506    #[doc = "level 0"]
507    #[inline(always)]
508    pub fn level0(self) -> &'a mut crate::W<REG> {
509        self.variant(PkcEls::Level0)
510    }
511    #[doc = "level 1"]
512    #[inline(always)]
513    pub fn level1(self) -> &'a mut crate::W<REG> {
514        self.variant(PkcEls::Level1)
515    }
516    #[doc = "level 2"]
517    #[inline(always)]
518    pub fn level2(self) -> &'a mut crate::W<REG> {
519        self.variant(PkcEls::Level2)
520    }
521    #[doc = "level 3"]
522    #[inline(always)]
523    pub fn level3(self) -> &'a mut crate::W<REG> {
524        self.variant(PkcEls::Level3)
525    }
526}
527#[doc = "USB-FS bus master priority level\n\nValue on reset: 0"]
528#[cfg_attr(feature = "defmt", derive(defmt::Format))]
529#[derive(Clone, Copy, Debug, PartialEq, Eq)]
530#[repr(u8)]
531pub enum UsbFsEnet {
532    #[doc = "0: level 0"]
533    Level0 = 0,
534    #[doc = "1: level 1"]
535    Level1 = 1,
536    #[doc = "2: level 2"]
537    Level2 = 2,
538    #[doc = "3: level 3"]
539    Level3 = 3,
540}
541impl From<UsbFsEnet> for u8 {
542    #[inline(always)]
543    fn from(variant: UsbFsEnet) -> Self {
544        variant as _
545    }
546}
547impl crate::FieldSpec for UsbFsEnet {
548    type Ux = u8;
549}
550impl crate::IsEnum for UsbFsEnet {}
551#[doc = "Field `USB_FS_ENET` reader - USB-FS bus master priority level"]
552pub type UsbFsEnetR = crate::FieldReader<UsbFsEnet>;
553impl UsbFsEnetR {
554    #[doc = "Get enumerated values variant"]
555    #[inline(always)]
556    pub const fn variant(&self) -> UsbFsEnet {
557        match self.bits {
558            0 => UsbFsEnet::Level0,
559            1 => UsbFsEnet::Level1,
560            2 => UsbFsEnet::Level2,
561            3 => UsbFsEnet::Level3,
562            _ => unreachable!(),
563        }
564    }
565    #[doc = "level 0"]
566    #[inline(always)]
567    pub fn is_level0(&self) -> bool {
568        *self == UsbFsEnet::Level0
569    }
570    #[doc = "level 1"]
571    #[inline(always)]
572    pub fn is_level1(&self) -> bool {
573        *self == UsbFsEnet::Level1
574    }
575    #[doc = "level 2"]
576    #[inline(always)]
577    pub fn is_level2(&self) -> bool {
578        *self == UsbFsEnet::Level2
579    }
580    #[doc = "level 3"]
581    #[inline(always)]
582    pub fn is_level3(&self) -> bool {
583        *self == UsbFsEnet::Level3
584    }
585}
586#[doc = "Field `USB_FS_ENET` writer - USB-FS bus master priority level"]
587pub type UsbFsEnetW<'a, REG> = crate::FieldWriter<'a, REG, 2, UsbFsEnet, crate::Safe>;
588impl<'a, REG> UsbFsEnetW<'a, REG>
589where
590    REG: crate::Writable + crate::RegisterSpec,
591    REG::Ux: From<u8>,
592{
593    #[doc = "level 0"]
594    #[inline(always)]
595    pub fn level0(self) -> &'a mut crate::W<REG> {
596        self.variant(UsbFsEnet::Level0)
597    }
598    #[doc = "level 1"]
599    #[inline(always)]
600    pub fn level1(self) -> &'a mut crate::W<REG> {
601        self.variant(UsbFsEnet::Level1)
602    }
603    #[doc = "level 2"]
604    #[inline(always)]
605    pub fn level2(self) -> &'a mut crate::W<REG> {
606        self.variant(UsbFsEnet::Level2)
607    }
608    #[doc = "level 3"]
609    #[inline(always)]
610    pub fn level3(self) -> &'a mut crate::W<REG> {
611        self.variant(UsbFsEnet::Level3)
612    }
613}
614impl R {
615    #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"]
616    #[inline(always)]
617    pub fn cpu0_cbus(&self) -> Cpu0CbusR {
618        Cpu0CbusR::new((self.bits & 3) as u8)
619    }
620    #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"]
621    #[inline(always)]
622    pub fn cpu0_sbus(&self) -> Cpu0SbusR {
623        Cpu0SbusR::new(((self.bits >> 2) & 3) as u8)
624    }
625    #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"]
626    #[inline(always)]
627    pub fn cpu1_cbus_smart_dma_i(&self) -> Cpu1CbusSmartDmaIR {
628        Cpu1CbusSmartDmaIR::new(((self.bits >> 4) & 3) as u8)
629    }
630    #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"]
631    #[inline(always)]
632    pub fn cpu1_sbus_smart_dma_d(&self) -> Cpu1SbusSmartDmaDR {
633        Cpu1SbusSmartDmaDR::new(((self.bits >> 6) & 3) as u8)
634    }
635    #[doc = "Bits 8:9 - DMA0 controller bus master priority level"]
636    #[inline(always)]
637    pub fn dma0(&self) -> Dma0R {
638        Dma0R::new(((self.bits >> 8) & 3) as u8)
639    }
640    #[doc = "Bits 12:13 - PKC and ELS bus master priority level"]
641    #[inline(always)]
642    pub fn pkc_els(&self) -> PkcElsR {
643        PkcElsR::new(((self.bits >> 12) & 3) as u8)
644    }
645    #[doc = "Bits 24:25 - USB-FS bus master priority level"]
646    #[inline(always)]
647    pub fn usb_fs_enet(&self) -> UsbFsEnetR {
648        UsbFsEnetR::new(((self.bits >> 24) & 3) as u8)
649    }
650}
651#[cfg(feature = "debug")]
652impl core::fmt::Debug for R {
653    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
654        f.debug_struct("AHBMATPRIO")
655            .field("cpu0_cbus", &self.cpu0_cbus())
656            .field("cpu0_sbus", &self.cpu0_sbus())
657            .field("cpu1_cbus_smart_dma_i", &self.cpu1_cbus_smart_dma_i())
658            .field("cpu1_sbus_smart_dma_d", &self.cpu1_sbus_smart_dma_d())
659            .field("dma0", &self.dma0())
660            .field("pkc_els", &self.pkc_els())
661            .field("usb_fs_enet", &self.usb_fs_enet())
662            .finish()
663    }
664}
665impl W {
666    #[doc = "Bits 0:1 - CPU0 C-AHB bus master priority level"]
667    #[inline(always)]
668    pub fn cpu0_cbus(&mut self) -> Cpu0CbusW<'_, AhbmatprioSpec> {
669        Cpu0CbusW::new(self, 0)
670    }
671    #[doc = "Bits 2:3 - CPU0 S-AHB bus master priority level"]
672    #[inline(always)]
673    pub fn cpu0_sbus(&mut self) -> Cpu0SbusW<'_, AhbmatprioSpec> {
674        Cpu0SbusW::new(self, 2)
675    }
676    #[doc = "Bits 4:5 - SmartDMA-I bus master priority level"]
677    #[inline(always)]
678    pub fn cpu1_cbus_smart_dma_i(&mut self) -> Cpu1CbusSmartDmaIW<'_, AhbmatprioSpec> {
679        Cpu1CbusSmartDmaIW::new(self, 4)
680    }
681    #[doc = "Bits 6:7 - SmartDMA-D bus master priority level"]
682    #[inline(always)]
683    pub fn cpu1_sbus_smart_dma_d(&mut self) -> Cpu1SbusSmartDmaDW<'_, AhbmatprioSpec> {
684        Cpu1SbusSmartDmaDW::new(self, 6)
685    }
686    #[doc = "Bits 8:9 - DMA0 controller bus master priority level"]
687    #[inline(always)]
688    pub fn dma0(&mut self) -> Dma0W<'_, AhbmatprioSpec> {
689        Dma0W::new(self, 8)
690    }
691    #[doc = "Bits 12:13 - PKC and ELS bus master priority level"]
692    #[inline(always)]
693    pub fn pkc_els(&mut self) -> PkcElsW<'_, AhbmatprioSpec> {
694        PkcElsW::new(self, 12)
695    }
696    #[doc = "Bits 24:25 - USB-FS bus master priority level"]
697    #[inline(always)]
698    pub fn usb_fs_enet(&mut self) -> UsbFsEnetW<'_, AhbmatprioSpec> {
699        UsbFsEnetW::new(self, 24)
700    }
701}
702#[doc = "AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
703pub struct AhbmatprioSpec;
704impl crate::RegisterSpec for AhbmatprioSpec {
705    type Ux = u32;
706}
707#[doc = "`read()` method returns [`ahbmatprio::R`](R) reader structure"]
708impl crate::Readable for AhbmatprioSpec {}
709#[doc = "`write(|w| ..)` method takes [`ahbmatprio::W`](W) writer structure"]
710impl crate::Writable for AhbmatprioSpec {
711    type Safety = crate::Unsafe;
712}
713#[doc = "`reset()` method sets AHBMATPRIO to value 0"]
714impl crate::Resettable for AhbmatprioSpec {}
mcxa_pac/syscon/ahbmatprio.rs

mcxa_pac/syscon/
ahbmatprio.rs
