1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 _reserved0: [u8; 0x0200],
6 remap: Remap,
7 _reserved1: [u8; 0x0c],
8 ahbmatprio: Ahbmatprio,
9 _reserved2: [u8; 0x28],
10 cpu0nstckcal: Cpu0nstckcal,
11 _reserved3: [u8; 0x08],
12 nmisrc: Nmisrc,
13 protlvl: Protlvl,
14 _reserved5: [u8; 0x0128],
15 slowclkdiv: Slowclkdiv,
16 busclkdiv: Busclkdiv,
17 ahbclkdiv: Ahbclkdiv,
18 _reserved8: [u8; 0x04],
19 frohfdiv: Frohfdiv,
20 frolfdiv: Frolfdiv,
21 _reserved10: [u8; 0x54],
22 pll1clkdiv: Pll1clkdiv,
23 _reserved11: [u8; 0x14],
24 clkunlock: Clkunlock,
25 nvm_ctrl: NvmCtrl,
26 _reserved13: [u8; 0x10],
27 smart_dmaint: SmartDmaint,
28 _reserved14: [u8; 0x58],
29 ram_interleave: RamInterleave,
30 _reserved15: [u8; 0x0398],
31 cpustat: Cpustat,
32 _reserved16: [u8; 0x14],
33 lpcac_ctrl: LpcacCtrl,
34 _reserved17: [u8; 0x0110],
35 pwm0subctl: Pwm0subctl,
36 pwm1subctl: Pwm1subctl,
37 ctimerglobalstarten: Ctimerglobalstarten,
38 ram_ctrl: RamCtrl,
39 _reserved21: [u8; 0x0218],
40 gray_code_lsb: GrayCodeLsb,
41 gray_code_msb: GrayCodeMsb,
42 binary_code_lsb: BinaryCodeLsb,
43 binary_code_msb: BinaryCodeMsb,
44 _reserved25: [u8; 0x02a0],
45 els_udf: ElsUdf,
46 _reserved26: [u8; 0x08],
47 msfcfg: Msfcfg,
48 els_uid: [ElsUid; 4],
49 _reserved28: [u8; 0x0c],
50 rop_state: RopState,
51 _reserved29: [u8; 0x18],
52 sram_xen: SramXen,
53 sram_xen_dp: SramXenDp,
54 _reserved31: [u8; 0x20],
55 els_otp_lc_state: ElsOtpLcState,
56 els_otp_lc_state_dp: ElsOtpLcStateDp,
57 _reserved33: [u8; 0x0118],
58 debug_lock_en: DebugLockEn,
59 debug_features: DebugFeatures,
60 debug_features_dp: DebugFeaturesDp,
61 _reserved36: [u8; 0x08],
62 swd_access_cpu0: SwdAccessCpu0,
63 _reserved37: [u8; 0x08],
64 debug_auth_beacon: DebugAuthBeacon,
65 _reserved38: [u8; 0x2c],
66 jtag_id: JtagId,
67 device_type: DeviceType,
68 device_id0: DeviceId0,
69 dieid: Dieid,
70}
71impl RegisterBlock {
72 #[doc = "0x200 - AHB Matrix Remap Control"]
73 #[inline(always)]
74 pub const fn remap(&self) -> &Remap {
75 &self.remap
76 }
77 #[doc = "0x210 - AHB Matrix Priority Control"]
78 #[inline(always)]
79 pub const fn ahbmatprio(&self) -> &Ahbmatprio {
80 &self.ahbmatprio
81 }
82 #[doc = "0x23c - Non-Secure CPU0 System Tick Calibration"]
83 #[inline(always)]
84 pub const fn cpu0nstckcal(&self) -> &Cpu0nstckcal {
85 &self.cpu0nstckcal
86 }
87 #[doc = "0x248 - NMI Source Select"]
88 #[inline(always)]
89 pub const fn nmisrc(&self) -> &Nmisrc {
90 &self.nmisrc
91 }
92 #[doc = "0x24c - Protect Level Control"]
93 #[inline(always)]
94 pub const fn protlvl(&self) -> &Protlvl {
95 &self.protlvl
96 }
97 #[doc = "0x378 - SLOW_CLK Clock Divider"]
98 #[inline(always)]
99 pub const fn slowclkdiv(&self) -> &Slowclkdiv {
100 &self.slowclkdiv
101 }
102 #[doc = "0x37c - BUS_CLK Clock Divider"]
103 #[inline(always)]
104 pub const fn busclkdiv(&self) -> &Busclkdiv {
105 &self.busclkdiv
106 }
107 #[doc = "0x380 - System Clock Divider"]
108 #[inline(always)]
109 pub const fn ahbclkdiv(&self) -> &Ahbclkdiv {
110 &self.ahbclkdiv
111 }
112 #[doc = "0x388 - FRO_HF_DIV Clock Divider"]
113 #[inline(always)]
114 pub const fn frohfdiv(&self) -> &Frohfdiv {
115 &self.frohfdiv
116 }
117 #[doc = "0x38c - FRO_LF_DIV Clock Divider"]
118 #[inline(always)]
119 pub const fn frolfdiv(&self) -> &Frolfdiv {
120 &self.frolfdiv
121 }
122 #[doc = "0x3e4 - PLL1_CLK_DIV Clock Divider"]
123 #[inline(always)]
124 pub const fn pll1clkdiv(&self) -> &Pll1clkdiv {
125 &self.pll1clkdiv
126 }
127 #[doc = "0x3fc - Clock Configuration Unlock"]
128 #[inline(always)]
129 pub const fn clkunlock(&self) -> &Clkunlock {
130 &self.clkunlock
131 }
132 #[doc = "0x400 - NVM Control"]
133 #[inline(always)]
134 pub const fn nvm_ctrl(&self) -> &NvmCtrl {
135 &self.nvm_ctrl
136 }
137 #[doc = "0x414 - SmartDMA Interrupt Hijack"]
138 #[inline(always)]
139 pub const fn smart_dmaint(&self) -> &SmartDmaint {
140 &self.smart_dmaint
141 }
142 #[doc = "0x470 - Controls RAM Interleave Integration"]
143 #[inline(always)]
144 pub const fn ram_interleave(&self) -> &RamInterleave {
145 &self.ram_interleave
146 }
147 #[doc = "0x80c - CPU Status"]
148 #[inline(always)]
149 pub const fn cpustat(&self) -> &Cpustat {
150 &self.cpustat
151 }
152 #[doc = "0x824 - LPCAC Control"]
153 #[inline(always)]
154 pub const fn lpcac_ctrl(&self) -> &LpcacCtrl {
155 &self.lpcac_ctrl
156 }
157 #[doc = "0x938 - PWM0 Submodule Control"]
158 #[inline(always)]
159 pub const fn pwm0subctl(&self) -> &Pwm0subctl {
160 &self.pwm0subctl
161 }
162 #[doc = "0x93c - PWM1 Submodule Control"]
163 #[inline(always)]
164 pub const fn pwm1subctl(&self) -> &Pwm1subctl {
165 &self.pwm1subctl
166 }
167 #[doc = "0x940 - CTIMER Global Start Enable"]
168 #[inline(always)]
169 pub const fn ctimerglobalstarten(&self) -> &Ctimerglobalstarten {
170 &self.ctimerglobalstarten
171 }
172 #[doc = "0x944 - RAM Control"]
173 #[inline(always)]
174 pub const fn ram_ctrl(&self) -> &RamCtrl {
175 &self.ram_ctrl
176 }
177 #[doc = "0xb60 - Gray to Binary Converter Gray Code \\[31:0\\]"]
178 #[inline(always)]
179 pub const fn gray_code_lsb(&self) -> &GrayCodeLsb {
180 &self.gray_code_lsb
181 }
182 #[doc = "0xb64 - Gray to Binary Converter Gray Code \\[41:32\\]"]
183 #[inline(always)]
184 pub const fn gray_code_msb(&self) -> &GrayCodeMsb {
185 &self.gray_code_msb
186 }
187 #[doc = "0xb68 - Gray to Binary Converter Binary Code \\[31:0\\]"]
188 #[inline(always)]
189 pub const fn binary_code_lsb(&self) -> &BinaryCodeLsb {
190 &self.binary_code_lsb
191 }
192 #[doc = "0xb6c - Gray to Binary Converter Binary Code \\[41:32\\]"]
193 #[inline(always)]
194 pub const fn binary_code_msb(&self) -> &BinaryCodeMsb {
195 &self.binary_code_msb
196 }
197 #[doc = "0xe10 - UDF Control"]
198 #[inline(always)]
199 pub const fn els_udf(&self) -> &ElsUdf {
200 &self.els_udf
201 }
202 #[doc = "0xe1c - MSF Configuration"]
203 #[inline(always)]
204 pub const fn msfcfg(&self) -> &Msfcfg {
205 &self.msfcfg
206 }
207 #[doc = "0xe20..0xe30 - Device UID n"]
208 #[inline(always)]
209 pub const fn els_uid(&self, n: usize) -> &ElsUid {
210 &self.els_uid[n]
211 }
212 #[doc = "Iterator for array of:"]
213 #[doc = "0xe20..0xe30 - Device UID n"]
214 #[inline(always)]
215 pub fn els_uid_iter(&self) -> impl Iterator<Item = &ElsUid> {
216 self.els_uid.iter()
217 }
218 #[doc = "0xe3c - ROP State Register"]
219 #[inline(always)]
220 pub const fn rop_state(&self) -> &RopState {
221 &self.rop_state
222 }
223 #[doc = "0xe58 - RAM XEN Control"]
224 #[inline(always)]
225 pub const fn sram_xen(&self) -> &SramXen {
226 &self.sram_xen
227 }
228 #[doc = "0xe5c - RAM XEN Control (Duplicate)"]
229 #[inline(always)]
230 pub const fn sram_xen_dp(&self) -> &SramXenDp {
231 &self.sram_xen_dp
232 }
233 #[doc = "0xe80 - Life Cycle State Register"]
234 #[inline(always)]
235 pub const fn els_otp_lc_state(&self) -> &ElsOtpLcState {
236 &self.els_otp_lc_state
237 }
238 #[doc = "0xe84 - Life Cycle State Register (Duplicate)"]
239 #[inline(always)]
240 pub const fn els_otp_lc_state_dp(&self) -> &ElsOtpLcStateDp {
241 &self.els_otp_lc_state_dp
242 }
243 #[doc = "0xfa0 - Control Write Access to Security"]
244 #[inline(always)]
245 pub const fn debug_lock_en(&self) -> &DebugLockEn {
246 &self.debug_lock_en
247 }
248 #[doc = "0xfa4 - Cortex Debug Features Control"]
249 #[inline(always)]
250 pub const fn debug_features(&self) -> &DebugFeatures {
251 &self.debug_features
252 }
253 #[doc = "0xfa8 - Cortex Debug Features Control (Duplicate)"]
254 #[inline(always)]
255 pub const fn debug_features_dp(&self) -> &DebugFeaturesDp {
256 &self.debug_features_dp
257 }
258 #[doc = "0xfb4 - CPU0 Software Debug Access"]
259 #[inline(always)]
260 pub const fn swd_access_cpu0(&self) -> &SwdAccessCpu0 {
261 &self.swd_access_cpu0
262 }
263 #[doc = "0xfc0 - Debug Authentication BEACON"]
264 #[inline(always)]
265 pub const fn debug_auth_beacon(&self) -> &DebugAuthBeacon {
266 &self.debug_auth_beacon
267 }
268 #[doc = "0xff0 - JTAG Chip ID"]
269 #[inline(always)]
270 pub const fn jtag_id(&self) -> &JtagId {
271 &self.jtag_id
272 }
273 #[doc = "0xff4 - Device Type"]
274 #[inline(always)]
275 pub const fn device_type(&self) -> &DeviceType {
276 &self.device_type
277 }
278 #[doc = "0xff8 - Device ID"]
279 #[inline(always)]
280 pub const fn device_id0(&self) -> &DeviceId0 {
281 &self.device_id0
282 }
283 #[doc = "0xffc - Chip Revision ID and Number"]
284 #[inline(always)]
285 pub const fn dieid(&self) -> &Dieid {
286 &self.dieid
287 }
288}
289#[doc = "REMAP (rw) register accessor: AHB Matrix Remap Control\n\nYou can [`read`](crate::Reg::read) this register and get [`remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remap`] module"]
290#[doc(alias = "REMAP")]
291pub type Remap = crate::Reg<remap::RemapSpec>;
292#[doc = "AHB Matrix Remap Control"]
293pub mod remap;
294#[doc = "AHBMATPRIO (rw) register accessor: AHB Matrix Priority Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbmatprio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbmatprio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbmatprio`] module"]
295#[doc(alias = "AHBMATPRIO")]
296pub type Ahbmatprio = crate::Reg<ahbmatprio::AhbmatprioSpec>;
297#[doc = "AHB Matrix Priority Control"]
298pub mod ahbmatprio;
299#[doc = "CPU0NSTCKCAL (rw) register accessor: Non-Secure CPU0 System Tick Calibration\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu0nstckcal::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu0nstckcal::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu0nstckcal`] module"]
300#[doc(alias = "CPU0NSTCKCAL")]
301pub type Cpu0nstckcal = crate::Reg<cpu0nstckcal::Cpu0nstckcalSpec>;
302#[doc = "Non-Secure CPU0 System Tick Calibration"]
303pub mod cpu0nstckcal;
304#[doc = "NMISRC (rw) register accessor: NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmisrc`] module"]
305#[doc(alias = "NMISRC")]
306pub type Nmisrc = crate::Reg<nmisrc::NmisrcSpec>;
307#[doc = "NMI Source Select"]
308pub mod nmisrc;
309#[doc = "PROTLVL (rw) register accessor: Protect Level Control\n\nYou can [`read`](crate::Reg::read) this register and get [`protlvl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`protlvl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@protlvl`] module"]
310#[doc(alias = "PROTLVL")]
311pub type Protlvl = crate::Reg<protlvl::ProtlvlSpec>;
312#[doc = "Protect Level Control"]
313pub mod protlvl;
314#[doc = "SLOWCLKDIV (rw) register accessor: SLOW_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`slowclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slowclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slowclkdiv`] module"]
315#[doc(alias = "SLOWCLKDIV")]
316pub type Slowclkdiv = crate::Reg<slowclkdiv::SlowclkdivSpec>;
317#[doc = "SLOW_CLK Clock Divider"]
318pub mod slowclkdiv;
319#[doc = "BUSCLKDIV (rw) register accessor: BUS_CLK Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`busclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busclkdiv`] module"]
320#[doc(alias = "BUSCLKDIV")]
321pub type Busclkdiv = crate::Reg<busclkdiv::BusclkdivSpec>;
322#[doc = "BUS_CLK Clock Divider"]
323pub mod busclkdiv;
324#[doc = "AHBCLKDIV (rw) register accessor: System Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahbclkdiv`] module"]
325#[doc(alias = "AHBCLKDIV")]
326pub type Ahbclkdiv = crate::Reg<ahbclkdiv::AhbclkdivSpec>;
327#[doc = "System Clock Divider"]
328pub mod ahbclkdiv;
329#[doc = "FROHFDIV (rw) register accessor: FRO_HF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frohfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frohfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frohfdiv`] module"]
330#[doc(alias = "FROHFDIV")]
331pub type Frohfdiv = crate::Reg<frohfdiv::FrohfdivSpec>;
332#[doc = "FRO_HF_DIV Clock Divider"]
333pub mod frohfdiv;
334#[doc = "FROLFDIV (rw) register accessor: FRO_LF_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`frolfdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frolfdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frolfdiv`] module"]
335#[doc(alias = "FROLFDIV")]
336pub type Frolfdiv = crate::Reg<frolfdiv::FrolfdivSpec>;
337#[doc = "FRO_LF_DIV Clock Divider"]
338pub mod frolfdiv;
339#[doc = "PLL1CLKDIV (rw) register accessor: PLL1_CLK_DIV Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pll1clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll1clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll1clkdiv`] module"]
340#[doc(alias = "PLL1CLKDIV")]
341pub type Pll1clkdiv = crate::Reg<pll1clkdiv::Pll1clkdivSpec>;
342#[doc = "PLL1_CLK_DIV Clock Divider"]
343pub mod pll1clkdiv;
344#[doc = "CLKUNLOCK (rw) register accessor: Clock Configuration Unlock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkunlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkunlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkunlock`] module"]
345#[doc(alias = "CLKUNLOCK")]
346pub type Clkunlock = crate::Reg<clkunlock::ClkunlockSpec>;
347#[doc = "Clock Configuration Unlock"]
348pub mod clkunlock;
349#[doc = "NVM_CTRL (rw) register accessor: NVM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`nvm_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvm_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nvm_ctrl`] module"]
350#[doc(alias = "NVM_CTRL")]
351pub type NvmCtrl = crate::Reg<nvm_ctrl::NvmCtrlSpec>;
352#[doc = "NVM Control"]
353pub mod nvm_ctrl;
354#[doc = "SmartDMAINT (rw) register accessor: SmartDMA Interrupt Hijack\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dmaint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dmaint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dmaint`] module"]
355#[doc(alias = "SmartDMAINT")]
356pub type SmartDmaint = crate::Reg<smart_dmaint::SmartDmaintSpec>;
357#[doc = "SmartDMA Interrupt Hijack"]
358pub mod smart_dmaint;
359#[doc = "RAM_INTERLEAVE (rw) register accessor: Controls RAM Interleave Integration\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_interleave::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_interleave::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_interleave`] module"]
360#[doc(alias = "RAM_INTERLEAVE")]
361pub type RamInterleave = crate::Reg<ram_interleave::RamInterleaveSpec>;
362#[doc = "Controls RAM Interleave Integration"]
363pub mod ram_interleave;
364#[doc = "CPUSTAT (r) register accessor: CPU Status\n\nYou can [`read`](crate::Reg::read) this register and get [`cpustat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpustat`] module"]
365#[doc(alias = "CPUSTAT")]
366pub type Cpustat = crate::Reg<cpustat::CpustatSpec>;
367#[doc = "CPU Status"]
368pub mod cpustat;
369#[doc = "LPCAC_CTRL (rw) register accessor: LPCAC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`lpcac_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcac_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpcac_ctrl`] module"]
370#[doc(alias = "LPCAC_CTRL")]
371pub type LpcacCtrl = crate::Reg<lpcac_ctrl::LpcacCtrlSpec>;
372#[doc = "LPCAC Control"]
373pub mod lpcac_ctrl;
374#[doc = "PWM0SUBCTL (rw) register accessor: PWM0 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0subctl`] module"]
375#[doc(alias = "PWM0SUBCTL")]
376pub type Pwm0subctl = crate::Reg<pwm0subctl::Pwm0subctlSpec>;
377#[doc = "PWM0 Submodule Control"]
378pub mod pwm0subctl;
379#[doc = "PWM1SUBCTL (rw) register accessor: PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1subctl`] module"]
380#[doc(alias = "PWM1SUBCTL")]
381pub type Pwm1subctl = crate::Reg<pwm1subctl::Pwm1subctlSpec>;
382#[doc = "PWM1 Submodule Control"]
383pub mod pwm1subctl;
384#[doc = "CTIMERGLOBALSTARTEN (rw) register accessor: CTIMER Global Start Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimerglobalstarten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimerglobalstarten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimerglobalstarten`] module"]
385#[doc(alias = "CTIMERGLOBALSTARTEN")]
386pub type Ctimerglobalstarten = crate::Reg<ctimerglobalstarten::CtimerglobalstartenSpec>;
387#[doc = "CTIMER Global Start Enable"]
388pub mod ctimerglobalstarten;
389#[doc = "RAM_CTRL (rw) register accessor: RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_ctrl`] module"]
390#[doc(alias = "RAM_CTRL")]
391pub type RamCtrl = crate::Reg<ram_ctrl::RamCtrlSpec>;
392#[doc = "RAM Control"]
393pub mod ram_ctrl;
394#[doc = "GRAY_CODE_LSB (rw) register accessor: Gray to Binary Converter Gray Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_lsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_lsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_lsb`] module"]
395#[doc(alias = "GRAY_CODE_LSB")]
396pub type GrayCodeLsb = crate::Reg<gray_code_lsb::GrayCodeLsbSpec>;
397#[doc = "Gray to Binary Converter Gray Code \\[31:0\\]"]
398pub mod gray_code_lsb;
399#[doc = "GRAY_CODE_MSB (rw) register accessor: Gray to Binary Converter Gray Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`gray_code_msb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gray_code_msb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gray_code_msb`] module"]
400#[doc(alias = "GRAY_CODE_MSB")]
401pub type GrayCodeMsb = crate::Reg<gray_code_msb::GrayCodeMsbSpec>;
402#[doc = "Gray to Binary Converter Gray Code \\[41:32\\]"]
403pub mod gray_code_msb;
404#[doc = "BINARY_CODE_LSB (r) register accessor: Gray to Binary Converter Binary Code \\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_lsb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_lsb`] module"]
405#[doc(alias = "BINARY_CODE_LSB")]
406pub type BinaryCodeLsb = crate::Reg<binary_code_lsb::BinaryCodeLsbSpec>;
407#[doc = "Gray to Binary Converter Binary Code \\[31:0\\]"]
408pub mod binary_code_lsb;
409#[doc = "BINARY_CODE_MSB (r) register accessor: Gray to Binary Converter Binary Code \\[41:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`binary_code_msb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@binary_code_msb`] module"]
410#[doc(alias = "BINARY_CODE_MSB")]
411pub type BinaryCodeMsb = crate::Reg<binary_code_msb::BinaryCodeMsbSpec>;
412#[doc = "Gray to Binary Converter Binary Code \\[41:32\\]"]
413pub mod binary_code_msb;
414#[doc = "ELS_UDF (rw) register accessor: UDF Control\n\nYou can [`read`](crate::Reg::read) this register and get [`els_udf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_udf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_udf`] module"]
415#[doc(alias = "ELS_UDF")]
416pub type ElsUdf = crate::Reg<els_udf::ElsUdfSpec>;
417#[doc = "UDF Control"]
418pub mod els_udf;
419#[doc = "MSFCFG (rw) register accessor: MSF Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`msfcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msfcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msfcfg`] module"]
420#[doc(alias = "MSFCFG")]
421pub type Msfcfg = crate::Reg<msfcfg::MsfcfgSpec>;
422#[doc = "MSF Configuration"]
423pub mod msfcfg;
424#[doc = "ELS_UID (rw) register accessor: Device UID n\n\nYou can [`read`](crate::Reg::read) this register and get [`els_uid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`els_uid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_uid`] module"]
425#[doc(alias = "ELS_UID")]
426pub type ElsUid = crate::Reg<els_uid::ElsUidSpec>;
427#[doc = "Device UID n"]
428pub mod els_uid;
429#[doc = "ROP_STATE (r) register accessor: ROP State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rop_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rop_state`] module"]
430#[doc(alias = "ROP_STATE")]
431pub type RopState = crate::Reg<rop_state::RopStateSpec>;
432#[doc = "ROP State Register"]
433pub mod rop_state;
434#[doc = "SRAM_XEN (rw) register accessor: RAM XEN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen`] module"]
435#[doc(alias = "SRAM_XEN")]
436pub type SramXen = crate::Reg<sram_xen::SramXenSpec>;
437#[doc = "RAM XEN Control"]
438pub mod sram_xen;
439#[doc = "SRAM_XEN_DP (rw) register accessor: RAM XEN Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_xen_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_xen_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_xen_dp`] module"]
440#[doc(alias = "SRAM_XEN_DP")]
441pub type SramXenDp = crate::Reg<sram_xen_dp::SramXenDpSpec>;
442#[doc = "RAM XEN Control (Duplicate)"]
443pub mod sram_xen_dp;
444#[doc = "ELS_OTP_LC_STATE (r) register accessor: Life Cycle State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state`] module"]
445#[doc(alias = "ELS_OTP_LC_STATE")]
446pub type ElsOtpLcState = crate::Reg<els_otp_lc_state::ElsOtpLcStateSpec>;
447#[doc = "Life Cycle State Register"]
448pub mod els_otp_lc_state;
449#[doc = "ELS_OTP_LC_STATE_DP (r) register accessor: Life Cycle State Register (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`els_otp_lc_state_dp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@els_otp_lc_state_dp`] module"]
450#[doc(alias = "ELS_OTP_LC_STATE_DP")]
451pub type ElsOtpLcStateDp = crate::Reg<els_otp_lc_state_dp::ElsOtpLcStateDpSpec>;
452#[doc = "Life Cycle State Register (Duplicate)"]
453pub mod els_otp_lc_state_dp;
454#[doc = "DEBUG_LOCK_EN (rw) register accessor: Control Write Access to Security\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_lock_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_lock_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_lock_en`] module"]
455#[doc(alias = "DEBUG_LOCK_EN")]
456pub type DebugLockEn = crate::Reg<debug_lock_en::DebugLockEnSpec>;
457#[doc = "Control Write Access to Security"]
458pub mod debug_lock_en;
459#[doc = "DEBUG_FEATURES (rw) register accessor: Cortex Debug Features Control\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features`] module"]
460#[doc(alias = "DEBUG_FEATURES")]
461pub type DebugFeatures = crate::Reg<debug_features::DebugFeaturesSpec>;
462#[doc = "Cortex Debug Features Control"]
463pub mod debug_features;
464#[doc = "DEBUG_FEATURES_DP (rw) register accessor: Cortex Debug Features Control (Duplicate)\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_features_dp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_features_dp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_features_dp`] module"]
465#[doc(alias = "DEBUG_FEATURES_DP")]
466pub type DebugFeaturesDp = crate::Reg<debug_features_dp::DebugFeaturesDpSpec>;
467#[doc = "Cortex Debug Features Control (Duplicate)"]
468pub mod debug_features_dp;
469#[doc = "SWD_ACCESS_CPU0 (rw) register accessor: CPU0 Software Debug Access\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_access_cpu0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_access_cpu0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swd_access_cpu0`] module"]
470#[doc(alias = "SWD_ACCESS_CPU0")]
471pub type SwdAccessCpu0 = crate::Reg<swd_access_cpu0::SwdAccessCpu0Spec>;
472#[doc = "CPU0 Software Debug Access"]
473pub mod swd_access_cpu0;
474#[doc = "DEBUG_AUTH_BEACON (rw) register accessor: Debug Authentication BEACON\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_auth_beacon::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_auth_beacon::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_auth_beacon`] module"]
475#[doc(alias = "DEBUG_AUTH_BEACON")]
476pub type DebugAuthBeacon = crate::Reg<debug_auth_beacon::DebugAuthBeaconSpec>;
477#[doc = "Debug Authentication BEACON"]
478pub mod debug_auth_beacon;
479#[doc = "JTAG_ID (r) register accessor: JTAG Chip ID\n\nYou can [`read`](crate::Reg::read) this register and get [`jtag_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_id`] module"]
480#[doc(alias = "JTAG_ID")]
481pub type JtagId = crate::Reg<jtag_id::JtagIdSpec>;
482#[doc = "JTAG Chip ID"]
483pub mod jtag_id;
484#[doc = "DEVICE_TYPE (r) register accessor: Device Type\n\nYou can [`read`](crate::Reg::read) this register and get [`device_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_type`] module"]
485#[doc(alias = "DEVICE_TYPE")]
486pub type DeviceType = crate::Reg<device_type::DeviceTypeSpec>;
487#[doc = "Device Type"]
488pub mod device_type;
489#[doc = "DEVICE_ID0 (r) register accessor: Device ID\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_id0`] module"]
490#[doc(alias = "DEVICE_ID0")]
491pub type DeviceId0 = crate::Reg<device_id0::DeviceId0Spec>;
492#[doc = "Device ID"]
493pub mod device_id0;
494#[doc = "DIEID (r) register accessor: Chip Revision ID and Number\n\nYou can [`read`](crate::Reg::read) this register and get [`dieid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieid`] module"]
495#[doc(alias = "DIEID")]
496pub type Dieid = crate::Reg<dieid::DieidSpec>;
497#[doc = "Chip Revision ID and Number"]
498pub mod dieid;