mcxa_pac/spc0/
vd_core_cfg.rs

1#[doc = "Register `VD_CORE_CFG` reader"]
2pub type R = crate::R<VdCoreCfgSpec>;
3#[doc = "Register `VD_CORE_CFG` writer"]
4pub type W = crate::W<VdCoreCfgSpec>;
5#[doc = "Core LVD Reset Enable\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Lvdre {
9    #[doc = "0: Disable"]
10    Disable = 0,
11    #[doc = "1: Enable"]
12    Enable = 1,
13}
14impl From<Lvdre> for bool {
15    #[inline(always)]
16    fn from(variant: Lvdre) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `LVDRE` reader - Core LVD Reset Enable"]
21pub type LvdreR = crate::BitReader<Lvdre>;
22impl LvdreR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Lvdre {
26        match self.bits {
27            false => Lvdre::Disable,
28            true => Lvdre::Enable,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Lvdre::Disable
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Lvdre::Enable
40    }
41}
42#[doc = "Field `LVDRE` writer - Core LVD Reset Enable"]
43pub type LvdreW<'a, REG> = crate::BitWriter<'a, REG, Lvdre>;
44impl<'a, REG> LvdreW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Lvdre::Disable)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Lvdre::Enable)
57    }
58}
59#[doc = "Core LVD Interrupt Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Lvdie {
63    #[doc = "0: Disable"]
64    Disable = 0,
65    #[doc = "1: Enable"]
66    Enable = 1,
67}
68impl From<Lvdie> for bool {
69    #[inline(always)]
70    fn from(variant: Lvdie) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `LVDIE` reader - Core LVD Interrupt Enable"]
75pub type LvdieR = crate::BitReader<Lvdie>;
76impl LvdieR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Lvdie {
80        match self.bits {
81            false => Lvdie::Disable,
82            true => Lvdie::Enable,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Lvdie::Disable
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Lvdie::Enable
94    }
95}
96#[doc = "Field `LVDIE` writer - Core LVD Interrupt Enable"]
97pub type LvdieW<'a, REG> = crate::BitWriter<'a, REG, Lvdie>;
98impl<'a, REG> LvdieW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Lvdie::Disable)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Lvdie::Enable)
111    }
112}
113#[doc = "Core Voltage Detect Reset Enable Lock\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Lock {
117    #[doc = "0: Allow"]
118    Allow = 0,
119    #[doc = "1: Deny"]
120    Deny = 1,
121}
122impl From<Lock> for bool {
123    #[inline(always)]
124    fn from(variant: Lock) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `LOCK` reader - Core Voltage Detect Reset Enable Lock"]
129pub type LockR = crate::BitReader<Lock>;
130impl LockR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Lock {
134        match self.bits {
135            false => Lock::Allow,
136            true => Lock::Deny,
137        }
138    }
139    #[doc = "Allow"]
140    #[inline(always)]
141    pub fn is_allow(&self) -> bool {
142        *self == Lock::Allow
143    }
144    #[doc = "Deny"]
145    #[inline(always)]
146    pub fn is_deny(&self) -> bool {
147        *self == Lock::Deny
148    }
149}
150#[doc = "Field `LOCK` writer - Core Voltage Detect Reset Enable Lock"]
151pub type LockW<'a, REG> = crate::BitWriter<'a, REG, Lock>;
152impl<'a, REG> LockW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Allow"]
157    #[inline(always)]
158    pub fn allow(self) -> &'a mut crate::W<REG> {
159        self.variant(Lock::Allow)
160    }
161    #[doc = "Deny"]
162    #[inline(always)]
163    pub fn deny(self) -> &'a mut crate::W<REG> {
164        self.variant(Lock::Deny)
165    }
166}
167impl R {
168    #[doc = "Bit 0 - Core LVD Reset Enable"]
169    #[inline(always)]
170    pub fn lvdre(&self) -> LvdreR {
171        LvdreR::new((self.bits & 1) != 0)
172    }
173    #[doc = "Bit 1 - Core LVD Interrupt Enable"]
174    #[inline(always)]
175    pub fn lvdie(&self) -> LvdieR {
176        LvdieR::new(((self.bits >> 1) & 1) != 0)
177    }
178    #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"]
179    #[inline(always)]
180    pub fn lock(&self) -> LockR {
181        LockR::new(((self.bits >> 16) & 1) != 0)
182    }
183}
184#[cfg(feature = "debug")]
185impl core::fmt::Debug for R {
186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187        f.debug_struct("VD_CORE_CFG")
188            .field("lvdre", &self.lvdre())
189            .field("lvdie", &self.lvdie())
190            .field("lock", &self.lock())
191            .finish()
192    }
193}
194impl W {
195    #[doc = "Bit 0 - Core LVD Reset Enable"]
196    #[inline(always)]
197    pub fn lvdre(&mut self) -> LvdreW<'_, VdCoreCfgSpec> {
198        LvdreW::new(self, 0)
199    }
200    #[doc = "Bit 1 - Core LVD Interrupt Enable"]
201    #[inline(always)]
202    pub fn lvdie(&mut self) -> LvdieW<'_, VdCoreCfgSpec> {
203        LvdieW::new(self, 1)
204    }
205    #[doc = "Bit 16 - Core Voltage Detect Reset Enable Lock"]
206    #[inline(always)]
207    pub fn lock(&mut self) -> LockW<'_, VdCoreCfgSpec> {
208        LockW::new(self, 16)
209    }
210}
211#[doc = "Core Voltage Detect Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`vd_core_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vd_core_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct VdCoreCfgSpec;
213impl crate::RegisterSpec for VdCoreCfgSpec {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`vd_core_cfg::R`](R) reader structure"]
217impl crate::Readable for VdCoreCfgSpec {}
218#[doc = "`write(|w| ..)` method takes [`vd_core_cfg::W`](W) writer structure"]
219impl crate::Writable for VdCoreCfgSpec {
220    type Safety = crate::Unsafe;
221}
222#[doc = "`reset()` method sets VD_CORE_CFG to value 0x01"]
223impl crate::Resettable for VdCoreCfgSpec {
224    const RESET_VALUE: u32 = 0x01;
225}
mcxa_pac/spc0/vd_core_cfg.rs

mcxa_pac/spc0/
vd_core_cfg.rs
