mcxa_pac/sgi0/
sgi_access_err.rs

1#[doc = "Register `sgi_access_err` reader"]
2pub type R = crate::R<SgiAccessErrSpec>;
3#[doc = "Register `sgi_access_err` writer"]
4pub type W = crate::W<SgiAccessErrSpec>;
5#[doc = "Field `apb_notav` reader - APB Error: address not available"]
6pub type ApbNotavR = crate::BitReader;
7#[doc = "Field `apb_notav` writer - APB Error: address not available"]
8pub type ApbNotavW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `apb_wrgmd` reader - APB Error: Wrong access mode"]
10pub type ApbWrgmdR = crate::BitReader;
11#[doc = "Field `apb_wrgmd` writer - APB Error: Wrong access mode"]
12pub type ApbWrgmdW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `accerr_rsvd1` reader - reserved for future erors on SPB I/F"]
14pub type AccerrRsvd1R = crate::FieldReader;
15#[doc = "Field `apb_master` reader - APB Master that triggered first APB error"]
16pub type ApbMasterR = crate::FieldReader;
17#[doc = "Field `apb_master` writer - APB Master that triggered first APB error"]
18pub type ApbMasterW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
19#[doc = "Field `accerr_rsvd2` reader - reserved for more block errors"]
20pub type AccerrRsvd2R = crate::FieldReader<u32>;
21impl R {
22    #[doc = "Bit 0 - APB Error: address not available"]
23    #[inline(always)]
24    pub fn apb_notav(&self) -> ApbNotavR {
25        ApbNotavR::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - APB Error: Wrong access mode"]
28    #[inline(always)]
29    pub fn apb_wrgmd(&self) -> ApbWrgmdR {
30        ApbWrgmdR::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bits 2:3 - reserved for future erors on SPB I/F"]
33    #[inline(always)]
34    pub fn accerr_rsvd1(&self) -> AccerrRsvd1R {
35        AccerrRsvd1R::new(((self.bits >> 2) & 3) as u8)
36    }
37    #[doc = "Bits 4:7 - APB Master that triggered first APB error"]
38    #[inline(always)]
39    pub fn apb_master(&self) -> ApbMasterR {
40        ApbMasterR::new(((self.bits >> 4) & 0x0f) as u8)
41    }
42    #[doc = "Bits 8:31 - reserved for more block errors"]
43    #[inline(always)]
44    pub fn accerr_rsvd2(&self) -> AccerrRsvd2R {
45        AccerrRsvd2R::new((self.bits >> 8) & 0x00ff_ffff)
46    }
47}
48#[cfg(feature = "debug")]
49impl core::fmt::Debug for R {
50    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
51        f.debug_struct("sgi_access_err")
52            .field("apb_notav", &self.apb_notav())
53            .field("apb_wrgmd", &self.apb_wrgmd())
54            .field("accerr_rsvd1", &self.accerr_rsvd1())
55            .field("apb_master", &self.apb_master())
56            .field("accerr_rsvd2", &self.accerr_rsvd2())
57            .finish()
58    }
59}
60impl W {
61    #[doc = "Bit 0 - APB Error: address not available"]
62    #[inline(always)]
63    pub fn apb_notav(&mut self) -> ApbNotavW<'_, SgiAccessErrSpec> {
64        ApbNotavW::new(self, 0)
65    }
66    #[doc = "Bit 1 - APB Error: Wrong access mode"]
67    #[inline(always)]
68    pub fn apb_wrgmd(&mut self) -> ApbWrgmdW<'_, SgiAccessErrSpec> {
69        ApbWrgmdW::new(self, 1)
70    }
71    #[doc = "Bits 4:7 - APB Master that triggered first APB error"]
72    #[inline(always)]
73    pub fn apb_master(&mut self) -> ApbMasterW<'_, SgiAccessErrSpec> {
74        ApbMasterW::new(self, 4)
75    }
76}
77#[doc = "Access Error\n\nYou can [`read`](crate::Reg::read) this register and get [`sgi_access_err::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sgi_access_err::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
78pub struct SgiAccessErrSpec;
79impl crate::RegisterSpec for SgiAccessErrSpec {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [`sgi_access_err::R`](R) reader structure"]
83impl crate::Readable for SgiAccessErrSpec {}
84#[doc = "`write(|w| ..)` method takes [`sgi_access_err::W`](W) writer structure"]
85impl crate::Writable for SgiAccessErrSpec {
86    type Safety = crate::Unsafe;
87}
88#[doc = "`reset()` method sets sgi_access_err to value 0"]
89impl crate::Resettable for SgiAccessErrSpec {}
mcxa_pac/sgi0/sgi_access_err.rs

mcxa_pac/sgi0/
sgi_access_err.rs
