mcxa_pac/scg0/
spllndiv.rs

1#[doc = "Register `SPLLNDIV` reader"]
2pub type R = crate::R<SpllndivSpec>;
3#[doc = "Register `SPLLNDIV` writer"]
4pub type W = crate::W<SpllndivSpec>;
5#[doc = "Field `NDIV` reader - Pre-divider divider ratio (N-divider)."]
6pub type NdivR = crate::FieldReader;
7#[doc = "Field `NDIV` writer - Pre-divider divider ratio (N-divider)."]
8pub type NdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Pre-divider ratio change request.\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Nreq {
13    #[doc = "0: Pre-divider ratio change is not requested"]
14    Disabled = 0,
15    #[doc = "1: Pre-divider ratio change is requested"]
16    Enabled = 1,
17}
18impl From<Nreq> for bool {
19    #[inline(always)]
20    fn from(variant: Nreq) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `NREQ` reader - Pre-divider ratio change request."]
25pub type NreqR = crate::BitReader<Nreq>;
26impl NreqR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Nreq {
30        match self.bits {
31            false => Nreq::Disabled,
32            true => Nreq::Enabled,
33        }
34    }
35    #[doc = "Pre-divider ratio change is not requested"]
36    #[inline(always)]
37    pub fn is_disabled(&self) -> bool {
38        *self == Nreq::Disabled
39    }
40    #[doc = "Pre-divider ratio change is requested"]
41    #[inline(always)]
42    pub fn is_enabled(&self) -> bool {
43        *self == Nreq::Enabled
44    }
45}
46#[doc = "Field `NREQ` writer - Pre-divider ratio change request."]
47pub type NreqW<'a, REG> = crate::BitWriter<'a, REG, Nreq>;
48impl<'a, REG> NreqW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Pre-divider ratio change is not requested"]
53    #[inline(always)]
54    pub fn disabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Nreq::Disabled)
56    }
57    #[doc = "Pre-divider ratio change is requested"]
58    #[inline(always)]
59    pub fn enabled(self) -> &'a mut crate::W<REG> {
60        self.variant(Nreq::Enabled)
61    }
62}
63impl R {
64    #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."]
65    #[inline(always)]
66    pub fn ndiv(&self) -> NdivR {
67        NdivR::new((self.bits & 0xff) as u8)
68    }
69    #[doc = "Bit 31 - Pre-divider ratio change request."]
70    #[inline(always)]
71    pub fn nreq(&self) -> NreqR {
72        NreqR::new(((self.bits >> 31) & 1) != 0)
73    }
74}
75#[cfg(feature = "debug")]
76impl core::fmt::Debug for R {
77    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78        f.debug_struct("SPLLNDIV")
79            .field("ndiv", &self.ndiv())
80            .field("nreq", &self.nreq())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:7 - Pre-divider divider ratio (N-divider)."]
86    #[inline(always)]
87    pub fn ndiv(&mut self) -> NdivW<'_, SpllndivSpec> {
88        NdivW::new(self, 0)
89    }
90    #[doc = "Bit 31 - Pre-divider ratio change request."]
91    #[inline(always)]
92    pub fn nreq(&mut self) -> NreqW<'_, SpllndivSpec> {
93        NreqW::new(self, 31)
94    }
95}
96#[doc = "SPLL N Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllndiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllndiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct SpllndivSpec;
98impl crate::RegisterSpec for SpllndivSpec {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`spllndiv::R`](R) reader structure"]
102impl crate::Readable for SpllndivSpec {}
103#[doc = "`write(|w| ..)` method takes [`spllndiv::W`](W) writer structure"]
104impl crate::Writable for SpllndivSpec {
105    type Safety = crate::Unsafe;
106}
107#[doc = "`reset()` method sets SPLLNDIV to value 0x01"]
108impl crate::Resettable for SpllndivSpec {
109    const RESET_VALUE: u32 = 0x01;
110}
mcxa_pac/scg0/spllndiv.rs

mcxa_pac/scg0/
spllndiv.rs
