mcxa_pac/scg0/
sirctcfg.rs

1#[doc = "Register `SIRCTCFG` reader"]
2pub type R = crate::R<SirctcfgSpec>;
3#[doc = "Register `SIRCTCFG` writer"]
4pub type W = crate::W<SirctcfgSpec>;
5#[doc = "Trim Source\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Trimsrc {
10    #[doc = "2: SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."]
11    Sosc = 2,
12}
13impl From<Trimsrc> for u8 {
14    #[inline(always)]
15    fn from(variant: Trimsrc) -> Self {
16        variant as _
17    }
18}
19impl crate::FieldSpec for Trimsrc {
20    type Ux = u8;
21}
22impl crate::IsEnum for Trimsrc {}
23#[doc = "Field `TRIMSRC` reader - Trim Source"]
24pub type TrimsrcR = crate::FieldReader<Trimsrc>;
25impl TrimsrcR {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<Trimsrc> {
29        match self.bits {
30            2 => Some(Trimsrc::Sosc),
31            _ => None,
32        }
33    }
34    #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."]
35    #[inline(always)]
36    pub fn is_sosc(&self) -> bool {
37        *self == Trimsrc::Sosc
38    }
39}
40#[doc = "Field `TRIMSRC` writer - Trim Source"]
41pub type TrimsrcW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trimsrc>;
42impl<'a, REG> TrimsrcW<'a, REG>
43where
44    REG: crate::Writable + crate::RegisterSpec,
45    REG::Ux: From<u8>,
46{
47    #[doc = "SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz."]
48    #[inline(always)]
49    pub fn sosc(self) -> &'a mut crate::W<REG> {
50        self.variant(Trimsrc::Sosc)
51    }
52}
53#[doc = "Field `TRIMDIV` reader - SIRC Trim Pre-divider"]
54pub type TrimdivR = crate::FieldReader;
55#[doc = "Field `TRIMDIV` writer - SIRC Trim Pre-divider"]
56pub type TrimdivW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
57impl R {
58    #[doc = "Bits 0:1 - Trim Source"]
59    #[inline(always)]
60    pub fn trimsrc(&self) -> TrimsrcR {
61        TrimsrcR::new((self.bits & 3) as u8)
62    }
63    #[doc = "Bits 16:22 - SIRC Trim Pre-divider"]
64    #[inline(always)]
65    pub fn trimdiv(&self) -> TrimdivR {
66        TrimdivR::new(((self.bits >> 16) & 0x7f) as u8)
67    }
68}
69#[cfg(feature = "debug")]
70impl core::fmt::Debug for R {
71    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
72        f.debug_struct("SIRCTCFG")
73            .field("trimsrc", &self.trimsrc())
74            .field("trimdiv", &self.trimdiv())
75            .finish()
76    }
77}
78impl W {
79    #[doc = "Bits 0:1 - Trim Source"]
80    #[inline(always)]
81    pub fn trimsrc(&mut self) -> TrimsrcW<'_, SirctcfgSpec> {
82        TrimsrcW::new(self, 0)
83    }
84    #[doc = "Bits 16:22 - SIRC Trim Pre-divider"]
85    #[inline(always)]
86    pub fn trimdiv(&mut self) -> TrimdivW<'_, SirctcfgSpec> {
87        TrimdivW::new(self, 16)
88    }
89}
90#[doc = "SIRC Trim Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
91pub struct SirctcfgSpec;
92impl crate::RegisterSpec for SirctcfgSpec {
93    type Ux = u32;
94}
95#[doc = "`read()` method returns [`sirctcfg::R`](R) reader structure"]
96impl crate::Readable for SirctcfgSpec {}
97#[doc = "`write(|w| ..)` method takes [`sirctcfg::W`](W) writer structure"]
98impl crate::Writable for SirctcfgSpec {
99    type Safety = crate::Unsafe;
100}
101#[doc = "`reset()` method sets SIRCTCFG to value 0"]
102impl crate::Resettable for SirctcfgSpec {}
mcxa_pac/scg0/sirctcfg.rs

mcxa_pac/scg0/
sirctcfg.rs
