mcxa_pac/pkc0/
pkc_int_enable.rs

1#[doc = "Register `PKC_INT_ENABLE` reader"]
2pub type R = crate::R<PkcIntEnableSpec>;
3#[doc = "Field `EN_PDONE` reader - PDONE interrupt enable flag"]
4pub type EnPdoneR = crate::BitReader;
5impl R {
6    #[doc = "Bit 0 - PDONE interrupt enable flag"]
7    #[inline(always)]
8    pub fn en_pdone(&self) -> EnPdoneR {
9        EnPdoneR::new((self.bits & 1) != 0)
10    }
11}
12#[cfg(feature = "debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("PKC_INT_ENABLE")
16            .field("en_pdone", &self.en_pdone())
17            .finish()
18    }
19}
20#[doc = "Interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pkc_int_enable::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct PkcIntEnableSpec;
22impl crate::RegisterSpec for PkcIntEnableSpec {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`pkc_int_enable::R`](R) reader structure"]
26impl crate::Readable for PkcIntEnableSpec {}
27#[doc = "`reset()` method sets PKC_INT_ENABLE to value 0"]
28impl crate::Resettable for PkcIntEnableSpec {}
mcxa_pac/pkc0/pkc_int_enable.rs

mcxa_pac/pkc0/
pkc_int_enable.rs
