mcxa_pac/pkc0/
pkc_access_err_clr.rs

1#[doc = "Register `PKC_ACCESS_ERR_CLR` writer"]
2pub type W = crate::W<PkcAccessErrClrSpec>;
3#[doc = "Field `ERR_CLR` writer - Write 1 to reset PKC_ACCESS_ERR SFR."]
4pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<PkcAccessErrClrSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bit 0 - Write 1 to reset PKC_ACCESS_ERR SFR."]
13    #[inline(always)]
14    pub fn err_clr(&mut self) -> ErrClrW<'_, PkcAccessErrClrSpec> {
15        ErrClrW::new(self, 0)
16    }
17}
18#[doc = "Clear Access Error\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkc_access_err_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct PkcAccessErrClrSpec;
20impl crate::RegisterSpec for PkcAccessErrClrSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`pkc_access_err_clr::W`](W) writer structure"]
24impl crate::Writable for PkcAccessErrClrSpec {
25    type Safety = crate::Unsafe;
26}
27#[doc = "`reset()` method sets PKC_ACCESS_ERR_CLR to value 0"]
28impl crate::Resettable for PkcAccessErrClrSpec {}
mcxa_pac/pkc0/pkc_access_err_clr.rs

mcxa_pac/pkc0/
pkc_access_err_clr.rs
