mcxa_pac/mrcc0/
mrcc_usb0_clksel.rs

1#[doc = "Register `MRCC_USB0_CLKSEL` reader"]
2pub type R = crate::R<MrccUsb0ClkselSpec>;
3#[doc = "Register `MRCC_USB0_CLKSEL` writer"]
4pub type W = crate::W<MrccUsb0ClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 3"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: PLL1_CLK"]
11    ClkrootSpll = 0,
12    #[doc = "1: CLK_48M"]
13    ScgScgFirc48mhzClk = 1,
14    #[doc = "2: CLK_IN"]
15    ClkrootSosc = 2,
16}
17impl From<Mux> for u8 {
18    #[inline(always)]
19    fn from(variant: Mux) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for Mux {
24    type Ux = u8;
25}
26impl crate::IsEnum for Mux {}
27#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
28pub type MuxR = crate::FieldReader<Mux>;
29impl MuxR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<Mux> {
33        match self.bits {
34            0 => Some(Mux::ClkrootSpll),
35            1 => Some(Mux::ScgScgFirc48mhzClk),
36            2 => Some(Mux::ClkrootSosc),
37            _ => None,
38        }
39    }
40    #[doc = "PLL1_CLK"]
41    #[inline(always)]
42    pub fn is_clkroot_spll(&self) -> bool {
43        *self == Mux::ClkrootSpll
44    }
45    #[doc = "CLK_48M"]
46    #[inline(always)]
47    pub fn is_scg_scg_firc_48mhz_clk(&self) -> bool {
48        *self == Mux::ScgScgFirc48mhzClk
49    }
50    #[doc = "CLK_IN"]
51    #[inline(always)]
52    pub fn is_clkroot_sosc(&self) -> bool {
53        *self == Mux::ClkrootSosc
54    }
55}
56#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
57pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>;
58impl<'a, REG> MuxW<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "PLL1_CLK"]
64    #[inline(always)]
65    pub fn clkroot_spll(self) -> &'a mut crate::W<REG> {
66        self.variant(Mux::ClkrootSpll)
67    }
68    #[doc = "CLK_48M"]
69    #[inline(always)]
70    pub fn scg_scg_firc_48mhz_clk(self) -> &'a mut crate::W<REG> {
71        self.variant(Mux::ScgScgFirc48mhzClk)
72    }
73    #[doc = "CLK_IN"]
74    #[inline(always)]
75    pub fn clkroot_sosc(self) -> &'a mut crate::W<REG> {
76        self.variant(Mux::ClkrootSosc)
77    }
78}
79impl R {
80    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
81    #[inline(always)]
82    pub fn mux(&self) -> MuxR {
83        MuxR::new((self.bits & 3) as u8)
84    }
85}
86#[cfg(feature = "debug")]
87impl core::fmt::Debug for R {
88    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
89        f.debug_struct("MRCC_USB0_CLKSEL").field("mux", &self.mux()).finish()
90    }
91}
92impl W {
93    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
94    #[inline(always)]
95    pub fn mux(&mut self) -> MuxW<'_, MrccUsb0ClkselSpec> {
96        MuxW::new(self, 0)
97    }
98}
99#[doc = "USB0 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_usb0_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_usb0_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
100pub struct MrccUsb0ClkselSpec;
101impl crate::RegisterSpec for MrccUsb0ClkselSpec {
102    type Ux = u32;
103}
104#[doc = "`read()` method returns [`mrcc_usb0_clksel::R`](R) reader structure"]
105impl crate::Readable for MrccUsb0ClkselSpec {}
106#[doc = "`write(|w| ..)` method takes [`mrcc_usb0_clksel::W`](W) writer structure"]
107impl crate::Writable for MrccUsb0ClkselSpec {
108    type Safety = crate::Unsafe;
109}
110#[doc = "`reset()` method sets MRCC_USB0_CLKSEL to value 0x03"]
111impl crate::Resettable for MrccUsb0ClkselSpec {
112    const RESET_VALUE: u32 = 0x03;
113}
mcxa_pac/mrcc0/mrcc_usb0_clksel.rs

mcxa_pac/mrcc0/
mrcc_usb0_clksel.rs
