mcxa_pac/mrcc0/
mrcc_glb_cc0_clr.rs

1#[doc = "Register `MRCC_GLB_CC0_CLR` writer"]
2pub type W = crate::W<MrccGlbCc0ClrSpec>;
3#[doc = "Field `DATA` writer - Data array value, refer to corresponding position in MRCC_GLB_CCn."]
4pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<MrccGlbCc0ClrSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:31 - Data array value, refer to corresponding position in MRCC_GLB_CCn."]
13    #[inline(always)]
14    pub fn data(&mut self) -> DataW<'_, MrccGlbCc0ClrSpec> {
15        DataW::new(self, 0)
16    }
17}
18#[doc = "AHB Clock Control Clear 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_cc0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct MrccGlbCc0ClrSpec;
20impl crate::RegisterSpec for MrccGlbCc0ClrSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`mrcc_glb_cc0_clr::W`](W) writer structure"]
24impl crate::Writable for MrccGlbCc0ClrSpec {
25    type Safety = crate::Unsafe;
26}
27#[doc = "`reset()` method sets MRCC_GLB_CC0_CLR to value 0x0001_0000"]
28impl crate::Resettable for MrccGlbCc0ClrSpec {
29    const RESET_VALUE: u32 = 0x0001_0000;
30}
mcxa_pac/mrcc0/mrcc_glb_cc0_clr.rs

mcxa_pac/mrcc0/
mrcc_glb_cc0_clr.rs
