1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Parity Type\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Pt {
9 #[doc = "0: Even parity"]
10 Even = 0,
11 #[doc = "1: Odd parity"]
12 Odd = 1,
13}
14impl From<Pt> for bool {
15 #[inline(always)]
16 fn from(variant: Pt) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `PT` reader - Parity Type"]
21pub type PtR = crate::BitReader<Pt>;
22impl PtR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Pt {
26 match self.bits {
27 false => Pt::Even,
28 true => Pt::Odd,
29 }
30 }
31 #[doc = "Even parity"]
32 #[inline(always)]
33 pub fn is_even(&self) -> bool {
34 *self == Pt::Even
35 }
36 #[doc = "Odd parity"]
37 #[inline(always)]
38 pub fn is_odd(&self) -> bool {
39 *self == Pt::Odd
40 }
41}
42#[doc = "Field `PT` writer - Parity Type"]
43pub type PtW<'a, REG> = crate::BitWriter<'a, REG, Pt>;
44impl<'a, REG> PtW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Even parity"]
49 #[inline(always)]
50 pub fn even(self) -> &'a mut crate::W<REG> {
51 self.variant(Pt::Even)
52 }
53 #[doc = "Odd parity"]
54 #[inline(always)]
55 pub fn odd(self) -> &'a mut crate::W<REG> {
56 self.variant(Pt::Odd)
57 }
58}
59#[doc = "Parity Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Pe {
63 #[doc = "0: Disable"]
64 Disabled = 0,
65 #[doc = "1: Enable"]
66 Enabled = 1,
67}
68impl From<Pe> for bool {
69 #[inline(always)]
70 fn from(variant: Pe) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `PE` reader - Parity Enable"]
75pub type PeR = crate::BitReader<Pe>;
76impl PeR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Pe {
80 match self.bits {
81 false => Pe::Disabled,
82 true => Pe::Enabled,
83 }
84 }
85 #[doc = "Disable"]
86 #[inline(always)]
87 pub fn is_disabled(&self) -> bool {
88 *self == Pe::Disabled
89 }
90 #[doc = "Enable"]
91 #[inline(always)]
92 pub fn is_enabled(&self) -> bool {
93 *self == Pe::Enabled
94 }
95}
96#[doc = "Field `PE` writer - Parity Enable"]
97pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>;
98impl<'a, REG> PeW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Disable"]
103 #[inline(always)]
104 pub fn disabled(self) -> &'a mut crate::W<REG> {
105 self.variant(Pe::Disabled)
106 }
107 #[doc = "Enable"]
108 #[inline(always)]
109 pub fn enabled(self) -> &'a mut crate::W<REG> {
110 self.variant(Pe::Enabled)
111 }
112}
113#[doc = "Idle Line Type Select\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Ilt {
117 #[doc = "0: After the start bit"]
118 FromStart = 0,
119 #[doc = "1: After the stop bit"]
120 FromStop = 1,
121}
122impl From<Ilt> for bool {
123 #[inline(always)]
124 fn from(variant: Ilt) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `ILT` reader - Idle Line Type Select"]
129pub type IltR = crate::BitReader<Ilt>;
130impl IltR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Ilt {
134 match self.bits {
135 false => Ilt::FromStart,
136 true => Ilt::FromStop,
137 }
138 }
139 #[doc = "After the start bit"]
140 #[inline(always)]
141 pub fn is_from_start(&self) -> bool {
142 *self == Ilt::FromStart
143 }
144 #[doc = "After the stop bit"]
145 #[inline(always)]
146 pub fn is_from_stop(&self) -> bool {
147 *self == Ilt::FromStop
148 }
149}
150#[doc = "Field `ILT` writer - Idle Line Type Select"]
151pub type IltW<'a, REG> = crate::BitWriter<'a, REG, Ilt>;
152impl<'a, REG> IltW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "After the start bit"]
157 #[inline(always)]
158 pub fn from_start(self) -> &'a mut crate::W<REG> {
159 self.variant(Ilt::FromStart)
160 }
161 #[doc = "After the stop bit"]
162 #[inline(always)]
163 pub fn from_stop(self) -> &'a mut crate::W<REG> {
164 self.variant(Ilt::FromStop)
165 }
166}
167#[doc = "Receiver Wake-Up Method Select\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Wake {
171 #[doc = "0: Idle"]
172 Idle = 0,
173 #[doc = "1: Mark"]
174 Mark = 1,
175}
176impl From<Wake> for bool {
177 #[inline(always)]
178 fn from(variant: Wake) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `WAKE` reader - Receiver Wake-Up Method Select"]
183pub type WakeR = crate::BitReader<Wake>;
184impl WakeR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> Wake {
188 match self.bits {
189 false => Wake::Idle,
190 true => Wake::Mark,
191 }
192 }
193 #[doc = "Idle"]
194 #[inline(always)]
195 pub fn is_idle(&self) -> bool {
196 *self == Wake::Idle
197 }
198 #[doc = "Mark"]
199 #[inline(always)]
200 pub fn is_mark(&self) -> bool {
201 *self == Wake::Mark
202 }
203}
204#[doc = "Field `WAKE` writer - Receiver Wake-Up Method Select"]
205pub type WakeW<'a, REG> = crate::BitWriter<'a, REG, Wake>;
206impl<'a, REG> WakeW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Idle"]
211 #[inline(always)]
212 pub fn idle(self) -> &'a mut crate::W<REG> {
213 self.variant(Wake::Idle)
214 }
215 #[doc = "Mark"]
216 #[inline(always)]
217 pub fn mark(self) -> &'a mut crate::W<REG> {
218 self.variant(Wake::Mark)
219 }
220}
221#[doc = "9-Bit Or 8-Bit Mode Select\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum M {
225 #[doc = "0: 8-bit"]
226 Data8 = 0,
227 #[doc = "1: 9-bit"]
228 Data9 = 1,
229}
230impl From<M> for bool {
231 #[inline(always)]
232 fn from(variant: M) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `M` reader - 9-Bit Or 8-Bit Mode Select"]
237pub type MR = crate::BitReader<M>;
238impl MR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> M {
242 match self.bits {
243 false => M::Data8,
244 true => M::Data9,
245 }
246 }
247 #[doc = "8-bit"]
248 #[inline(always)]
249 pub fn is_data8(&self) -> bool {
250 *self == M::Data8
251 }
252 #[doc = "9-bit"]
253 #[inline(always)]
254 pub fn is_data9(&self) -> bool {
255 *self == M::Data9
256 }
257}
258#[doc = "Field `M` writer - 9-Bit Or 8-Bit Mode Select"]
259pub type MW<'a, REG> = crate::BitWriter<'a, REG, M>;
260impl<'a, REG> MW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "8-bit"]
265 #[inline(always)]
266 pub fn data8(self) -> &'a mut crate::W<REG> {
267 self.variant(M::Data8)
268 }
269 #[doc = "9-bit"]
270 #[inline(always)]
271 pub fn data9(self) -> &'a mut crate::W<REG> {
272 self.variant(M::Data9)
273 }
274}
275#[doc = "Receiver Source Select\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Rsrc {
279 #[doc = "0: Internal Loopback mode"]
280 NoEffect = 0,
281 #[doc = "1: Single-wire mode"]
282 Onewire = 1,
283}
284impl From<Rsrc> for bool {
285 #[inline(always)]
286 fn from(variant: Rsrc) -> Self {
287 variant as u8 != 0
288 }
289}
290#[doc = "Field `RSRC` reader - Receiver Source Select"]
291pub type RsrcR = crate::BitReader<Rsrc>;
292impl RsrcR {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub const fn variant(&self) -> Rsrc {
296 match self.bits {
297 false => Rsrc::NoEffect,
298 true => Rsrc::Onewire,
299 }
300 }
301 #[doc = "Internal Loopback mode"]
302 #[inline(always)]
303 pub fn is_no_effect(&self) -> bool {
304 *self == Rsrc::NoEffect
305 }
306 #[doc = "Single-wire mode"]
307 #[inline(always)]
308 pub fn is_onewire(&self) -> bool {
309 *self == Rsrc::Onewire
310 }
311}
312#[doc = "Field `RSRC` writer - Receiver Source Select"]
313pub type RsrcW<'a, REG> = crate::BitWriter<'a, REG, Rsrc>;
314impl<'a, REG> RsrcW<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317{
318 #[doc = "Internal Loopback mode"]
319 #[inline(always)]
320 pub fn no_effect(self) -> &'a mut crate::W<REG> {
321 self.variant(Rsrc::NoEffect)
322 }
323 #[doc = "Single-wire mode"]
324 #[inline(always)]
325 pub fn onewire(self) -> &'a mut crate::W<REG> {
326 self.variant(Rsrc::Onewire)
327 }
328}
329#[doc = "Doze Mode\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Dozeen {
333 #[doc = "0: Enable"]
334 Enabled = 0,
335 #[doc = "1: Disable"]
336 Disabled = 1,
337}
338impl From<Dozeen> for bool {
339 #[inline(always)]
340 fn from(variant: Dozeen) -> Self {
341 variant as u8 != 0
342 }
343}
344#[doc = "Field `DOZEEN` reader - Doze Mode"]
345pub type DozeenR = crate::BitReader<Dozeen>;
346impl DozeenR {
347 #[doc = "Get enumerated values variant"]
348 #[inline(always)]
349 pub const fn variant(&self) -> Dozeen {
350 match self.bits {
351 false => Dozeen::Enabled,
352 true => Dozeen::Disabled,
353 }
354 }
355 #[doc = "Enable"]
356 #[inline(always)]
357 pub fn is_enabled(&self) -> bool {
358 *self == Dozeen::Enabled
359 }
360 #[doc = "Disable"]
361 #[inline(always)]
362 pub fn is_disabled(&self) -> bool {
363 *self == Dozeen::Disabled
364 }
365}
366#[doc = "Field `DOZEEN` writer - Doze Mode"]
367pub type DozeenW<'a, REG> = crate::BitWriter<'a, REG, Dozeen>;
368impl<'a, REG> DozeenW<'a, REG>
369where
370 REG: crate::Writable + crate::RegisterSpec,
371{
372 #[doc = "Enable"]
373 #[inline(always)]
374 pub fn enabled(self) -> &'a mut crate::W<REG> {
375 self.variant(Dozeen::Enabled)
376 }
377 #[doc = "Disable"]
378 #[inline(always)]
379 pub fn disabled(self) -> &'a mut crate::W<REG> {
380 self.variant(Dozeen::Disabled)
381 }
382}
383#[doc = "Loop Mode Select\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Loops {
387 #[doc = "0: Normal operation: RXD and TXD use separate pins"]
388 Noffect = 0,
389 #[doc = "1: Loop mode or Single-Wire mode"]
390 Loopback = 1,
391}
392impl From<Loops> for bool {
393 #[inline(always)]
394 fn from(variant: Loops) -> Self {
395 variant as u8 != 0
396 }
397}
398#[doc = "Field `LOOPS` reader - Loop Mode Select"]
399pub type LoopsR = crate::BitReader<Loops>;
400impl LoopsR {
401 #[doc = "Get enumerated values variant"]
402 #[inline(always)]
403 pub const fn variant(&self) -> Loops {
404 match self.bits {
405 false => Loops::Noffect,
406 true => Loops::Loopback,
407 }
408 }
409 #[doc = "Normal operation: RXD and TXD use separate pins"]
410 #[inline(always)]
411 pub fn is_noffect(&self) -> bool {
412 *self == Loops::Noffect
413 }
414 #[doc = "Loop mode or Single-Wire mode"]
415 #[inline(always)]
416 pub fn is_loopback(&self) -> bool {
417 *self == Loops::Loopback
418 }
419}
420#[doc = "Field `LOOPS` writer - Loop Mode Select"]
421pub type LoopsW<'a, REG> = crate::BitWriter<'a, REG, Loops>;
422impl<'a, REG> LoopsW<'a, REG>
423where
424 REG: crate::Writable + crate::RegisterSpec,
425{
426 #[doc = "Normal operation: RXD and TXD use separate pins"]
427 #[inline(always)]
428 pub fn noffect(self) -> &'a mut crate::W<REG> {
429 self.variant(Loops::Noffect)
430 }
431 #[doc = "Loop mode or Single-Wire mode"]
432 #[inline(always)]
433 pub fn loopback(self) -> &'a mut crate::W<REG> {
434 self.variant(Loops::Loopback)
435 }
436}
437#[doc = "Idle Configuration\n\nValue on reset: 0"]
438#[cfg_attr(feature = "defmt", derive(defmt::Format))]
439#[derive(Clone, Copy, Debug, PartialEq, Eq)]
440#[repr(u8)]
441pub enum Idlecfg {
442 #[doc = "0: 1"]
443 Idle1 = 0,
444 #[doc = "1: 2"]
445 Idle2 = 1,
446 #[doc = "2: 4"]
447 Idle4 = 2,
448 #[doc = "3: 8"]
449 Idle8 = 3,
450 #[doc = "4: 16"]
451 Idle16 = 4,
452 #[doc = "5: 32"]
453 Idle32 = 5,
454 #[doc = "6: 64"]
455 Idle64 = 6,
456 #[doc = "7: 128"]
457 Idle128 = 7,
458}
459impl From<Idlecfg> for u8 {
460 #[inline(always)]
461 fn from(variant: Idlecfg) -> Self {
462 variant as _
463 }
464}
465impl crate::FieldSpec for Idlecfg {
466 type Ux = u8;
467}
468impl crate::IsEnum for Idlecfg {}
469#[doc = "Field `IDLECFG` reader - Idle Configuration"]
470pub type IdlecfgR = crate::FieldReader<Idlecfg>;
471impl IdlecfgR {
472 #[doc = "Get enumerated values variant"]
473 #[inline(always)]
474 pub const fn variant(&self) -> Idlecfg {
475 match self.bits {
476 0 => Idlecfg::Idle1,
477 1 => Idlecfg::Idle2,
478 2 => Idlecfg::Idle4,
479 3 => Idlecfg::Idle8,
480 4 => Idlecfg::Idle16,
481 5 => Idlecfg::Idle32,
482 6 => Idlecfg::Idle64,
483 7 => Idlecfg::Idle128,
484 _ => unreachable!(),
485 }
486 }
487 #[doc = "1"]
488 #[inline(always)]
489 pub fn is_idle_1(&self) -> bool {
490 *self == Idlecfg::Idle1
491 }
492 #[doc = "2"]
493 #[inline(always)]
494 pub fn is_idle_2(&self) -> bool {
495 *self == Idlecfg::Idle2
496 }
497 #[doc = "4"]
498 #[inline(always)]
499 pub fn is_idle_4(&self) -> bool {
500 *self == Idlecfg::Idle4
501 }
502 #[doc = "8"]
503 #[inline(always)]
504 pub fn is_idle_8(&self) -> bool {
505 *self == Idlecfg::Idle8
506 }
507 #[doc = "16"]
508 #[inline(always)]
509 pub fn is_idle_16(&self) -> bool {
510 *self == Idlecfg::Idle16
511 }
512 #[doc = "32"]
513 #[inline(always)]
514 pub fn is_idle_32(&self) -> bool {
515 *self == Idlecfg::Idle32
516 }
517 #[doc = "64"]
518 #[inline(always)]
519 pub fn is_idle_64(&self) -> bool {
520 *self == Idlecfg::Idle64
521 }
522 #[doc = "128"]
523 #[inline(always)]
524 pub fn is_idle_128(&self) -> bool {
525 *self == Idlecfg::Idle128
526 }
527}
528#[doc = "Field `IDLECFG` writer - Idle Configuration"]
529pub type IdlecfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Idlecfg, crate::Safe>;
530impl<'a, REG> IdlecfgW<'a, REG>
531where
532 REG: crate::Writable + crate::RegisterSpec,
533 REG::Ux: From<u8>,
534{
535 #[doc = "1"]
536 #[inline(always)]
537 pub fn idle_1(self) -> &'a mut crate::W<REG> {
538 self.variant(Idlecfg::Idle1)
539 }
540 #[doc = "2"]
541 #[inline(always)]
542 pub fn idle_2(self) -> &'a mut crate::W<REG> {
543 self.variant(Idlecfg::Idle2)
544 }
545 #[doc = "4"]
546 #[inline(always)]
547 pub fn idle_4(self) -> &'a mut crate::W<REG> {
548 self.variant(Idlecfg::Idle4)
549 }
550 #[doc = "8"]
551 #[inline(always)]
552 pub fn idle_8(self) -> &'a mut crate::W<REG> {
553 self.variant(Idlecfg::Idle8)
554 }
555 #[doc = "16"]
556 #[inline(always)]
557 pub fn idle_16(self) -> &'a mut crate::W<REG> {
558 self.variant(Idlecfg::Idle16)
559 }
560 #[doc = "32"]
561 #[inline(always)]
562 pub fn idle_32(self) -> &'a mut crate::W<REG> {
563 self.variant(Idlecfg::Idle32)
564 }
565 #[doc = "64"]
566 #[inline(always)]
567 pub fn idle_64(self) -> &'a mut crate::W<REG> {
568 self.variant(Idlecfg::Idle64)
569 }
570 #[doc = "128"]
571 #[inline(always)]
572 pub fn idle_128(self) -> &'a mut crate::W<REG> {
573 self.variant(Idlecfg::Idle128)
574 }
575}
576#[doc = "7-Bit Mode Select\n\nValue on reset: 0"]
577#[cfg_attr(feature = "defmt", derive(defmt::Format))]
578#[derive(Clone, Copy, Debug, PartialEq, Eq)]
579pub enum M7 {
580 #[doc = "0: 8-bit to 10-bit"]
581 NoEffect = 0,
582 #[doc = "1: 7-bit"]
583 Data7 = 1,
584}
585impl From<M7> for bool {
586 #[inline(always)]
587 fn from(variant: M7) -> Self {
588 variant as u8 != 0
589 }
590}
591#[doc = "Field `M7` reader - 7-Bit Mode Select"]
592pub type M7R = crate::BitReader<M7>;
593impl M7R {
594 #[doc = "Get enumerated values variant"]
595 #[inline(always)]
596 pub const fn variant(&self) -> M7 {
597 match self.bits {
598 false => M7::NoEffect,
599 true => M7::Data7,
600 }
601 }
602 #[doc = "8-bit to 10-bit"]
603 #[inline(always)]
604 pub fn is_no_effect(&self) -> bool {
605 *self == M7::NoEffect
606 }
607 #[doc = "7-bit"]
608 #[inline(always)]
609 pub fn is_data7(&self) -> bool {
610 *self == M7::Data7
611 }
612}
613#[doc = "Field `M7` writer - 7-Bit Mode Select"]
614pub type M7W<'a, REG> = crate::BitWriter<'a, REG, M7>;
615impl<'a, REG> M7W<'a, REG>
616where
617 REG: crate::Writable + crate::RegisterSpec,
618{
619 #[doc = "8-bit to 10-bit"]
620 #[inline(always)]
621 pub fn no_effect(self) -> &'a mut crate::W<REG> {
622 self.variant(M7::NoEffect)
623 }
624 #[doc = "7-bit"]
625 #[inline(always)]
626 pub fn data7(self) -> &'a mut crate::W<REG> {
627 self.variant(M7::Data7)
628 }
629}
630#[doc = "TXD and RXD Pin Swap\n\nValue on reset: 0"]
631#[cfg_attr(feature = "defmt", derive(defmt::Format))]
632#[derive(Clone, Copy, Debug, PartialEq, Eq)]
633pub enum Swap {
634 #[doc = "0: Use the standard way"]
635 Standard = 0,
636 #[doc = "1: Swap"]
637 Swap = 1,
638}
639impl From<Swap> for bool {
640 #[inline(always)]
641 fn from(variant: Swap) -> Self {
642 variant as u8 != 0
643 }
644}
645#[doc = "Field `SWAP` reader - TXD and RXD Pin Swap"]
646pub type SwapR = crate::BitReader<Swap>;
647impl SwapR {
648 #[doc = "Get enumerated values variant"]
649 #[inline(always)]
650 pub const fn variant(&self) -> Swap {
651 match self.bits {
652 false => Swap::Standard,
653 true => Swap::Swap,
654 }
655 }
656 #[doc = "Use the standard way"]
657 #[inline(always)]
658 pub fn is_standard(&self) -> bool {
659 *self == Swap::Standard
660 }
661 #[doc = "Swap"]
662 #[inline(always)]
663 pub fn is_swap(&self) -> bool {
664 *self == Swap::Swap
665 }
666}
667#[doc = "Field `SWAP` writer - TXD and RXD Pin Swap"]
668pub type SwapW<'a, REG> = crate::BitWriter<'a, REG, Swap>;
669impl<'a, REG> SwapW<'a, REG>
670where
671 REG: crate::Writable + crate::RegisterSpec,
672{
673 #[doc = "Use the standard way"]
674 #[inline(always)]
675 pub fn standard(self) -> &'a mut crate::W<REG> {
676 self.variant(Swap::Standard)
677 }
678 #[doc = "Swap"]
679 #[inline(always)]
680 pub fn swap(self) -> &'a mut crate::W<REG> {
681 self.variant(Swap::Swap)
682 }
683}
684#[doc = "Match 2 (MA2F) Interrupt Enable\n\nValue on reset: 0"]
685#[cfg_attr(feature = "defmt", derive(defmt::Format))]
686#[derive(Clone, Copy, Debug, PartialEq, Eq)]
687pub enum Ma2ie {
688 #[doc = "0: Disable"]
689 Disabled = 0,
690 #[doc = "1: Enable"]
691 Enabled = 1,
692}
693impl From<Ma2ie> for bool {
694 #[inline(always)]
695 fn from(variant: Ma2ie) -> Self {
696 variant as u8 != 0
697 }
698}
699#[doc = "Field `MA2IE` reader - Match 2 (MA2F) Interrupt Enable"]
700pub type Ma2ieR = crate::BitReader<Ma2ie>;
701impl Ma2ieR {
702 #[doc = "Get enumerated values variant"]
703 #[inline(always)]
704 pub const fn variant(&self) -> Ma2ie {
705 match self.bits {
706 false => Ma2ie::Disabled,
707 true => Ma2ie::Enabled,
708 }
709 }
710 #[doc = "Disable"]
711 #[inline(always)]
712 pub fn is_disabled(&self) -> bool {
713 *self == Ma2ie::Disabled
714 }
715 #[doc = "Enable"]
716 #[inline(always)]
717 pub fn is_enabled(&self) -> bool {
718 *self == Ma2ie::Enabled
719 }
720}
721#[doc = "Field `MA2IE` writer - Match 2 (MA2F) Interrupt Enable"]
722pub type Ma2ieW<'a, REG> = crate::BitWriter<'a, REG, Ma2ie>;
723impl<'a, REG> Ma2ieW<'a, REG>
724where
725 REG: crate::Writable + crate::RegisterSpec,
726{
727 #[doc = "Disable"]
728 #[inline(always)]
729 pub fn disabled(self) -> &'a mut crate::W<REG> {
730 self.variant(Ma2ie::Disabled)
731 }
732 #[doc = "Enable"]
733 #[inline(always)]
734 pub fn enabled(self) -> &'a mut crate::W<REG> {
735 self.variant(Ma2ie::Enabled)
736 }
737}
738#[doc = "Match 1 (MA1F) Interrupt Enable\n\nValue on reset: 0"]
739#[cfg_attr(feature = "defmt", derive(defmt::Format))]
740#[derive(Clone, Copy, Debug, PartialEq, Eq)]
741pub enum Ma1ie {
742 #[doc = "0: Disable"]
743 Disabled = 0,
744 #[doc = "1: Enable"]
745 Enabled = 1,
746}
747impl From<Ma1ie> for bool {
748 #[inline(always)]
749 fn from(variant: Ma1ie) -> Self {
750 variant as u8 != 0
751 }
752}
753#[doc = "Field `MA1IE` reader - Match 1 (MA1F) Interrupt Enable"]
754pub type Ma1ieR = crate::BitReader<Ma1ie>;
755impl Ma1ieR {
756 #[doc = "Get enumerated values variant"]
757 #[inline(always)]
758 pub const fn variant(&self) -> Ma1ie {
759 match self.bits {
760 false => Ma1ie::Disabled,
761 true => Ma1ie::Enabled,
762 }
763 }
764 #[doc = "Disable"]
765 #[inline(always)]
766 pub fn is_disabled(&self) -> bool {
767 *self == Ma1ie::Disabled
768 }
769 #[doc = "Enable"]
770 #[inline(always)]
771 pub fn is_enabled(&self) -> bool {
772 *self == Ma1ie::Enabled
773 }
774}
775#[doc = "Field `MA1IE` writer - Match 1 (MA1F) Interrupt Enable"]
776pub type Ma1ieW<'a, REG> = crate::BitWriter<'a, REG, Ma1ie>;
777impl<'a, REG> Ma1ieW<'a, REG>
778where
779 REG: crate::Writable + crate::RegisterSpec,
780{
781 #[doc = "Disable"]
782 #[inline(always)]
783 pub fn disabled(self) -> &'a mut crate::W<REG> {
784 self.variant(Ma1ie::Disabled)
785 }
786 #[doc = "Enable"]
787 #[inline(always)]
788 pub fn enabled(self) -> &'a mut crate::W<REG> {
789 self.variant(Ma1ie::Enabled)
790 }
791}
792#[doc = "Send Break\n\nValue on reset: 0"]
793#[cfg_attr(feature = "defmt", derive(defmt::Format))]
794#[derive(Clone, Copy, Debug, PartialEq, Eq)]
795pub enum Sbk {
796 #[doc = "0: Normal transmitter operation"]
797 NoEffect = 0,
798 #[doc = "1: Queue break character(s) to be sent"]
799 TxBreak = 1,
800}
801impl From<Sbk> for bool {
802 #[inline(always)]
803 fn from(variant: Sbk) -> Self {
804 variant as u8 != 0
805 }
806}
807#[doc = "Field `SBK` reader - Send Break"]
808pub type SbkR = crate::BitReader<Sbk>;
809impl SbkR {
810 #[doc = "Get enumerated values variant"]
811 #[inline(always)]
812 pub const fn variant(&self) -> Sbk {
813 match self.bits {
814 false => Sbk::NoEffect,
815 true => Sbk::TxBreak,
816 }
817 }
818 #[doc = "Normal transmitter operation"]
819 #[inline(always)]
820 pub fn is_no_effect(&self) -> bool {
821 *self == Sbk::NoEffect
822 }
823 #[doc = "Queue break character(s) to be sent"]
824 #[inline(always)]
825 pub fn is_tx_break(&self) -> bool {
826 *self == Sbk::TxBreak
827 }
828}
829#[doc = "Field `SBK` writer - Send Break"]
830pub type SbkW<'a, REG> = crate::BitWriter<'a, REG, Sbk>;
831impl<'a, REG> SbkW<'a, REG>
832where
833 REG: crate::Writable + crate::RegisterSpec,
834{
835 #[doc = "Normal transmitter operation"]
836 #[inline(always)]
837 pub fn no_effect(self) -> &'a mut crate::W<REG> {
838 self.variant(Sbk::NoEffect)
839 }
840 #[doc = "Queue break character(s) to be sent"]
841 #[inline(always)]
842 pub fn tx_break(self) -> &'a mut crate::W<REG> {
843 self.variant(Sbk::TxBreak)
844 }
845}
846#[doc = "Receiver Wake-Up Control\n\nValue on reset: 0"]
847#[cfg_attr(feature = "defmt", derive(defmt::Format))]
848#[derive(Clone, Copy, Debug, PartialEq, Eq)]
849pub enum Rwu {
850 #[doc = "0: Normal receiver operation"]
851 NoEffect = 0,
852 #[doc = "1: LPUART receiver in standby, waiting for a wake-up condition"]
853 RxWakeup = 1,
854}
855impl From<Rwu> for bool {
856 #[inline(always)]
857 fn from(variant: Rwu) -> Self {
858 variant as u8 != 0
859 }
860}
861#[doc = "Field `RWU` reader - Receiver Wake-Up Control"]
862pub type RwuR = crate::BitReader<Rwu>;
863impl RwuR {
864 #[doc = "Get enumerated values variant"]
865 #[inline(always)]
866 pub const fn variant(&self) -> Rwu {
867 match self.bits {
868 false => Rwu::NoEffect,
869 true => Rwu::RxWakeup,
870 }
871 }
872 #[doc = "Normal receiver operation"]
873 #[inline(always)]
874 pub fn is_no_effect(&self) -> bool {
875 *self == Rwu::NoEffect
876 }
877 #[doc = "LPUART receiver in standby, waiting for a wake-up condition"]
878 #[inline(always)]
879 pub fn is_rx_wakeup(&self) -> bool {
880 *self == Rwu::RxWakeup
881 }
882}
883#[doc = "Field `RWU` writer - Receiver Wake-Up Control"]
884pub type RwuW<'a, REG> = crate::BitWriter<'a, REG, Rwu>;
885impl<'a, REG> RwuW<'a, REG>
886where
887 REG: crate::Writable + crate::RegisterSpec,
888{
889 #[doc = "Normal receiver operation"]
890 #[inline(always)]
891 pub fn no_effect(self) -> &'a mut crate::W<REG> {
892 self.variant(Rwu::NoEffect)
893 }
894 #[doc = "LPUART receiver in standby, waiting for a wake-up condition"]
895 #[inline(always)]
896 pub fn rx_wakeup(self) -> &'a mut crate::W<REG> {
897 self.variant(Rwu::RxWakeup)
898 }
899}
900#[doc = "Receiver Enable\n\nValue on reset: 0"]
901#[cfg_attr(feature = "defmt", derive(defmt::Format))]
902#[derive(Clone, Copy, Debug, PartialEq, Eq)]
903pub enum Re {
904 #[doc = "0: Disable"]
905 Disabled = 0,
906 #[doc = "1: Enable"]
907 Enabled = 1,
908}
909impl From<Re> for bool {
910 #[inline(always)]
911 fn from(variant: Re) -> Self {
912 variant as u8 != 0
913 }
914}
915#[doc = "Field `RE` reader - Receiver Enable"]
916pub type ReR = crate::BitReader<Re>;
917impl ReR {
918 #[doc = "Get enumerated values variant"]
919 #[inline(always)]
920 pub const fn variant(&self) -> Re {
921 match self.bits {
922 false => Re::Disabled,
923 true => Re::Enabled,
924 }
925 }
926 #[doc = "Disable"]
927 #[inline(always)]
928 pub fn is_disabled(&self) -> bool {
929 *self == Re::Disabled
930 }
931 #[doc = "Enable"]
932 #[inline(always)]
933 pub fn is_enabled(&self) -> bool {
934 *self == Re::Enabled
935 }
936}
937#[doc = "Field `RE` writer - Receiver Enable"]
938pub type ReW<'a, REG> = crate::BitWriter<'a, REG, Re>;
939impl<'a, REG> ReW<'a, REG>
940where
941 REG: crate::Writable + crate::RegisterSpec,
942{
943 #[doc = "Disable"]
944 #[inline(always)]
945 pub fn disabled(self) -> &'a mut crate::W<REG> {
946 self.variant(Re::Disabled)
947 }
948 #[doc = "Enable"]
949 #[inline(always)]
950 pub fn enabled(self) -> &'a mut crate::W<REG> {
951 self.variant(Re::Enabled)
952 }
953}
954#[doc = "Transmitter Enable\n\nValue on reset: 0"]
955#[cfg_attr(feature = "defmt", derive(defmt::Format))]
956#[derive(Clone, Copy, Debug, PartialEq, Eq)]
957pub enum Te {
958 #[doc = "0: Disable"]
959 Disabled = 0,
960 #[doc = "1: Enable"]
961 Enabled = 1,
962}
963impl From<Te> for bool {
964 #[inline(always)]
965 fn from(variant: Te) -> Self {
966 variant as u8 != 0
967 }
968}
969#[doc = "Field `TE` reader - Transmitter Enable"]
970pub type TeR = crate::BitReader<Te>;
971impl TeR {
972 #[doc = "Get enumerated values variant"]
973 #[inline(always)]
974 pub const fn variant(&self) -> Te {
975 match self.bits {
976 false => Te::Disabled,
977 true => Te::Enabled,
978 }
979 }
980 #[doc = "Disable"]
981 #[inline(always)]
982 pub fn is_disabled(&self) -> bool {
983 *self == Te::Disabled
984 }
985 #[doc = "Enable"]
986 #[inline(always)]
987 pub fn is_enabled(&self) -> bool {
988 *self == Te::Enabled
989 }
990}
991#[doc = "Field `TE` writer - Transmitter Enable"]
992pub type TeW<'a, REG> = crate::BitWriter<'a, REG, Te>;
993impl<'a, REG> TeW<'a, REG>
994where
995 REG: crate::Writable + crate::RegisterSpec,
996{
997 #[doc = "Disable"]
998 #[inline(always)]
999 pub fn disabled(self) -> &'a mut crate::W<REG> {
1000 self.variant(Te::Disabled)
1001 }
1002 #[doc = "Enable"]
1003 #[inline(always)]
1004 pub fn enabled(self) -> &'a mut crate::W<REG> {
1005 self.variant(Te::Enabled)
1006 }
1007}
1008#[doc = "Idle Line Interrupt Enable\n\nValue on reset: 0"]
1009#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1010#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1011pub enum Ilie {
1012 #[doc = "0: Disable"]
1013 Disabled = 0,
1014 #[doc = "1: Enable"]
1015 Enabled = 1,
1016}
1017impl From<Ilie> for bool {
1018 #[inline(always)]
1019 fn from(variant: Ilie) -> Self {
1020 variant as u8 != 0
1021 }
1022}
1023#[doc = "Field `ILIE` reader - Idle Line Interrupt Enable"]
1024pub type IlieR = crate::BitReader<Ilie>;
1025impl IlieR {
1026 #[doc = "Get enumerated values variant"]
1027 #[inline(always)]
1028 pub const fn variant(&self) -> Ilie {
1029 match self.bits {
1030 false => Ilie::Disabled,
1031 true => Ilie::Enabled,
1032 }
1033 }
1034 #[doc = "Disable"]
1035 #[inline(always)]
1036 pub fn is_disabled(&self) -> bool {
1037 *self == Ilie::Disabled
1038 }
1039 #[doc = "Enable"]
1040 #[inline(always)]
1041 pub fn is_enabled(&self) -> bool {
1042 *self == Ilie::Enabled
1043 }
1044}
1045#[doc = "Field `ILIE` writer - Idle Line Interrupt Enable"]
1046pub type IlieW<'a, REG> = crate::BitWriter<'a, REG, Ilie>;
1047impl<'a, REG> IlieW<'a, REG>
1048where
1049 REG: crate::Writable + crate::RegisterSpec,
1050{
1051 #[doc = "Disable"]
1052 #[inline(always)]
1053 pub fn disabled(self) -> &'a mut crate::W<REG> {
1054 self.variant(Ilie::Disabled)
1055 }
1056 #[doc = "Enable"]
1057 #[inline(always)]
1058 pub fn enabled(self) -> &'a mut crate::W<REG> {
1059 self.variant(Ilie::Enabled)
1060 }
1061}
1062#[doc = "Receiver Interrupt Enable\n\nValue on reset: 0"]
1063#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1064#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1065pub enum Rie {
1066 #[doc = "0: Disable"]
1067 Disabled = 0,
1068 #[doc = "1: Enable"]
1069 Enabled = 1,
1070}
1071impl From<Rie> for bool {
1072 #[inline(always)]
1073 fn from(variant: Rie) -> Self {
1074 variant as u8 != 0
1075 }
1076}
1077#[doc = "Field `RIE` reader - Receiver Interrupt Enable"]
1078pub type RieR = crate::BitReader<Rie>;
1079impl RieR {
1080 #[doc = "Get enumerated values variant"]
1081 #[inline(always)]
1082 pub const fn variant(&self) -> Rie {
1083 match self.bits {
1084 false => Rie::Disabled,
1085 true => Rie::Enabled,
1086 }
1087 }
1088 #[doc = "Disable"]
1089 #[inline(always)]
1090 pub fn is_disabled(&self) -> bool {
1091 *self == Rie::Disabled
1092 }
1093 #[doc = "Enable"]
1094 #[inline(always)]
1095 pub fn is_enabled(&self) -> bool {
1096 *self == Rie::Enabled
1097 }
1098}
1099#[doc = "Field `RIE` writer - Receiver Interrupt Enable"]
1100pub type RieW<'a, REG> = crate::BitWriter<'a, REG, Rie>;
1101impl<'a, REG> RieW<'a, REG>
1102where
1103 REG: crate::Writable + crate::RegisterSpec,
1104{
1105 #[doc = "Disable"]
1106 #[inline(always)]
1107 pub fn disabled(self) -> &'a mut crate::W<REG> {
1108 self.variant(Rie::Disabled)
1109 }
1110 #[doc = "Enable"]
1111 #[inline(always)]
1112 pub fn enabled(self) -> &'a mut crate::W<REG> {
1113 self.variant(Rie::Enabled)
1114 }
1115}
1116#[doc = "Transmission Complete Interrupt Enable\n\nValue on reset: 0"]
1117#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1119pub enum Tcie {
1120 #[doc = "0: Disable"]
1121 Disabled = 0,
1122 #[doc = "1: Enable"]
1123 Enabled = 1,
1124}
1125impl From<Tcie> for bool {
1126 #[inline(always)]
1127 fn from(variant: Tcie) -> Self {
1128 variant as u8 != 0
1129 }
1130}
1131#[doc = "Field `TCIE` reader - Transmission Complete Interrupt Enable"]
1132pub type TcieR = crate::BitReader<Tcie>;
1133impl TcieR {
1134 #[doc = "Get enumerated values variant"]
1135 #[inline(always)]
1136 pub const fn variant(&self) -> Tcie {
1137 match self.bits {
1138 false => Tcie::Disabled,
1139 true => Tcie::Enabled,
1140 }
1141 }
1142 #[doc = "Disable"]
1143 #[inline(always)]
1144 pub fn is_disabled(&self) -> bool {
1145 *self == Tcie::Disabled
1146 }
1147 #[doc = "Enable"]
1148 #[inline(always)]
1149 pub fn is_enabled(&self) -> bool {
1150 *self == Tcie::Enabled
1151 }
1152}
1153#[doc = "Field `TCIE` writer - Transmission Complete Interrupt Enable"]
1154pub type TcieW<'a, REG> = crate::BitWriter<'a, REG, Tcie>;
1155impl<'a, REG> TcieW<'a, REG>
1156where
1157 REG: crate::Writable + crate::RegisterSpec,
1158{
1159 #[doc = "Disable"]
1160 #[inline(always)]
1161 pub fn disabled(self) -> &'a mut crate::W<REG> {
1162 self.variant(Tcie::Disabled)
1163 }
1164 #[doc = "Enable"]
1165 #[inline(always)]
1166 pub fn enabled(self) -> &'a mut crate::W<REG> {
1167 self.variant(Tcie::Enabled)
1168 }
1169}
1170#[doc = "Transmit Interrupt Enable\n\nValue on reset: 0"]
1171#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1172#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1173pub enum Tie {
1174 #[doc = "0: Disable"]
1175 Disabled = 0,
1176 #[doc = "1: Enable"]
1177 Enabled = 1,
1178}
1179impl From<Tie> for bool {
1180 #[inline(always)]
1181 fn from(variant: Tie) -> Self {
1182 variant as u8 != 0
1183 }
1184}
1185#[doc = "Field `TIE` reader - Transmit Interrupt Enable"]
1186pub type TieR = crate::BitReader<Tie>;
1187impl TieR {
1188 #[doc = "Get enumerated values variant"]
1189 #[inline(always)]
1190 pub const fn variant(&self) -> Tie {
1191 match self.bits {
1192 false => Tie::Disabled,
1193 true => Tie::Enabled,
1194 }
1195 }
1196 #[doc = "Disable"]
1197 #[inline(always)]
1198 pub fn is_disabled(&self) -> bool {
1199 *self == Tie::Disabled
1200 }
1201 #[doc = "Enable"]
1202 #[inline(always)]
1203 pub fn is_enabled(&self) -> bool {
1204 *self == Tie::Enabled
1205 }
1206}
1207#[doc = "Field `TIE` writer - Transmit Interrupt Enable"]
1208pub type TieW<'a, REG> = crate::BitWriter<'a, REG, Tie>;
1209impl<'a, REG> TieW<'a, REG>
1210where
1211 REG: crate::Writable + crate::RegisterSpec,
1212{
1213 #[doc = "Disable"]
1214 #[inline(always)]
1215 pub fn disabled(self) -> &'a mut crate::W<REG> {
1216 self.variant(Tie::Disabled)
1217 }
1218 #[doc = "Enable"]
1219 #[inline(always)]
1220 pub fn enabled(self) -> &'a mut crate::W<REG> {
1221 self.variant(Tie::Enabled)
1222 }
1223}
1224#[doc = "Parity Error Interrupt Enable\n\nValue on reset: 0"]
1225#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1227pub enum Peie {
1228 #[doc = "0: Disable"]
1229 Disabled = 0,
1230 #[doc = "1: Enable"]
1231 Enabled = 1,
1232}
1233impl From<Peie> for bool {
1234 #[inline(always)]
1235 fn from(variant: Peie) -> Self {
1236 variant as u8 != 0
1237 }
1238}
1239#[doc = "Field `PEIE` reader - Parity Error Interrupt Enable"]
1240pub type PeieR = crate::BitReader<Peie>;
1241impl PeieR {
1242 #[doc = "Get enumerated values variant"]
1243 #[inline(always)]
1244 pub const fn variant(&self) -> Peie {
1245 match self.bits {
1246 false => Peie::Disabled,
1247 true => Peie::Enabled,
1248 }
1249 }
1250 #[doc = "Disable"]
1251 #[inline(always)]
1252 pub fn is_disabled(&self) -> bool {
1253 *self == Peie::Disabled
1254 }
1255 #[doc = "Enable"]
1256 #[inline(always)]
1257 pub fn is_enabled(&self) -> bool {
1258 *self == Peie::Enabled
1259 }
1260}
1261#[doc = "Field `PEIE` writer - Parity Error Interrupt Enable"]
1262pub type PeieW<'a, REG> = crate::BitWriter<'a, REG, Peie>;
1263impl<'a, REG> PeieW<'a, REG>
1264where
1265 REG: crate::Writable + crate::RegisterSpec,
1266{
1267 #[doc = "Disable"]
1268 #[inline(always)]
1269 pub fn disabled(self) -> &'a mut crate::W<REG> {
1270 self.variant(Peie::Disabled)
1271 }
1272 #[doc = "Enable"]
1273 #[inline(always)]
1274 pub fn enabled(self) -> &'a mut crate::W<REG> {
1275 self.variant(Peie::Enabled)
1276 }
1277}
1278#[doc = "Framing Error Interrupt Enable\n\nValue on reset: 0"]
1279#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1280#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1281pub enum Feie {
1282 #[doc = "0: Disable"]
1283 Disabled = 0,
1284 #[doc = "1: Enable"]
1285 Enabled = 1,
1286}
1287impl From<Feie> for bool {
1288 #[inline(always)]
1289 fn from(variant: Feie) -> Self {
1290 variant as u8 != 0
1291 }
1292}
1293#[doc = "Field `FEIE` reader - Framing Error Interrupt Enable"]
1294pub type FeieR = crate::BitReader<Feie>;
1295impl FeieR {
1296 #[doc = "Get enumerated values variant"]
1297 #[inline(always)]
1298 pub const fn variant(&self) -> Feie {
1299 match self.bits {
1300 false => Feie::Disabled,
1301 true => Feie::Enabled,
1302 }
1303 }
1304 #[doc = "Disable"]
1305 #[inline(always)]
1306 pub fn is_disabled(&self) -> bool {
1307 *self == Feie::Disabled
1308 }
1309 #[doc = "Enable"]
1310 #[inline(always)]
1311 pub fn is_enabled(&self) -> bool {
1312 *self == Feie::Enabled
1313 }
1314}
1315#[doc = "Field `FEIE` writer - Framing Error Interrupt Enable"]
1316pub type FeieW<'a, REG> = crate::BitWriter<'a, REG, Feie>;
1317impl<'a, REG> FeieW<'a, REG>
1318where
1319 REG: crate::Writable + crate::RegisterSpec,
1320{
1321 #[doc = "Disable"]
1322 #[inline(always)]
1323 pub fn disabled(self) -> &'a mut crate::W<REG> {
1324 self.variant(Feie::Disabled)
1325 }
1326 #[doc = "Enable"]
1327 #[inline(always)]
1328 pub fn enabled(self) -> &'a mut crate::W<REG> {
1329 self.variant(Feie::Enabled)
1330 }
1331}
1332#[doc = "Noise Error Interrupt Enable\n\nValue on reset: 0"]
1333#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1335pub enum Neie {
1336 #[doc = "0: Disable"]
1337 Disabled = 0,
1338 #[doc = "1: Enable"]
1339 Enabled = 1,
1340}
1341impl From<Neie> for bool {
1342 #[inline(always)]
1343 fn from(variant: Neie) -> Self {
1344 variant as u8 != 0
1345 }
1346}
1347#[doc = "Field `NEIE` reader - Noise Error Interrupt Enable"]
1348pub type NeieR = crate::BitReader<Neie>;
1349impl NeieR {
1350 #[doc = "Get enumerated values variant"]
1351 #[inline(always)]
1352 pub const fn variant(&self) -> Neie {
1353 match self.bits {
1354 false => Neie::Disabled,
1355 true => Neie::Enabled,
1356 }
1357 }
1358 #[doc = "Disable"]
1359 #[inline(always)]
1360 pub fn is_disabled(&self) -> bool {
1361 *self == Neie::Disabled
1362 }
1363 #[doc = "Enable"]
1364 #[inline(always)]
1365 pub fn is_enabled(&self) -> bool {
1366 *self == Neie::Enabled
1367 }
1368}
1369#[doc = "Field `NEIE` writer - Noise Error Interrupt Enable"]
1370pub type NeieW<'a, REG> = crate::BitWriter<'a, REG, Neie>;
1371impl<'a, REG> NeieW<'a, REG>
1372where
1373 REG: crate::Writable + crate::RegisterSpec,
1374{
1375 #[doc = "Disable"]
1376 #[inline(always)]
1377 pub fn disabled(self) -> &'a mut crate::W<REG> {
1378 self.variant(Neie::Disabled)
1379 }
1380 #[doc = "Enable"]
1381 #[inline(always)]
1382 pub fn enabled(self) -> &'a mut crate::W<REG> {
1383 self.variant(Neie::Enabled)
1384 }
1385}
1386#[doc = "Overrun Interrupt Enable\n\nValue on reset: 0"]
1387#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1388#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1389pub enum Orie {
1390 #[doc = "0: Disable"]
1391 Disabled = 0,
1392 #[doc = "1: Enable"]
1393 Enabled = 1,
1394}
1395impl From<Orie> for bool {
1396 #[inline(always)]
1397 fn from(variant: Orie) -> Self {
1398 variant as u8 != 0
1399 }
1400}
1401#[doc = "Field `ORIE` reader - Overrun Interrupt Enable"]
1402pub type OrieR = crate::BitReader<Orie>;
1403impl OrieR {
1404 #[doc = "Get enumerated values variant"]
1405 #[inline(always)]
1406 pub const fn variant(&self) -> Orie {
1407 match self.bits {
1408 false => Orie::Disabled,
1409 true => Orie::Enabled,
1410 }
1411 }
1412 #[doc = "Disable"]
1413 #[inline(always)]
1414 pub fn is_disabled(&self) -> bool {
1415 *self == Orie::Disabled
1416 }
1417 #[doc = "Enable"]
1418 #[inline(always)]
1419 pub fn is_enabled(&self) -> bool {
1420 *self == Orie::Enabled
1421 }
1422}
1423#[doc = "Field `ORIE` writer - Overrun Interrupt Enable"]
1424pub type OrieW<'a, REG> = crate::BitWriter<'a, REG, Orie>;
1425impl<'a, REG> OrieW<'a, REG>
1426where
1427 REG: crate::Writable + crate::RegisterSpec,
1428{
1429 #[doc = "Disable"]
1430 #[inline(always)]
1431 pub fn disabled(self) -> &'a mut crate::W<REG> {
1432 self.variant(Orie::Disabled)
1433 }
1434 #[doc = "Enable"]
1435 #[inline(always)]
1436 pub fn enabled(self) -> &'a mut crate::W<REG> {
1437 self.variant(Orie::Enabled)
1438 }
1439}
1440#[doc = "Transmit Data Inversion\n\nValue on reset: 0"]
1441#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1442#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1443pub enum Txinv {
1444 #[doc = "0: Not inverted"]
1445 NotInverted = 0,
1446 #[doc = "1: Inverted"]
1447 Inverted = 1,
1448}
1449impl From<Txinv> for bool {
1450 #[inline(always)]
1451 fn from(variant: Txinv) -> Self {
1452 variant as u8 != 0
1453 }
1454}
1455#[doc = "Field `TXINV` reader - Transmit Data Inversion"]
1456pub type TxinvR = crate::BitReader<Txinv>;
1457impl TxinvR {
1458 #[doc = "Get enumerated values variant"]
1459 #[inline(always)]
1460 pub const fn variant(&self) -> Txinv {
1461 match self.bits {
1462 false => Txinv::NotInverted,
1463 true => Txinv::Inverted,
1464 }
1465 }
1466 #[doc = "Not inverted"]
1467 #[inline(always)]
1468 pub fn is_not_inverted(&self) -> bool {
1469 *self == Txinv::NotInverted
1470 }
1471 #[doc = "Inverted"]
1472 #[inline(always)]
1473 pub fn is_inverted(&self) -> bool {
1474 *self == Txinv::Inverted
1475 }
1476}
1477#[doc = "Field `TXINV` writer - Transmit Data Inversion"]
1478pub type TxinvW<'a, REG> = crate::BitWriter<'a, REG, Txinv>;
1479impl<'a, REG> TxinvW<'a, REG>
1480where
1481 REG: crate::Writable + crate::RegisterSpec,
1482{
1483 #[doc = "Not inverted"]
1484 #[inline(always)]
1485 pub fn not_inverted(self) -> &'a mut crate::W<REG> {
1486 self.variant(Txinv::NotInverted)
1487 }
1488 #[doc = "Inverted"]
1489 #[inline(always)]
1490 pub fn inverted(self) -> &'a mut crate::W<REG> {
1491 self.variant(Txinv::Inverted)
1492 }
1493}
1494#[doc = "TXD Pin Direction in Single-Wire Mode\n\nValue on reset: 0"]
1495#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1496#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1497pub enum Txdir {
1498 #[doc = "0: Input"]
1499 TxInput = 0,
1500 #[doc = "1: Output"]
1501 TxOutput = 1,
1502}
1503impl From<Txdir> for bool {
1504 #[inline(always)]
1505 fn from(variant: Txdir) -> Self {
1506 variant as u8 != 0
1507 }
1508}
1509#[doc = "Field `TXDIR` reader - TXD Pin Direction in Single-Wire Mode"]
1510pub type TxdirR = crate::BitReader<Txdir>;
1511impl TxdirR {
1512 #[doc = "Get enumerated values variant"]
1513 #[inline(always)]
1514 pub const fn variant(&self) -> Txdir {
1515 match self.bits {
1516 false => Txdir::TxInput,
1517 true => Txdir::TxOutput,
1518 }
1519 }
1520 #[doc = "Input"]
1521 #[inline(always)]
1522 pub fn is_tx_input(&self) -> bool {
1523 *self == Txdir::TxInput
1524 }
1525 #[doc = "Output"]
1526 #[inline(always)]
1527 pub fn is_tx_output(&self) -> bool {
1528 *self == Txdir::TxOutput
1529 }
1530}
1531#[doc = "Field `TXDIR` writer - TXD Pin Direction in Single-Wire Mode"]
1532pub type TxdirW<'a, REG> = crate::BitWriter<'a, REG, Txdir>;
1533impl<'a, REG> TxdirW<'a, REG>
1534where
1535 REG: crate::Writable + crate::RegisterSpec,
1536{
1537 #[doc = "Input"]
1538 #[inline(always)]
1539 pub fn tx_input(self) -> &'a mut crate::W<REG> {
1540 self.variant(Txdir::TxInput)
1541 }
1542 #[doc = "Output"]
1543 #[inline(always)]
1544 pub fn tx_output(self) -> &'a mut crate::W<REG> {
1545 self.variant(Txdir::TxOutput)
1546 }
1547}
1548#[doc = "Field `R9T8` reader - Receive Bit 9 Transmit Bit 8"]
1549pub type R9t8R = crate::BitReader;
1550#[doc = "Field `R9T8` writer - Receive Bit 9 Transmit Bit 8"]
1551pub type R9t8W<'a, REG> = crate::BitWriter<'a, REG>;
1552#[doc = "Field `R8T9` reader - Receive Bit 8 Transmit Bit 9"]
1553pub type R8t9R = crate::BitReader;
1554#[doc = "Field `R8T9` writer - Receive Bit 8 Transmit Bit 9"]
1555pub type R8t9W<'a, REG> = crate::BitWriter<'a, REG>;
1556impl R {
1557 #[doc = "Bit 0 - Parity Type"]
1558 #[inline(always)]
1559 pub fn pt(&self) -> PtR {
1560 PtR::new((self.bits & 1) != 0)
1561 }
1562 #[doc = "Bit 1 - Parity Enable"]
1563 #[inline(always)]
1564 pub fn pe(&self) -> PeR {
1565 PeR::new(((self.bits >> 1) & 1) != 0)
1566 }
1567 #[doc = "Bit 2 - Idle Line Type Select"]
1568 #[inline(always)]
1569 pub fn ilt(&self) -> IltR {
1570 IltR::new(((self.bits >> 2) & 1) != 0)
1571 }
1572 #[doc = "Bit 3 - Receiver Wake-Up Method Select"]
1573 #[inline(always)]
1574 pub fn wake(&self) -> WakeR {
1575 WakeR::new(((self.bits >> 3) & 1) != 0)
1576 }
1577 #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"]
1578 #[inline(always)]
1579 pub fn m(&self) -> MR {
1580 MR::new(((self.bits >> 4) & 1) != 0)
1581 }
1582 #[doc = "Bit 5 - Receiver Source Select"]
1583 #[inline(always)]
1584 pub fn rsrc(&self) -> RsrcR {
1585 RsrcR::new(((self.bits >> 5) & 1) != 0)
1586 }
1587 #[doc = "Bit 6 - Doze Mode"]
1588 #[inline(always)]
1589 pub fn dozeen(&self) -> DozeenR {
1590 DozeenR::new(((self.bits >> 6) & 1) != 0)
1591 }
1592 #[doc = "Bit 7 - Loop Mode Select"]
1593 #[inline(always)]
1594 pub fn loops(&self) -> LoopsR {
1595 LoopsR::new(((self.bits >> 7) & 1) != 0)
1596 }
1597 #[doc = "Bits 8:10 - Idle Configuration"]
1598 #[inline(always)]
1599 pub fn idlecfg(&self) -> IdlecfgR {
1600 IdlecfgR::new(((self.bits >> 8) & 7) as u8)
1601 }
1602 #[doc = "Bit 11 - 7-Bit Mode Select"]
1603 #[inline(always)]
1604 pub fn m7(&self) -> M7R {
1605 M7R::new(((self.bits >> 11) & 1) != 0)
1606 }
1607 #[doc = "Bit 12 - TXD and RXD Pin Swap"]
1608 #[inline(always)]
1609 pub fn swap(&self) -> SwapR {
1610 SwapR::new(((self.bits >> 12) & 1) != 0)
1611 }
1612 #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"]
1613 #[inline(always)]
1614 pub fn ma2ie(&self) -> Ma2ieR {
1615 Ma2ieR::new(((self.bits >> 14) & 1) != 0)
1616 }
1617 #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"]
1618 #[inline(always)]
1619 pub fn ma1ie(&self) -> Ma1ieR {
1620 Ma1ieR::new(((self.bits >> 15) & 1) != 0)
1621 }
1622 #[doc = "Bit 16 - Send Break"]
1623 #[inline(always)]
1624 pub fn sbk(&self) -> SbkR {
1625 SbkR::new(((self.bits >> 16) & 1) != 0)
1626 }
1627 #[doc = "Bit 17 - Receiver Wake-Up Control"]
1628 #[inline(always)]
1629 pub fn rwu(&self) -> RwuR {
1630 RwuR::new(((self.bits >> 17) & 1) != 0)
1631 }
1632 #[doc = "Bit 18 - Receiver Enable"]
1633 #[inline(always)]
1634 pub fn re(&self) -> ReR {
1635 ReR::new(((self.bits >> 18) & 1) != 0)
1636 }
1637 #[doc = "Bit 19 - Transmitter Enable"]
1638 #[inline(always)]
1639 pub fn te(&self) -> TeR {
1640 TeR::new(((self.bits >> 19) & 1) != 0)
1641 }
1642 #[doc = "Bit 20 - Idle Line Interrupt Enable"]
1643 #[inline(always)]
1644 pub fn ilie(&self) -> IlieR {
1645 IlieR::new(((self.bits >> 20) & 1) != 0)
1646 }
1647 #[doc = "Bit 21 - Receiver Interrupt Enable"]
1648 #[inline(always)]
1649 pub fn rie(&self) -> RieR {
1650 RieR::new(((self.bits >> 21) & 1) != 0)
1651 }
1652 #[doc = "Bit 22 - Transmission Complete Interrupt Enable"]
1653 #[inline(always)]
1654 pub fn tcie(&self) -> TcieR {
1655 TcieR::new(((self.bits >> 22) & 1) != 0)
1656 }
1657 #[doc = "Bit 23 - Transmit Interrupt Enable"]
1658 #[inline(always)]
1659 pub fn tie(&self) -> TieR {
1660 TieR::new(((self.bits >> 23) & 1) != 0)
1661 }
1662 #[doc = "Bit 24 - Parity Error Interrupt Enable"]
1663 #[inline(always)]
1664 pub fn peie(&self) -> PeieR {
1665 PeieR::new(((self.bits >> 24) & 1) != 0)
1666 }
1667 #[doc = "Bit 25 - Framing Error Interrupt Enable"]
1668 #[inline(always)]
1669 pub fn feie(&self) -> FeieR {
1670 FeieR::new(((self.bits >> 25) & 1) != 0)
1671 }
1672 #[doc = "Bit 26 - Noise Error Interrupt Enable"]
1673 #[inline(always)]
1674 pub fn neie(&self) -> NeieR {
1675 NeieR::new(((self.bits >> 26) & 1) != 0)
1676 }
1677 #[doc = "Bit 27 - Overrun Interrupt Enable"]
1678 #[inline(always)]
1679 pub fn orie(&self) -> OrieR {
1680 OrieR::new(((self.bits >> 27) & 1) != 0)
1681 }
1682 #[doc = "Bit 28 - Transmit Data Inversion"]
1683 #[inline(always)]
1684 pub fn txinv(&self) -> TxinvR {
1685 TxinvR::new(((self.bits >> 28) & 1) != 0)
1686 }
1687 #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"]
1688 #[inline(always)]
1689 pub fn txdir(&self) -> TxdirR {
1690 TxdirR::new(((self.bits >> 29) & 1) != 0)
1691 }
1692 #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"]
1693 #[inline(always)]
1694 pub fn r9t8(&self) -> R9t8R {
1695 R9t8R::new(((self.bits >> 30) & 1) != 0)
1696 }
1697 #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"]
1698 #[inline(always)]
1699 pub fn r8t9(&self) -> R8t9R {
1700 R8t9R::new(((self.bits >> 31) & 1) != 0)
1701 }
1702}
1703#[cfg(feature = "debug")]
1704impl core::fmt::Debug for R {
1705 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1706 f.debug_struct("CTRL")
1707 .field("pt", &self.pt())
1708 .field("pe", &self.pe())
1709 .field("ilt", &self.ilt())
1710 .field("wake", &self.wake())
1711 .field("m", &self.m())
1712 .field("rsrc", &self.rsrc())
1713 .field("dozeen", &self.dozeen())
1714 .field("loops", &self.loops())
1715 .field("idlecfg", &self.idlecfg())
1716 .field("m7", &self.m7())
1717 .field("swap", &self.swap())
1718 .field("ma2ie", &self.ma2ie())
1719 .field("ma1ie", &self.ma1ie())
1720 .field("sbk", &self.sbk())
1721 .field("rwu", &self.rwu())
1722 .field("re", &self.re())
1723 .field("te", &self.te())
1724 .field("ilie", &self.ilie())
1725 .field("rie", &self.rie())
1726 .field("tcie", &self.tcie())
1727 .field("tie", &self.tie())
1728 .field("peie", &self.peie())
1729 .field("feie", &self.feie())
1730 .field("neie", &self.neie())
1731 .field("orie", &self.orie())
1732 .field("txinv", &self.txinv())
1733 .field("txdir", &self.txdir())
1734 .field("r9t8", &self.r9t8())
1735 .field("r8t9", &self.r8t9())
1736 .finish()
1737 }
1738}
1739impl W {
1740 #[doc = "Bit 0 - Parity Type"]
1741 #[inline(always)]
1742 pub fn pt(&mut self) -> PtW<'_, CtrlSpec> {
1743 PtW::new(self, 0)
1744 }
1745 #[doc = "Bit 1 - Parity Enable"]
1746 #[inline(always)]
1747 pub fn pe(&mut self) -> PeW<'_, CtrlSpec> {
1748 PeW::new(self, 1)
1749 }
1750 #[doc = "Bit 2 - Idle Line Type Select"]
1751 #[inline(always)]
1752 pub fn ilt(&mut self) -> IltW<'_, CtrlSpec> {
1753 IltW::new(self, 2)
1754 }
1755 #[doc = "Bit 3 - Receiver Wake-Up Method Select"]
1756 #[inline(always)]
1757 pub fn wake(&mut self) -> WakeW<'_, CtrlSpec> {
1758 WakeW::new(self, 3)
1759 }
1760 #[doc = "Bit 4 - 9-Bit Or 8-Bit Mode Select"]
1761 #[inline(always)]
1762 pub fn m(&mut self) -> MW<'_, CtrlSpec> {
1763 MW::new(self, 4)
1764 }
1765 #[doc = "Bit 5 - Receiver Source Select"]
1766 #[inline(always)]
1767 pub fn rsrc(&mut self) -> RsrcW<'_, CtrlSpec> {
1768 RsrcW::new(self, 5)
1769 }
1770 #[doc = "Bit 6 - Doze Mode"]
1771 #[inline(always)]
1772 pub fn dozeen(&mut self) -> DozeenW<'_, CtrlSpec> {
1773 DozeenW::new(self, 6)
1774 }
1775 #[doc = "Bit 7 - Loop Mode Select"]
1776 #[inline(always)]
1777 pub fn loops(&mut self) -> LoopsW<'_, CtrlSpec> {
1778 LoopsW::new(self, 7)
1779 }
1780 #[doc = "Bits 8:10 - Idle Configuration"]
1781 #[inline(always)]
1782 pub fn idlecfg(&mut self) -> IdlecfgW<'_, CtrlSpec> {
1783 IdlecfgW::new(self, 8)
1784 }
1785 #[doc = "Bit 11 - 7-Bit Mode Select"]
1786 #[inline(always)]
1787 pub fn m7(&mut self) -> M7W<'_, CtrlSpec> {
1788 M7W::new(self, 11)
1789 }
1790 #[doc = "Bit 12 - TXD and RXD Pin Swap"]
1791 #[inline(always)]
1792 pub fn swap(&mut self) -> SwapW<'_, CtrlSpec> {
1793 SwapW::new(self, 12)
1794 }
1795 #[doc = "Bit 14 - Match 2 (MA2F) Interrupt Enable"]
1796 #[inline(always)]
1797 pub fn ma2ie(&mut self) -> Ma2ieW<'_, CtrlSpec> {
1798 Ma2ieW::new(self, 14)
1799 }
1800 #[doc = "Bit 15 - Match 1 (MA1F) Interrupt Enable"]
1801 #[inline(always)]
1802 pub fn ma1ie(&mut self) -> Ma1ieW<'_, CtrlSpec> {
1803 Ma1ieW::new(self, 15)
1804 }
1805 #[doc = "Bit 16 - Send Break"]
1806 #[inline(always)]
1807 pub fn sbk(&mut self) -> SbkW<'_, CtrlSpec> {
1808 SbkW::new(self, 16)
1809 }
1810 #[doc = "Bit 17 - Receiver Wake-Up Control"]
1811 #[inline(always)]
1812 pub fn rwu(&mut self) -> RwuW<'_, CtrlSpec> {
1813 RwuW::new(self, 17)
1814 }
1815 #[doc = "Bit 18 - Receiver Enable"]
1816 #[inline(always)]
1817 pub fn re(&mut self) -> ReW<'_, CtrlSpec> {
1818 ReW::new(self, 18)
1819 }
1820 #[doc = "Bit 19 - Transmitter Enable"]
1821 #[inline(always)]
1822 pub fn te(&mut self) -> TeW<'_, CtrlSpec> {
1823 TeW::new(self, 19)
1824 }
1825 #[doc = "Bit 20 - Idle Line Interrupt Enable"]
1826 #[inline(always)]
1827 pub fn ilie(&mut self) -> IlieW<'_, CtrlSpec> {
1828 IlieW::new(self, 20)
1829 }
1830 #[doc = "Bit 21 - Receiver Interrupt Enable"]
1831 #[inline(always)]
1832 pub fn rie(&mut self) -> RieW<'_, CtrlSpec> {
1833 RieW::new(self, 21)
1834 }
1835 #[doc = "Bit 22 - Transmission Complete Interrupt Enable"]
1836 #[inline(always)]
1837 pub fn tcie(&mut self) -> TcieW<'_, CtrlSpec> {
1838 TcieW::new(self, 22)
1839 }
1840 #[doc = "Bit 23 - Transmit Interrupt Enable"]
1841 #[inline(always)]
1842 pub fn tie(&mut self) -> TieW<'_, CtrlSpec> {
1843 TieW::new(self, 23)
1844 }
1845 #[doc = "Bit 24 - Parity Error Interrupt Enable"]
1846 #[inline(always)]
1847 pub fn peie(&mut self) -> PeieW<'_, CtrlSpec> {
1848 PeieW::new(self, 24)
1849 }
1850 #[doc = "Bit 25 - Framing Error Interrupt Enable"]
1851 #[inline(always)]
1852 pub fn feie(&mut self) -> FeieW<'_, CtrlSpec> {
1853 FeieW::new(self, 25)
1854 }
1855 #[doc = "Bit 26 - Noise Error Interrupt Enable"]
1856 #[inline(always)]
1857 pub fn neie(&mut self) -> NeieW<'_, CtrlSpec> {
1858 NeieW::new(self, 26)
1859 }
1860 #[doc = "Bit 27 - Overrun Interrupt Enable"]
1861 #[inline(always)]
1862 pub fn orie(&mut self) -> OrieW<'_, CtrlSpec> {
1863 OrieW::new(self, 27)
1864 }
1865 #[doc = "Bit 28 - Transmit Data Inversion"]
1866 #[inline(always)]
1867 pub fn txinv(&mut self) -> TxinvW<'_, CtrlSpec> {
1868 TxinvW::new(self, 28)
1869 }
1870 #[doc = "Bit 29 - TXD Pin Direction in Single-Wire Mode"]
1871 #[inline(always)]
1872 pub fn txdir(&mut self) -> TxdirW<'_, CtrlSpec> {
1873 TxdirW::new(self, 29)
1874 }
1875 #[doc = "Bit 30 - Receive Bit 9 Transmit Bit 8"]
1876 #[inline(always)]
1877 pub fn r9t8(&mut self) -> R9t8W<'_, CtrlSpec> {
1878 R9t8W::new(self, 30)
1879 }
1880 #[doc = "Bit 31 - Receive Bit 8 Transmit Bit 9"]
1881 #[inline(always)]
1882 pub fn r8t9(&mut self) -> R8t9W<'_, CtrlSpec> {
1883 R8t9W::new(self, 31)
1884 }
1885}
1886#[doc = "Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1887pub struct CtrlSpec;
1888impl crate::RegisterSpec for CtrlSpec {
1889 type Ux = u32;
1890}
1891#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
1892impl crate::Readable for CtrlSpec {}
1893#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
1894impl crate::Writable for CtrlSpec {
1895 type Safety = crate::Unsafe;
1896}
1897#[doc = "`reset()` method sets CTRL to value 0"]
1898impl crate::Resettable for CtrlSpec {}