1#[doc = "Register `SCFGR1` reader"]
2pub type R = crate::R<Scfgr1Spec>;
3#[doc = "Register `SCFGR1` writer"]
4pub type W = crate::W<Scfgr1Spec>;
5#[doc = "Address SCL Stall\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Adrstall {
9 #[doc = "0: Disable"]
10 Disabled = 0,
11 #[doc = "1: Enable"]
12 Enabled = 1,
13}
14impl From<Adrstall> for bool {
15 #[inline(always)]
16 fn from(variant: Adrstall) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `ADRSTALL` reader - Address SCL Stall"]
21pub type AdrstallR = crate::BitReader<Adrstall>;
22impl AdrstallR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Adrstall {
26 match self.bits {
27 false => Adrstall::Disabled,
28 true => Adrstall::Enabled,
29 }
30 }
31 #[doc = "Disable"]
32 #[inline(always)]
33 pub fn is_disabled(&self) -> bool {
34 *self == Adrstall::Disabled
35 }
36 #[doc = "Enable"]
37 #[inline(always)]
38 pub fn is_enabled(&self) -> bool {
39 *self == Adrstall::Enabled
40 }
41}
42#[doc = "Field `ADRSTALL` writer - Address SCL Stall"]
43pub type AdrstallW<'a, REG> = crate::BitWriter<'a, REG, Adrstall>;
44impl<'a, REG> AdrstallW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Disable"]
49 #[inline(always)]
50 pub fn disabled(self) -> &'a mut crate::W<REG> {
51 self.variant(Adrstall::Disabled)
52 }
53 #[doc = "Enable"]
54 #[inline(always)]
55 pub fn enabled(self) -> &'a mut crate::W<REG> {
56 self.variant(Adrstall::Enabled)
57 }
58}
59#[doc = "RX SCL Stall\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Rxstall {
63 #[doc = "0: Disable"]
64 Disabled = 0,
65 #[doc = "1: Enable"]
66 Enabled = 1,
67}
68impl From<Rxstall> for bool {
69 #[inline(always)]
70 fn from(variant: Rxstall) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `RXSTALL` reader - RX SCL Stall"]
75pub type RxstallR = crate::BitReader<Rxstall>;
76impl RxstallR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Rxstall {
80 match self.bits {
81 false => Rxstall::Disabled,
82 true => Rxstall::Enabled,
83 }
84 }
85 #[doc = "Disable"]
86 #[inline(always)]
87 pub fn is_disabled(&self) -> bool {
88 *self == Rxstall::Disabled
89 }
90 #[doc = "Enable"]
91 #[inline(always)]
92 pub fn is_enabled(&self) -> bool {
93 *self == Rxstall::Enabled
94 }
95}
96#[doc = "Field `RXSTALL` writer - RX SCL Stall"]
97pub type RxstallW<'a, REG> = crate::BitWriter<'a, REG, Rxstall>;
98impl<'a, REG> RxstallW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Disable"]
103 #[inline(always)]
104 pub fn disabled(self) -> &'a mut crate::W<REG> {
105 self.variant(Rxstall::Disabled)
106 }
107 #[doc = "Enable"]
108 #[inline(always)]
109 pub fn enabled(self) -> &'a mut crate::W<REG> {
110 self.variant(Rxstall::Enabled)
111 }
112}
113#[doc = "Transmit Data SCL Stall\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Txdstall {
117 #[doc = "0: Disable"]
118 Disabled = 0,
119 #[doc = "1: Enable"]
120 Enabled = 1,
121}
122impl From<Txdstall> for bool {
123 #[inline(always)]
124 fn from(variant: Txdstall) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `TXDSTALL` reader - Transmit Data SCL Stall"]
129pub type TxdstallR = crate::BitReader<Txdstall>;
130impl TxdstallR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Txdstall {
134 match self.bits {
135 false => Txdstall::Disabled,
136 true => Txdstall::Enabled,
137 }
138 }
139 #[doc = "Disable"]
140 #[inline(always)]
141 pub fn is_disabled(&self) -> bool {
142 *self == Txdstall::Disabled
143 }
144 #[doc = "Enable"]
145 #[inline(always)]
146 pub fn is_enabled(&self) -> bool {
147 *self == Txdstall::Enabled
148 }
149}
150#[doc = "Field `TXDSTALL` writer - Transmit Data SCL Stall"]
151pub type TxdstallW<'a, REG> = crate::BitWriter<'a, REG, Txdstall>;
152impl<'a, REG> TxdstallW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Disable"]
157 #[inline(always)]
158 pub fn disabled(self) -> &'a mut crate::W<REG> {
159 self.variant(Txdstall::Disabled)
160 }
161 #[doc = "Enable"]
162 #[inline(always)]
163 pub fn enabled(self) -> &'a mut crate::W<REG> {
164 self.variant(Txdstall::Enabled)
165 }
166}
167#[doc = "ACK SCL Stall\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Ackstall {
171 #[doc = "0: Disable"]
172 Disabled = 0,
173 #[doc = "1: Enable"]
174 Enabled = 1,
175}
176impl From<Ackstall> for bool {
177 #[inline(always)]
178 fn from(variant: Ackstall) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `ACKSTALL` reader - ACK SCL Stall"]
183pub type AckstallR = crate::BitReader<Ackstall>;
184impl AckstallR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> Ackstall {
188 match self.bits {
189 false => Ackstall::Disabled,
190 true => Ackstall::Enabled,
191 }
192 }
193 #[doc = "Disable"]
194 #[inline(always)]
195 pub fn is_disabled(&self) -> bool {
196 *self == Ackstall::Disabled
197 }
198 #[doc = "Enable"]
199 #[inline(always)]
200 pub fn is_enabled(&self) -> bool {
201 *self == Ackstall::Enabled
202 }
203}
204#[doc = "Field `ACKSTALL` writer - ACK SCL Stall"]
205pub type AckstallW<'a, REG> = crate::BitWriter<'a, REG, Ackstall>;
206impl<'a, REG> AckstallW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Disable"]
211 #[inline(always)]
212 pub fn disabled(self) -> &'a mut crate::W<REG> {
213 self.variant(Ackstall::Disabled)
214 }
215 #[doc = "Enable"]
216 #[inline(always)]
217 pub fn enabled(self) -> &'a mut crate::W<REG> {
218 self.variant(Ackstall::Enabled)
219 }
220}
221#[doc = "Receive NACK\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Rxnack {
225 #[doc = "0: ACK or NACK always determined by STAR\\[TXNACK\\]"]
226 SetByTxnack = 0,
227 #[doc = "1: NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"]
228 AlwaysGeneratedOnAddressOrReceiveDataOverrun = 1,
229}
230impl From<Rxnack> for bool {
231 #[inline(always)]
232 fn from(variant: Rxnack) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `RXNACK` reader - Receive NACK"]
237pub type RxnackR = crate::BitReader<Rxnack>;
238impl RxnackR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> Rxnack {
242 match self.bits {
243 false => Rxnack::SetByTxnack,
244 true => Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun,
245 }
246 }
247 #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"]
248 #[inline(always)]
249 pub fn is_set_by_txnack(&self) -> bool {
250 *self == Rxnack::SetByTxnack
251 }
252 #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"]
253 #[inline(always)]
254 pub fn is_always_generated_on_address_or_receive_data_overrun(&self) -> bool {
255 *self == Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun
256 }
257}
258#[doc = "Field `RXNACK` writer - Receive NACK"]
259pub type RxnackW<'a, REG> = crate::BitWriter<'a, REG, Rxnack>;
260impl<'a, REG> RxnackW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "ACK or NACK always determined by STAR\\[TXNACK\\]"]
265 #[inline(always)]
266 pub fn set_by_txnack(self) -> &'a mut crate::W<REG> {
267 self.variant(Rxnack::SetByTxnack)
268 }
269 #[doc = "NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR\\[TXNACK\\]"]
270 #[inline(always)]
271 pub fn always_generated_on_address_or_receive_data_overrun(self) -> &'a mut crate::W<REG> {
272 self.variant(Rxnack::AlwaysGeneratedOnAddressOrReceiveDataOverrun)
273 }
274}
275#[doc = "General Call Enable\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Gcen {
279 #[doc = "0: Disable"]
280 Disabled = 0,
281 #[doc = "1: Enable"]
282 Enabled = 1,
283}
284impl From<Gcen> for bool {
285 #[inline(always)]
286 fn from(variant: Gcen) -> Self {
287 variant as u8 != 0
288 }
289}
290#[doc = "Field `GCEN` reader - General Call Enable"]
291pub type GcenR = crate::BitReader<Gcen>;
292impl GcenR {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub const fn variant(&self) -> Gcen {
296 match self.bits {
297 false => Gcen::Disabled,
298 true => Gcen::Enabled,
299 }
300 }
301 #[doc = "Disable"]
302 #[inline(always)]
303 pub fn is_disabled(&self) -> bool {
304 *self == Gcen::Disabled
305 }
306 #[doc = "Enable"]
307 #[inline(always)]
308 pub fn is_enabled(&self) -> bool {
309 *self == Gcen::Enabled
310 }
311}
312#[doc = "Field `GCEN` writer - General Call Enable"]
313pub type GcenW<'a, REG> = crate::BitWriter<'a, REG, Gcen>;
314impl<'a, REG> GcenW<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317{
318 #[doc = "Disable"]
319 #[inline(always)]
320 pub fn disabled(self) -> &'a mut crate::W<REG> {
321 self.variant(Gcen::Disabled)
322 }
323 #[doc = "Enable"]
324 #[inline(always)]
325 pub fn enabled(self) -> &'a mut crate::W<REG> {
326 self.variant(Gcen::Enabled)
327 }
328}
329#[doc = "SMBus Alert Enable\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Saen {
333 #[doc = "0: Disable"]
334 Disable = 0,
335 #[doc = "1: Enable"]
336 Enable = 1,
337}
338impl From<Saen> for bool {
339 #[inline(always)]
340 fn from(variant: Saen) -> Self {
341 variant as u8 != 0
342 }
343}
344#[doc = "Field `SAEN` reader - SMBus Alert Enable"]
345pub type SaenR = crate::BitReader<Saen>;
346impl SaenR {
347 #[doc = "Get enumerated values variant"]
348 #[inline(always)]
349 pub const fn variant(&self) -> Saen {
350 match self.bits {
351 false => Saen::Disable,
352 true => Saen::Enable,
353 }
354 }
355 #[doc = "Disable"]
356 #[inline(always)]
357 pub fn is_disable(&self) -> bool {
358 *self == Saen::Disable
359 }
360 #[doc = "Enable"]
361 #[inline(always)]
362 pub fn is_enable(&self) -> bool {
363 *self == Saen::Enable
364 }
365}
366#[doc = "Field `SAEN` writer - SMBus Alert Enable"]
367pub type SaenW<'a, REG> = crate::BitWriter<'a, REG, Saen>;
368impl<'a, REG> SaenW<'a, REG>
369where
370 REG: crate::Writable + crate::RegisterSpec,
371{
372 #[doc = "Disable"]
373 #[inline(always)]
374 pub fn disable(self) -> &'a mut crate::W<REG> {
375 self.variant(Saen::Disable)
376 }
377 #[doc = "Enable"]
378 #[inline(always)]
379 pub fn enable(self) -> &'a mut crate::W<REG> {
380 self.variant(Saen::Enable)
381 }
382}
383#[doc = "Transmit Flag Configuration\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Txcfg {
387 #[doc = "0: MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"]
388 AssertsDuringSlaveTransmitTransferWhenTxDataEmpty = 0,
389 #[doc = "1: MSR\\[TDF\\] is set whenever STDR is empty"]
390 AssertsWhenTxDataEmpty = 1,
391}
392impl From<Txcfg> for bool {
393 #[inline(always)]
394 fn from(variant: Txcfg) -> Self {
395 variant as u8 != 0
396 }
397}
398#[doc = "Field `TXCFG` reader - Transmit Flag Configuration"]
399pub type TxcfgR = crate::BitReader<Txcfg>;
400impl TxcfgR {
401 #[doc = "Get enumerated values variant"]
402 #[inline(always)]
403 pub const fn variant(&self) -> Txcfg {
404 match self.bits {
405 false => Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty,
406 true => Txcfg::AssertsWhenTxDataEmpty,
407 }
408 }
409 #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"]
410 #[inline(always)]
411 pub fn is_asserts_during_slave_transmit_transfer_when_tx_data_empty(&self) -> bool {
412 *self == Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty
413 }
414 #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"]
415 #[inline(always)]
416 pub fn is_asserts_when_tx_data_empty(&self) -> bool {
417 *self == Txcfg::AssertsWhenTxDataEmpty
418 }
419}
420#[doc = "Field `TXCFG` writer - Transmit Flag Configuration"]
421pub type TxcfgW<'a, REG> = crate::BitWriter<'a, REG, Txcfg>;
422impl<'a, REG> TxcfgW<'a, REG>
423where
424 REG: crate::Writable + crate::RegisterSpec,
425{
426 #[doc = "MSR\\[TDF\\] is set only during a target-transmit transfer when STDR is empty"]
427 #[inline(always)]
428 pub fn asserts_during_slave_transmit_transfer_when_tx_data_empty(self) -> &'a mut crate::W<REG> {
429 self.variant(Txcfg::AssertsDuringSlaveTransmitTransferWhenTxDataEmpty)
430 }
431 #[doc = "MSR\\[TDF\\] is set whenever STDR is empty"]
432 #[inline(always)]
433 pub fn asserts_when_tx_data_empty(self) -> &'a mut crate::W<REG> {
434 self.variant(Txcfg::AssertsWhenTxDataEmpty)
435 }
436}
437#[doc = "Receive Data Configuration\n\nValue on reset: 0"]
438#[cfg_attr(feature = "defmt", derive(defmt::Format))]
439#[derive(Clone, Copy, Debug, PartialEq, Eq)]
440pub enum Rxcfg {
441 #[doc = "0: Return received data, clear MSR\\[RDF\\]"]
442 ReturnsReceivedDataAndClearsRxDataFlag = 0,
443 #[doc = "1: Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"]
444 WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag = 1,
445}
446impl From<Rxcfg> for bool {
447 #[inline(always)]
448 fn from(variant: Rxcfg) -> Self {
449 variant as u8 != 0
450 }
451}
452#[doc = "Field `RXCFG` reader - Receive Data Configuration"]
453pub type RxcfgR = crate::BitReader<Rxcfg>;
454impl RxcfgR {
455 #[doc = "Get enumerated values variant"]
456 #[inline(always)]
457 pub const fn variant(&self) -> Rxcfg {
458 match self.bits {
459 false => Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag,
460 true => Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag,
461 }
462 }
463 #[doc = "Return received data, clear MSR\\[RDF\\]"]
464 #[inline(always)]
465 pub fn is_returns_received_data_and_clears_rx_data_flag(&self) -> bool {
466 *self == Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag
467 }
468 #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"]
469 #[inline(always)]
470 pub fn is_when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag(&self) -> bool {
471 *self == Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag
472 }
473}
474#[doc = "Field `RXCFG` writer - Receive Data Configuration"]
475pub type RxcfgW<'a, REG> = crate::BitWriter<'a, REG, Rxcfg>;
476impl<'a, REG> RxcfgW<'a, REG>
477where
478 REG: crate::Writable + crate::RegisterSpec,
479{
480 #[doc = "Return received data, clear MSR\\[RDF\\]"]
481 #[inline(always)]
482 pub fn returns_received_data_and_clears_rx_data_flag(self) -> &'a mut crate::W<REG> {
483 self.variant(Rxcfg::ReturnsReceivedDataAndClearsRxDataFlag)
484 }
485 #[doc = "Return SASR and clear SSR\\[AVF\\] when SSR\\[AVF\\] is set, return received data and clear MSR\\[RDF\\] when SSR\\[AFV\\] is not set"]
486 #[inline(always)]
487 pub fn when_address_valid_flag_set_returns_address_status_and_clears_address_valid_flag(
488 self,
489 ) -> &'a mut crate::W<REG> {
490 self.variant(Rxcfg::WhenAddressValidFlagSetReturnsAddressStatusAndClearsAddressValidFlag)
491 }
492}
493#[doc = "Ignore NACK\n\nValue on reset: 0"]
494#[cfg_attr(feature = "defmt", derive(defmt::Format))]
495#[derive(Clone, Copy, Debug, PartialEq, Eq)]
496pub enum Ignack {
497 #[doc = "0: End transfer on NACK"]
498 EndsTransferOnNack = 0,
499 #[doc = "1: Do not end transfer on NACK"]
500 DoesNotEndTransferOnNack = 1,
501}
502impl From<Ignack> for bool {
503 #[inline(always)]
504 fn from(variant: Ignack) -> Self {
505 variant as u8 != 0
506 }
507}
508#[doc = "Field `IGNACK` reader - Ignore NACK"]
509pub type IgnackR = crate::BitReader<Ignack>;
510impl IgnackR {
511 #[doc = "Get enumerated values variant"]
512 #[inline(always)]
513 pub const fn variant(&self) -> Ignack {
514 match self.bits {
515 false => Ignack::EndsTransferOnNack,
516 true => Ignack::DoesNotEndTransferOnNack,
517 }
518 }
519 #[doc = "End transfer on NACK"]
520 #[inline(always)]
521 pub fn is_ends_transfer_on_nack(&self) -> bool {
522 *self == Ignack::EndsTransferOnNack
523 }
524 #[doc = "Do not end transfer on NACK"]
525 #[inline(always)]
526 pub fn is_does_not_end_transfer_on_nack(&self) -> bool {
527 *self == Ignack::DoesNotEndTransferOnNack
528 }
529}
530#[doc = "Field `IGNACK` writer - Ignore NACK"]
531pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG, Ignack>;
532impl<'a, REG> IgnackW<'a, REG>
533where
534 REG: crate::Writable + crate::RegisterSpec,
535{
536 #[doc = "End transfer on NACK"]
537 #[inline(always)]
538 pub fn ends_transfer_on_nack(self) -> &'a mut crate::W<REG> {
539 self.variant(Ignack::EndsTransferOnNack)
540 }
541 #[doc = "Do not end transfer on NACK"]
542 #[inline(always)]
543 pub fn does_not_end_transfer_on_nack(self) -> &'a mut crate::W<REG> {
544 self.variant(Ignack::DoesNotEndTransferOnNack)
545 }
546}
547#[doc = "HS Mode Enable\n\nValue on reset: 0"]
548#[cfg_attr(feature = "defmt", derive(defmt::Format))]
549#[derive(Clone, Copy, Debug, PartialEq, Eq)]
550pub enum Hsmen {
551 #[doc = "0: Disable"]
552 Disabled = 0,
553 #[doc = "1: Enable"]
554 Enabled = 1,
555}
556impl From<Hsmen> for bool {
557 #[inline(always)]
558 fn from(variant: Hsmen) -> Self {
559 variant as u8 != 0
560 }
561}
562#[doc = "Field `HSMEN` reader - HS Mode Enable"]
563pub type HsmenR = crate::BitReader<Hsmen>;
564impl HsmenR {
565 #[doc = "Get enumerated values variant"]
566 #[inline(always)]
567 pub const fn variant(&self) -> Hsmen {
568 match self.bits {
569 false => Hsmen::Disabled,
570 true => Hsmen::Enabled,
571 }
572 }
573 #[doc = "Disable"]
574 #[inline(always)]
575 pub fn is_disabled(&self) -> bool {
576 *self == Hsmen::Disabled
577 }
578 #[doc = "Enable"]
579 #[inline(always)]
580 pub fn is_enabled(&self) -> bool {
581 *self == Hsmen::Enabled
582 }
583}
584#[doc = "Field `HSMEN` writer - HS Mode Enable"]
585pub type HsmenW<'a, REG> = crate::BitWriter<'a, REG, Hsmen>;
586impl<'a, REG> HsmenW<'a, REG>
587where
588 REG: crate::Writable + crate::RegisterSpec,
589{
590 #[doc = "Disable"]
591 #[inline(always)]
592 pub fn disabled(self) -> &'a mut crate::W<REG> {
593 self.variant(Hsmen::Disabled)
594 }
595 #[doc = "Enable"]
596 #[inline(always)]
597 pub fn enabled(self) -> &'a mut crate::W<REG> {
598 self.variant(Hsmen::Enabled)
599 }
600}
601#[doc = "Address Configuration\n\nValue on reset: 0"]
602#[cfg_attr(feature = "defmt", derive(defmt::Format))]
603#[derive(Clone, Copy, Debug, PartialEq, Eq)]
604#[repr(u8)]
605pub enum Addrcfg {
606 #[doc = "0: Address match 0 (7-bit)"]
607 AddressMatch0_7Bit = 0,
608 #[doc = "1: Address match 0 (10-bit)"]
609 AddressMatch0_10Bit = 1,
610 #[doc = "2: Address match 0 (7-bit) or address match 1 (7-bit)"]
611 AddressMatch0_7BitOrAddressMatch1_7Bit = 2,
612 #[doc = "3: Address match 0 (10-bit) or address match 1 (10-bit)"]
613 AddressMatch0_10BitOrAddressMatch1_10Bit = 3,
614 #[doc = "4: Address match 0 (7-bit) or address match 1 (10-bit)"]
615 AddressMatch0_7BitOrAddressMatch1_10Bit = 4,
616 #[doc = "5: Address match 0 (10-bit) or address match 1 (7-bit)"]
617 AddressMatch0_10BitOrAddressMatch1_7Bit = 5,
618 #[doc = "6: From address match 0 (7-bit) to address match 1 (7-bit)"]
619 FromAddressMatch0_7BitToAddressMatch1_7Bit = 6,
620 #[doc = "7: From address match 0 (10-bit) to address match 1 (10-bit)"]
621 FromAddressMatch0_10BitToAddressMatch1_10Bit = 7,
622}
623impl From<Addrcfg> for u8 {
624 #[inline(always)]
625 fn from(variant: Addrcfg) -> Self {
626 variant as _
627 }
628}
629impl crate::FieldSpec for Addrcfg {
630 type Ux = u8;
631}
632impl crate::IsEnum for Addrcfg {}
633#[doc = "Field `ADDRCFG` reader - Address Configuration"]
634pub type AddrcfgR = crate::FieldReader<Addrcfg>;
635impl AddrcfgR {
636 #[doc = "Get enumerated values variant"]
637 #[inline(always)]
638 pub const fn variant(&self) -> Addrcfg {
639 match self.bits {
640 0 => Addrcfg::AddressMatch0_7Bit,
641 1 => Addrcfg::AddressMatch0_10Bit,
642 2 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit,
643 3 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit,
644 4 => Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit,
645 5 => Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit,
646 6 => Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit,
647 7 => Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit,
648 _ => unreachable!(),
649 }
650 }
651 #[doc = "Address match 0 (7-bit)"]
652 #[inline(always)]
653 pub fn is_address_match0_7_bit(&self) -> bool {
654 *self == Addrcfg::AddressMatch0_7Bit
655 }
656 #[doc = "Address match 0 (10-bit)"]
657 #[inline(always)]
658 pub fn is_address_match0_10_bit(&self) -> bool {
659 *self == Addrcfg::AddressMatch0_10Bit
660 }
661 #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"]
662 #[inline(always)]
663 pub fn is_address_match0_7_bit_or_address_match1_7_bit(&self) -> bool {
664 *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit
665 }
666 #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"]
667 #[inline(always)]
668 pub fn is_address_match0_10_bit_or_address_match1_10_bit(&self) -> bool {
669 *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit
670 }
671 #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"]
672 #[inline(always)]
673 pub fn is_address_match0_7_bit_or_address_match1_10_bit(&self) -> bool {
674 *self == Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit
675 }
676 #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"]
677 #[inline(always)]
678 pub fn is_address_match0_10_bit_or_address_match1_7_bit(&self) -> bool {
679 *self == Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit
680 }
681 #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"]
682 #[inline(always)]
683 pub fn is_from_address_match0_7_bit_to_address_match1_7_bit(&self) -> bool {
684 *self == Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit
685 }
686 #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"]
687 #[inline(always)]
688 pub fn is_from_address_match0_10_bit_to_address_match1_10_bit(&self) -> bool {
689 *self == Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit
690 }
691}
692#[doc = "Field `ADDRCFG` writer - Address Configuration"]
693pub type AddrcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Addrcfg, crate::Safe>;
694impl<'a, REG> AddrcfgW<'a, REG>
695where
696 REG: crate::Writable + crate::RegisterSpec,
697 REG::Ux: From<u8>,
698{
699 #[doc = "Address match 0 (7-bit)"]
700 #[inline(always)]
701 pub fn address_match0_7_bit(self) -> &'a mut crate::W<REG> {
702 self.variant(Addrcfg::AddressMatch0_7Bit)
703 }
704 #[doc = "Address match 0 (10-bit)"]
705 #[inline(always)]
706 pub fn address_match0_10_bit(self) -> &'a mut crate::W<REG> {
707 self.variant(Addrcfg::AddressMatch0_10Bit)
708 }
709 #[doc = "Address match 0 (7-bit) or address match 1 (7-bit)"]
710 #[inline(always)]
711 pub fn address_match0_7_bit_or_address_match1_7_bit(self) -> &'a mut crate::W<REG> {
712 self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_7Bit)
713 }
714 #[doc = "Address match 0 (10-bit) or address match 1 (10-bit)"]
715 #[inline(always)]
716 pub fn address_match0_10_bit_or_address_match1_10_bit(self) -> &'a mut crate::W<REG> {
717 self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_10Bit)
718 }
719 #[doc = "Address match 0 (7-bit) or address match 1 (10-bit)"]
720 #[inline(always)]
721 pub fn address_match0_7_bit_or_address_match1_10_bit(self) -> &'a mut crate::W<REG> {
722 self.variant(Addrcfg::AddressMatch0_7BitOrAddressMatch1_10Bit)
723 }
724 #[doc = "Address match 0 (10-bit) or address match 1 (7-bit)"]
725 #[inline(always)]
726 pub fn address_match0_10_bit_or_address_match1_7_bit(self) -> &'a mut crate::W<REG> {
727 self.variant(Addrcfg::AddressMatch0_10BitOrAddressMatch1_7Bit)
728 }
729 #[doc = "From address match 0 (7-bit) to address match 1 (7-bit)"]
730 #[inline(always)]
731 pub fn from_address_match0_7_bit_to_address_match1_7_bit(self) -> &'a mut crate::W<REG> {
732 self.variant(Addrcfg::FromAddressMatch0_7BitToAddressMatch1_7Bit)
733 }
734 #[doc = "From address match 0 (10-bit) to address match 1 (10-bit)"]
735 #[inline(always)]
736 pub fn from_address_match0_10_bit_to_address_match1_10_bit(self) -> &'a mut crate::W<REG> {
737 self.variant(Addrcfg::FromAddressMatch0_10BitToAddressMatch1_10Bit)
738 }
739}
740#[doc = "Receive All\n\nValue on reset: 0"]
741#[cfg_attr(feature = "defmt", derive(defmt::Format))]
742#[derive(Clone, Copy, Debug, PartialEq, Eq)]
743pub enum Rxall {
744 #[doc = "0: Disable"]
745 Disabled = 0,
746 #[doc = "1: Enable"]
747 Enabled = 1,
748}
749impl From<Rxall> for bool {
750 #[inline(always)]
751 fn from(variant: Rxall) -> Self {
752 variant as u8 != 0
753 }
754}
755#[doc = "Field `RXALL` reader - Receive All"]
756pub type RxallR = crate::BitReader<Rxall>;
757impl RxallR {
758 #[doc = "Get enumerated values variant"]
759 #[inline(always)]
760 pub const fn variant(&self) -> Rxall {
761 match self.bits {
762 false => Rxall::Disabled,
763 true => Rxall::Enabled,
764 }
765 }
766 #[doc = "Disable"]
767 #[inline(always)]
768 pub fn is_disabled(&self) -> bool {
769 *self == Rxall::Disabled
770 }
771 #[doc = "Enable"]
772 #[inline(always)]
773 pub fn is_enabled(&self) -> bool {
774 *self == Rxall::Enabled
775 }
776}
777#[doc = "Field `RXALL` writer - Receive All"]
778pub type RxallW<'a, REG> = crate::BitWriter<'a, REG, Rxall>;
779impl<'a, REG> RxallW<'a, REG>
780where
781 REG: crate::Writable + crate::RegisterSpec,
782{
783 #[doc = "Disable"]
784 #[inline(always)]
785 pub fn disabled(self) -> &'a mut crate::W<REG> {
786 self.variant(Rxall::Disabled)
787 }
788 #[doc = "Enable"]
789 #[inline(always)]
790 pub fn enabled(self) -> &'a mut crate::W<REG> {
791 self.variant(Rxall::Enabled)
792 }
793}
794#[doc = "Repeated Start Configuration\n\nValue on reset: 0"]
795#[cfg_attr(feature = "defmt", derive(defmt::Format))]
796#[derive(Clone, Copy, Debug, PartialEq, Eq)]
797pub enum Rscfg {
798 #[doc = "0: Any repeated Start condition following an address match"]
799 AnyRepeatedStartAfterAddressMatch = 0,
800 #[doc = "1: Any repeated Start condition"]
801 AnyRepeatedStart = 1,
802}
803impl From<Rscfg> for bool {
804 #[inline(always)]
805 fn from(variant: Rscfg) -> Self {
806 variant as u8 != 0
807 }
808}
809#[doc = "Field `RSCFG` reader - Repeated Start Configuration"]
810pub type RscfgR = crate::BitReader<Rscfg>;
811impl RscfgR {
812 #[doc = "Get enumerated values variant"]
813 #[inline(always)]
814 pub const fn variant(&self) -> Rscfg {
815 match self.bits {
816 false => Rscfg::AnyRepeatedStartAfterAddressMatch,
817 true => Rscfg::AnyRepeatedStart,
818 }
819 }
820 #[doc = "Any repeated Start condition following an address match"]
821 #[inline(always)]
822 pub fn is_any_repeated_start_after_address_match(&self) -> bool {
823 *self == Rscfg::AnyRepeatedStartAfterAddressMatch
824 }
825 #[doc = "Any repeated Start condition"]
826 #[inline(always)]
827 pub fn is_any_repeated_start(&self) -> bool {
828 *self == Rscfg::AnyRepeatedStart
829 }
830}
831#[doc = "Field `RSCFG` writer - Repeated Start Configuration"]
832pub type RscfgW<'a, REG> = crate::BitWriter<'a, REG, Rscfg>;
833impl<'a, REG> RscfgW<'a, REG>
834where
835 REG: crate::Writable + crate::RegisterSpec,
836{
837 #[doc = "Any repeated Start condition following an address match"]
838 #[inline(always)]
839 pub fn any_repeated_start_after_address_match(self) -> &'a mut crate::W<REG> {
840 self.variant(Rscfg::AnyRepeatedStartAfterAddressMatch)
841 }
842 #[doc = "Any repeated Start condition"]
843 #[inline(always)]
844 pub fn any_repeated_start(self) -> &'a mut crate::W<REG> {
845 self.variant(Rscfg::AnyRepeatedStart)
846 }
847}
848#[doc = "Stop Detect Configuration\n\nValue on reset: 0"]
849#[cfg_attr(feature = "defmt", derive(defmt::Format))]
850#[derive(Clone, Copy, Debug, PartialEq, Eq)]
851pub enum Sdcfg {
852 #[doc = "0: Any Stop condition following an address match"]
853 AnyStopAfterAddressMatch = 0,
854 #[doc = "1: Any Stop condition"]
855 AnyStop = 1,
856}
857impl From<Sdcfg> for bool {
858 #[inline(always)]
859 fn from(variant: Sdcfg) -> Self {
860 variant as u8 != 0
861 }
862}
863#[doc = "Field `SDCFG` reader - Stop Detect Configuration"]
864pub type SdcfgR = crate::BitReader<Sdcfg>;
865impl SdcfgR {
866 #[doc = "Get enumerated values variant"]
867 #[inline(always)]
868 pub const fn variant(&self) -> Sdcfg {
869 match self.bits {
870 false => Sdcfg::AnyStopAfterAddressMatch,
871 true => Sdcfg::AnyStop,
872 }
873 }
874 #[doc = "Any Stop condition following an address match"]
875 #[inline(always)]
876 pub fn is_any_stop_after_address_match(&self) -> bool {
877 *self == Sdcfg::AnyStopAfterAddressMatch
878 }
879 #[doc = "Any Stop condition"]
880 #[inline(always)]
881 pub fn is_any_stop(&self) -> bool {
882 *self == Sdcfg::AnyStop
883 }
884}
885#[doc = "Field `SDCFG` writer - Stop Detect Configuration"]
886pub type SdcfgW<'a, REG> = crate::BitWriter<'a, REG, Sdcfg>;
887impl<'a, REG> SdcfgW<'a, REG>
888where
889 REG: crate::Writable + crate::RegisterSpec,
890{
891 #[doc = "Any Stop condition following an address match"]
892 #[inline(always)]
893 pub fn any_stop_after_address_match(self) -> &'a mut crate::W<REG> {
894 self.variant(Sdcfg::AnyStopAfterAddressMatch)
895 }
896 #[doc = "Any Stop condition"]
897 #[inline(always)]
898 pub fn any_stop(self) -> &'a mut crate::W<REG> {
899 self.variant(Sdcfg::AnyStop)
900 }
901}
902impl R {
903 #[doc = "Bit 0 - Address SCL Stall"]
904 #[inline(always)]
905 pub fn adrstall(&self) -> AdrstallR {
906 AdrstallR::new((self.bits & 1) != 0)
907 }
908 #[doc = "Bit 1 - RX SCL Stall"]
909 #[inline(always)]
910 pub fn rxstall(&self) -> RxstallR {
911 RxstallR::new(((self.bits >> 1) & 1) != 0)
912 }
913 #[doc = "Bit 2 - Transmit Data SCL Stall"]
914 #[inline(always)]
915 pub fn txdstall(&self) -> TxdstallR {
916 TxdstallR::new(((self.bits >> 2) & 1) != 0)
917 }
918 #[doc = "Bit 3 - ACK SCL Stall"]
919 #[inline(always)]
920 pub fn ackstall(&self) -> AckstallR {
921 AckstallR::new(((self.bits >> 3) & 1) != 0)
922 }
923 #[doc = "Bit 4 - Receive NACK"]
924 #[inline(always)]
925 pub fn rxnack(&self) -> RxnackR {
926 RxnackR::new(((self.bits >> 4) & 1) != 0)
927 }
928 #[doc = "Bit 8 - General Call Enable"]
929 #[inline(always)]
930 pub fn gcen(&self) -> GcenR {
931 GcenR::new(((self.bits >> 8) & 1) != 0)
932 }
933 #[doc = "Bit 9 - SMBus Alert Enable"]
934 #[inline(always)]
935 pub fn saen(&self) -> SaenR {
936 SaenR::new(((self.bits >> 9) & 1) != 0)
937 }
938 #[doc = "Bit 10 - Transmit Flag Configuration"]
939 #[inline(always)]
940 pub fn txcfg(&self) -> TxcfgR {
941 TxcfgR::new(((self.bits >> 10) & 1) != 0)
942 }
943 #[doc = "Bit 11 - Receive Data Configuration"]
944 #[inline(always)]
945 pub fn rxcfg(&self) -> RxcfgR {
946 RxcfgR::new(((self.bits >> 11) & 1) != 0)
947 }
948 #[doc = "Bit 12 - Ignore NACK"]
949 #[inline(always)]
950 pub fn ignack(&self) -> IgnackR {
951 IgnackR::new(((self.bits >> 12) & 1) != 0)
952 }
953 #[doc = "Bit 13 - HS Mode Enable"]
954 #[inline(always)]
955 pub fn hsmen(&self) -> HsmenR {
956 HsmenR::new(((self.bits >> 13) & 1) != 0)
957 }
958 #[doc = "Bits 16:18 - Address Configuration"]
959 #[inline(always)]
960 pub fn addrcfg(&self) -> AddrcfgR {
961 AddrcfgR::new(((self.bits >> 16) & 7) as u8)
962 }
963 #[doc = "Bit 24 - Receive All"]
964 #[inline(always)]
965 pub fn rxall(&self) -> RxallR {
966 RxallR::new(((self.bits >> 24) & 1) != 0)
967 }
968 #[doc = "Bit 25 - Repeated Start Configuration"]
969 #[inline(always)]
970 pub fn rscfg(&self) -> RscfgR {
971 RscfgR::new(((self.bits >> 25) & 1) != 0)
972 }
973 #[doc = "Bit 26 - Stop Detect Configuration"]
974 #[inline(always)]
975 pub fn sdcfg(&self) -> SdcfgR {
976 SdcfgR::new(((self.bits >> 26) & 1) != 0)
977 }
978}
979#[cfg(feature = "debug")]
980impl core::fmt::Debug for R {
981 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
982 f.debug_struct("SCFGR1")
983 .field("adrstall", &self.adrstall())
984 .field("rxstall", &self.rxstall())
985 .field("txdstall", &self.txdstall())
986 .field("ackstall", &self.ackstall())
987 .field("rxnack", &self.rxnack())
988 .field("gcen", &self.gcen())
989 .field("saen", &self.saen())
990 .field("txcfg", &self.txcfg())
991 .field("rxcfg", &self.rxcfg())
992 .field("ignack", &self.ignack())
993 .field("hsmen", &self.hsmen())
994 .field("addrcfg", &self.addrcfg())
995 .field("rxall", &self.rxall())
996 .field("rscfg", &self.rscfg())
997 .field("sdcfg", &self.sdcfg())
998 .finish()
999 }
1000}
1001impl W {
1002 #[doc = "Bit 0 - Address SCL Stall"]
1003 #[inline(always)]
1004 pub fn adrstall(&mut self) -> AdrstallW<'_, Scfgr1Spec> {
1005 AdrstallW::new(self, 0)
1006 }
1007 #[doc = "Bit 1 - RX SCL Stall"]
1008 #[inline(always)]
1009 pub fn rxstall(&mut self) -> RxstallW<'_, Scfgr1Spec> {
1010 RxstallW::new(self, 1)
1011 }
1012 #[doc = "Bit 2 - Transmit Data SCL Stall"]
1013 #[inline(always)]
1014 pub fn txdstall(&mut self) -> TxdstallW<'_, Scfgr1Spec> {
1015 TxdstallW::new(self, 2)
1016 }
1017 #[doc = "Bit 3 - ACK SCL Stall"]
1018 #[inline(always)]
1019 pub fn ackstall(&mut self) -> AckstallW<'_, Scfgr1Spec> {
1020 AckstallW::new(self, 3)
1021 }
1022 #[doc = "Bit 4 - Receive NACK"]
1023 #[inline(always)]
1024 pub fn rxnack(&mut self) -> RxnackW<'_, Scfgr1Spec> {
1025 RxnackW::new(self, 4)
1026 }
1027 #[doc = "Bit 8 - General Call Enable"]
1028 #[inline(always)]
1029 pub fn gcen(&mut self) -> GcenW<'_, Scfgr1Spec> {
1030 GcenW::new(self, 8)
1031 }
1032 #[doc = "Bit 9 - SMBus Alert Enable"]
1033 #[inline(always)]
1034 pub fn saen(&mut self) -> SaenW<'_, Scfgr1Spec> {
1035 SaenW::new(self, 9)
1036 }
1037 #[doc = "Bit 10 - Transmit Flag Configuration"]
1038 #[inline(always)]
1039 pub fn txcfg(&mut self) -> TxcfgW<'_, Scfgr1Spec> {
1040 TxcfgW::new(self, 10)
1041 }
1042 #[doc = "Bit 11 - Receive Data Configuration"]
1043 #[inline(always)]
1044 pub fn rxcfg(&mut self) -> RxcfgW<'_, Scfgr1Spec> {
1045 RxcfgW::new(self, 11)
1046 }
1047 #[doc = "Bit 12 - Ignore NACK"]
1048 #[inline(always)]
1049 pub fn ignack(&mut self) -> IgnackW<'_, Scfgr1Spec> {
1050 IgnackW::new(self, 12)
1051 }
1052 #[doc = "Bit 13 - HS Mode Enable"]
1053 #[inline(always)]
1054 pub fn hsmen(&mut self) -> HsmenW<'_, Scfgr1Spec> {
1055 HsmenW::new(self, 13)
1056 }
1057 #[doc = "Bits 16:18 - Address Configuration"]
1058 #[inline(always)]
1059 pub fn addrcfg(&mut self) -> AddrcfgW<'_, Scfgr1Spec> {
1060 AddrcfgW::new(self, 16)
1061 }
1062 #[doc = "Bit 24 - Receive All"]
1063 #[inline(always)]
1064 pub fn rxall(&mut self) -> RxallW<'_, Scfgr1Spec> {
1065 RxallW::new(self, 24)
1066 }
1067 #[doc = "Bit 25 - Repeated Start Configuration"]
1068 #[inline(always)]
1069 pub fn rscfg(&mut self) -> RscfgW<'_, Scfgr1Spec> {
1070 RscfgW::new(self, 25)
1071 }
1072 #[doc = "Bit 26 - Stop Detect Configuration"]
1073 #[inline(always)]
1074 pub fn sdcfg(&mut self) -> SdcfgW<'_, Scfgr1Spec> {
1075 SdcfgW::new(self, 26)
1076 }
1077}
1078#[doc = "Target Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`scfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1079pub struct Scfgr1Spec;
1080impl crate::RegisterSpec for Scfgr1Spec {
1081 type Ux = u32;
1082}
1083#[doc = "`read()` method returns [`scfgr1::R`](R) reader structure"]
1084impl crate::Readable for Scfgr1Spec {}
1085#[doc = "`write(|w| ..)` method takes [`scfgr1::W`](W) writer structure"]
1086impl crate::Writable for Scfgr1Spec {
1087 type Safety = crate::Unsafe;
1088}
1089#[doc = "`reset()` method sets SCFGR1 to value 0"]
1090impl crate::Resettable for Scfgr1Spec {}