mcxa_pac/lpi2c0/
mccr1.rs

1#[doc = "Register `MCCR1` reader"]
2pub type R = crate::R<Mccr1Spec>;
3#[doc = "Register `MCCR1` writer"]
4pub type W = crate::W<Mccr1Spec>;
5#[doc = "Field `CLKLO` reader - Clock Low Period"]
6pub type ClkloR = crate::FieldReader;
7#[doc = "Field `CLKLO` writer - Clock Low Period"]
8pub type ClkloW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `CLKHI` reader - Clock High Period"]
10pub type ClkhiR = crate::FieldReader;
11#[doc = "Field `CLKHI` writer - Clock High Period"]
12pub type ClkhiW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `SETHOLD` reader - Setup Hold Delay"]
14pub type SetholdR = crate::FieldReader;
15#[doc = "Field `SETHOLD` writer - Setup Hold Delay"]
16pub type SetholdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `DATAVD` reader - Data Valid Delay"]
18pub type DatavdR = crate::FieldReader;
19#[doc = "Field `DATAVD` writer - Data Valid Delay"]
20pub type DatavdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21impl R {
22    #[doc = "Bits 0:5 - Clock Low Period"]
23    #[inline(always)]
24    pub fn clklo(&self) -> ClkloR {
25        ClkloR::new((self.bits & 0x3f) as u8)
26    }
27    #[doc = "Bits 8:13 - Clock High Period"]
28    #[inline(always)]
29    pub fn clkhi(&self) -> ClkhiR {
30        ClkhiR::new(((self.bits >> 8) & 0x3f) as u8)
31    }
32    #[doc = "Bits 16:21 - Setup Hold Delay"]
33    #[inline(always)]
34    pub fn sethold(&self) -> SetholdR {
35        SetholdR::new(((self.bits >> 16) & 0x3f) as u8)
36    }
37    #[doc = "Bits 24:29 - Data Valid Delay"]
38    #[inline(always)]
39    pub fn datavd(&self) -> DatavdR {
40        DatavdR::new(((self.bits >> 24) & 0x3f) as u8)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("MCCR1")
47            .field("clklo", &self.clklo())
48            .field("clkhi", &self.clkhi())
49            .field("sethold", &self.sethold())
50            .field("datavd", &self.datavd())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:5 - Clock Low Period"]
56    #[inline(always)]
57    pub fn clklo(&mut self) -> ClkloW<'_, Mccr1Spec> {
58        ClkloW::new(self, 0)
59    }
60    #[doc = "Bits 8:13 - Clock High Period"]
61    #[inline(always)]
62    pub fn clkhi(&mut self) -> ClkhiW<'_, Mccr1Spec> {
63        ClkhiW::new(self, 8)
64    }
65    #[doc = "Bits 16:21 - Setup Hold Delay"]
66    #[inline(always)]
67    pub fn sethold(&mut self) -> SetholdW<'_, Mccr1Spec> {
68        SetholdW::new(self, 16)
69    }
70    #[doc = "Bits 24:29 - Data Valid Delay"]
71    #[inline(always)]
72    pub fn datavd(&mut self) -> DatavdW<'_, Mccr1Spec> {
73        DatavdW::new(self, 24)
74    }
75}
76#[doc = "Controller Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct Mccr1Spec;
78impl crate::RegisterSpec for Mccr1Spec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`mccr1::R`](R) reader structure"]
82impl crate::Readable for Mccr1Spec {}
83#[doc = "`write(|w| ..)` method takes [`mccr1::W`](W) writer structure"]
84impl crate::Writable for Mccr1Spec {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets MCCR1 to value 0"]
88impl crate::Resettable for Mccr1Spec {}
mcxa_pac/lpi2c0/mccr1.rs

mcxa_pac/lpi2c0/
mccr1.rs
