mcxa_pac/i3c0/
swdatab.rs

1#[doc = "Register `SWDATAB` writer"]
2pub type W = crate::W<SwdatabSpec>;
3#[doc = "Field `DATA` writer - Data"]
4pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
5#[doc = "End\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum End {
9    #[doc = "0: Not the end"]
10    NotEnd = 0,
11    #[doc = "1: End"]
12    End = 1,
13}
14impl From<End> for bool {
15    #[inline(always)]
16    fn from(variant: End) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `END` writer - End"]
21pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>;
22impl<'a, REG> EndW<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    #[doc = "Not the end"]
27    #[inline(always)]
28    pub fn not_end(self) -> &'a mut crate::W<REG> {
29        self.variant(End::NotEnd)
30    }
31    #[doc = "End"]
32    #[inline(always)]
33    pub fn end(self) -> &'a mut crate::W<REG> {
34        self.variant(End::End)
35    }
36}
37#[doc = "End Also\n\nValue on reset: 0"]
38#[cfg_attr(feature = "defmt", derive(defmt::Format))]
39#[derive(Clone, Copy, Debug, PartialEq, Eq)]
40pub enum EndAlso {
41    #[doc = "0: Not the end"]
42    NotEnd = 0,
43    #[doc = "1: End"]
44    End = 1,
45}
46impl From<EndAlso> for bool {
47    #[inline(always)]
48    fn from(variant: EndAlso) -> Self {
49        variant as u8 != 0
50    }
51}
52#[doc = "Field `END_ALSO` writer - End Also"]
53pub type EndAlsoW<'a, REG> = crate::BitWriter<'a, REG, EndAlso>;
54impl<'a, REG> EndAlsoW<'a, REG>
55where
56    REG: crate::Writable + crate::RegisterSpec,
57{
58    #[doc = "Not the end"]
59    #[inline(always)]
60    pub fn not_end(self) -> &'a mut crate::W<REG> {
61        self.variant(EndAlso::NotEnd)
62    }
63    #[doc = "End"]
64    #[inline(always)]
65    pub fn end(self) -> &'a mut crate::W<REG> {
66        self.variant(EndAlso::End)
67    }
68}
69#[cfg(feature = "debug")]
70impl core::fmt::Debug for crate::generic::Reg<SwdatabSpec> {
71    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
72        write!(f, "(not readable)")
73    }
74}
75impl W {
76    #[doc = "Bits 0:7 - Data"]
77    #[inline(always)]
78    pub fn data(&mut self) -> DataW<'_, SwdatabSpec> {
79        DataW::new(self, 0)
80    }
81    #[doc = "Bit 8 - End"]
82    #[inline(always)]
83    pub fn end(&mut self) -> EndW<'_, SwdatabSpec> {
84        EndW::new(self, 8)
85    }
86    #[doc = "Bit 16 - End Also"]
87    #[inline(always)]
88    pub fn end_also(&mut self) -> EndAlsoW<'_, SwdatabSpec> {
89        EndAlsoW::new(self, 16)
90    }
91}
92#[doc = "Target Write Data Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
93pub struct SwdatabSpec;
94impl crate::RegisterSpec for SwdatabSpec {
95    type Ux = u32;
96}
97#[doc = "`write(|w| ..)` method takes [`swdatab::W`](W) writer structure"]
98impl crate::Writable for SwdatabSpec {
99    type Safety = crate::Unsafe;
100}
101#[doc = "`reset()` method sets SWDATAB to value 0"]
102impl crate::Resettable for SwdatabSpec {}
mcxa_pac/i3c0/swdatab.rs

mcxa_pac/i3c0/
swdatab.rs
