mcxa_pac/i3c0/
sidext.rs

1#[doc = "Register `SIDEXT` reader"]
2pub type R = crate::R<SidextSpec>;
3#[doc = "Register `SIDEXT` writer"]
4pub type W = crate::W<SidextSpec>;
5#[doc = "Field `DCR` reader - Device Characteristic Register"]
6pub type DcrR = crate::FieldReader;
7#[doc = "Field `DCR` writer - Device Characteristic Register"]
8pub type DcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `BCR` reader - Bus Characteristics Register"]
10pub type BcrR = crate::FieldReader;
11#[doc = "Field `BCR` writer - Bus Characteristics Register"]
12pub type BcrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13impl R {
14    #[doc = "Bits 8:15 - Device Characteristic Register"]
15    #[inline(always)]
16    pub fn dcr(&self) -> DcrR {
17        DcrR::new(((self.bits >> 8) & 0xff) as u8)
18    }
19    #[doc = "Bits 16:23 - Bus Characteristics Register"]
20    #[inline(always)]
21    pub fn bcr(&self) -> BcrR {
22        BcrR::new(((self.bits >> 16) & 0xff) as u8)
23    }
24}
25#[cfg(feature = "debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SIDEXT")
29            .field("dcr", &self.dcr())
30            .field("bcr", &self.bcr())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 8:15 - Device Characteristic Register"]
36    #[inline(always)]
37    pub fn dcr(&mut self) -> DcrW<'_, SidextSpec> {
38        DcrW::new(self, 8)
39    }
40    #[doc = "Bits 16:23 - Bus Characteristics Register"]
41    #[inline(always)]
42    pub fn bcr(&mut self) -> BcrW<'_, SidextSpec> {
43        BcrW::new(self, 16)
44    }
45}
46#[doc = "Target ID Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`sidext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sidext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct SidextSpec;
48impl crate::RegisterSpec for SidextSpec {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`sidext::R`](R) reader structure"]
52impl crate::Readable for SidextSpec {}
53#[doc = "`write(|w| ..)` method takes [`sidext::W`](W) writer structure"]
54impl crate::Writable for SidextSpec {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets SIDEXT to value 0x0066_ef00"]
58impl crate::Resettable for SidextSpec {
59    const RESET_VALUE: u32 = 0x0066_ef00;
60}
mcxa_pac/i3c0/sidext.rs

mcxa_pac/i3c0/
sidext.rs
