mcxa_pac/i3c0/
mwmsg_ddr_data.rs

1#[doc = "Register `MWMSG_DDR_DATA` writer"]
2pub type W = crate::W<MwmsgDdrDataSpec>;
3#[doc = "Field `DATA16B` writer - Data"]
4pub type Data16bW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<MwmsgDdrDataSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:15 - Data"]
13    #[inline(always)]
14    pub fn data16b(&mut self) -> Data16bW<'_, MwmsgDdrDataSpec> {
15        Data16bW::new(self, 0)
16    }
17}
18#[doc = "Controller Write Message Data in DDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwmsg_ddr_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct MwmsgDdrDataSpec;
20impl crate::RegisterSpec for MwmsgDdrDataSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`mwmsg_ddr_data::W`](W) writer structure"]
24impl crate::Writable for MwmsgDdrDataSpec {
25    type Safety = crate::Unsafe;
26}
27#[doc = "`reset()` method sets MWMSG_DDR_DATA to value 0"]
28impl crate::Resettable for MwmsgDdrDataSpec {}
mcxa_pac/i3c0/mwmsg_ddr_data.rs

mcxa_pac/i3c0/
mwmsg_ddr_data.rs
