mcxa_pac/i3c0/
mwmsg_ddr_control2.rs

1#[doc = "Register `MWMSG_DDR_CONTROL2` writer"]
2pub type W = crate::W<MwmsgDdrControl2Spec>;
3#[doc = "Field `LEN` writer - Length of Message"]
4pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
5#[doc = "End of Message\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum End {
9    #[doc = "0: Not the end"]
10    NotEnd = 0,
11    #[doc = "1: End"]
12    End = 1,
13}
14impl From<End> for bool {
15    #[inline(always)]
16    fn from(variant: End) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `END` writer - End of Message"]
21pub type EndW<'a, REG> = crate::BitWriter<'a, REG, End>;
22impl<'a, REG> EndW<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    #[doc = "Not the end"]
27    #[inline(always)]
28    pub fn not_end(self) -> &'a mut crate::W<REG> {
29        self.variant(End::NotEnd)
30    }
31    #[doc = "End"]
32    #[inline(always)]
33    pub fn end(self) -> &'a mut crate::W<REG> {
34        self.variant(End::End)
35    }
36}
37#[cfg(feature = "debug")]
38impl core::fmt::Debug for crate::generic::Reg<MwmsgDdrControl2Spec> {
39    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
40        write!(f, "(not readable)")
41    }
42}
43impl W {
44    #[doc = "Bits 0:9 - Length of Message"]
45    #[inline(always)]
46    pub fn len(&mut self) -> LenW<'_, MwmsgDdrControl2Spec> {
47        LenW::new(self, 0)
48    }
49    #[doc = "Bit 14 - End of Message"]
50    #[inline(always)]
51    pub fn end(&mut self) -> EndW<'_, MwmsgDdrControl2Spec> {
52        EndW::new(self, 14)
53    }
54}
55#[doc = "Controller Write Message in DDR Mode Control 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwmsg_ddr_control2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
56pub struct MwmsgDdrControl2Spec;
57impl crate::RegisterSpec for MwmsgDdrControl2Spec {
58    type Ux = u32;
59}
60#[doc = "`write(|w| ..)` method takes [`mwmsg_ddr_control2::W`](W) writer structure"]
61impl crate::Writable for MwmsgDdrControl2Spec {
62    type Safety = crate::Unsafe;
63}
64#[doc = "`reset()` method sets MWMSG_DDR_CONTROL2 to value 0"]
65impl crate::Resettable for MwmsgDdrControl2Spec {}
mcxa_pac/i3c0/mwmsg_ddr_control2.rs

mcxa_pac/i3c0/
mwmsg_ddr_control2.rs
