mcxa_pac/i3c0/
mibirules.rs1#[doc = "Register `MIBIRULES` reader"]
2pub type R = crate::R<MibirulesSpec>;
3#[doc = "Register `MIBIRULES` writer"]
4pub type W = crate::W<MibirulesSpec>;
5#[doc = "Field `ADDR0` reader - ADDR0"]
6pub type Addr0R = crate::FieldReader;
7#[doc = "Field `ADDR0` writer - ADDR0"]
8pub type Addr0W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `ADDR1` reader - ADDR1"]
10pub type Addr1R = crate::FieldReader;
11#[doc = "Field `ADDR1` writer - ADDR1"]
12pub type Addr1W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `ADDR2` reader - ADDR2"]
14pub type Addr2R = crate::FieldReader;
15#[doc = "Field `ADDR2` writer - ADDR2"]
16pub type Addr2W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `ADDR3` reader - ADDR3"]
18pub type Addr3R = crate::FieldReader;
19#[doc = "Field `ADDR3` writer - ADDR3"]
20pub type Addr3W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
21#[doc = "Field `ADDR4` reader - ADDR4"]
22pub type Addr4R = crate::FieldReader;
23#[doc = "Field `ADDR4` writer - ADDR4"]
24pub type Addr4W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
25#[doc = "Most Significant Address Bit is 0\n\nValue on reset: 0"]
26#[cfg_attr(feature = "defmt", derive(defmt::Format))]
27#[derive(Clone, Copy, Debug, PartialEq, Eq)]
28pub enum Msb0 {
29 #[doc = "0: MSB is not 0"]
30 Disable = 0,
31 #[doc = "1: MSB is 0"]
32 Enable = 1,
33}
34impl From<Msb0> for bool {
35 #[inline(always)]
36 fn from(variant: Msb0) -> Self {
37 variant as u8 != 0
38 }
39}
40#[doc = "Field `MSB0` reader - Most Significant Address Bit is 0"]
41pub type Msb0R = crate::BitReader<Msb0>;
42impl Msb0R {
43 #[doc = "Get enumerated values variant"]
44 #[inline(always)]
45 pub const fn variant(&self) -> Msb0 {
46 match self.bits {
47 false => Msb0::Disable,
48 true => Msb0::Enable,
49 }
50 }
51 #[doc = "MSB is not 0"]
52 #[inline(always)]
53 pub fn is_disable(&self) -> bool {
54 *self == Msb0::Disable
55 }
56 #[doc = "MSB is 0"]
57 #[inline(always)]
58 pub fn is_enable(&self) -> bool {
59 *self == Msb0::Enable
60 }
61}
62#[doc = "Field `MSB0` writer - Most Significant Address Bit is 0"]
63pub type Msb0W<'a, REG> = crate::BitWriter<'a, REG, Msb0>;
64impl<'a, REG> Msb0W<'a, REG>
65where
66 REG: crate::Writable + crate::RegisterSpec,
67{
68 #[doc = "MSB is not 0"]
69 #[inline(always)]
70 pub fn disable(self) -> &'a mut crate::W<REG> {
71 self.variant(Msb0::Disable)
72 }
73 #[doc = "MSB is 0"]
74 #[inline(always)]
75 pub fn enable(self) -> &'a mut crate::W<REG> {
76 self.variant(Msb0::Enable)
77 }
78}
79#[doc = "No IBI byte\n\nValue on reset: 0"]
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum Nobyte {
83 #[doc = "0: With mandatory IBI byte"]
84 Ibibyte = 0,
85 #[doc = "1: Without mandatory IBI byte"]
86 NoIbibyte = 1,
87}
88impl From<Nobyte> for bool {
89 #[inline(always)]
90 fn from(variant: Nobyte) -> Self {
91 variant as u8 != 0
92 }
93}
94#[doc = "Field `NOBYTE` reader - No IBI byte"]
95pub type NobyteR = crate::BitReader<Nobyte>;
96impl NobyteR {
97 #[doc = "Get enumerated values variant"]
98 #[inline(always)]
99 pub const fn variant(&self) -> Nobyte {
100 match self.bits {
101 false => Nobyte::Ibibyte,
102 true => Nobyte::NoIbibyte,
103 }
104 }
105 #[doc = "With mandatory IBI byte"]
106 #[inline(always)]
107 pub fn is_ibibyte(&self) -> bool {
108 *self == Nobyte::Ibibyte
109 }
110 #[doc = "Without mandatory IBI byte"]
111 #[inline(always)]
112 pub fn is_no_ibibyte(&self) -> bool {
113 *self == Nobyte::NoIbibyte
114 }
115}
116#[doc = "Field `NOBYTE` writer - No IBI byte"]
117pub type NobyteW<'a, REG> = crate::BitWriter<'a, REG, Nobyte>;
118impl<'a, REG> NobyteW<'a, REG>
119where
120 REG: crate::Writable + crate::RegisterSpec,
121{
122 #[doc = "With mandatory IBI byte"]
123 #[inline(always)]
124 pub fn ibibyte(self) -> &'a mut crate::W<REG> {
125 self.variant(Nobyte::Ibibyte)
126 }
127 #[doc = "Without mandatory IBI byte"]
128 #[inline(always)]
129 pub fn no_ibibyte(self) -> &'a mut crate::W<REG> {
130 self.variant(Nobyte::NoIbibyte)
131 }
132}
133impl R {
134 #[doc = "Bits 0:5 - ADDR0"]
135 #[inline(always)]
136 pub fn addr0(&self) -> Addr0R {
137 Addr0R::new((self.bits & 0x3f) as u8)
138 }
139 #[doc = "Bits 6:11 - ADDR1"]
140 #[inline(always)]
141 pub fn addr1(&self) -> Addr1R {
142 Addr1R::new(((self.bits >> 6) & 0x3f) as u8)
143 }
144 #[doc = "Bits 12:17 - ADDR2"]
145 #[inline(always)]
146 pub fn addr2(&self) -> Addr2R {
147 Addr2R::new(((self.bits >> 12) & 0x3f) as u8)
148 }
149 #[doc = "Bits 18:23 - ADDR3"]
150 #[inline(always)]
151 pub fn addr3(&self) -> Addr3R {
152 Addr3R::new(((self.bits >> 18) & 0x3f) as u8)
153 }
154 #[doc = "Bits 24:29 - ADDR4"]
155 #[inline(always)]
156 pub fn addr4(&self) -> Addr4R {
157 Addr4R::new(((self.bits >> 24) & 0x3f) as u8)
158 }
159 #[doc = "Bit 30 - Most Significant Address Bit is 0"]
160 #[inline(always)]
161 pub fn msb0(&self) -> Msb0R {
162 Msb0R::new(((self.bits >> 30) & 1) != 0)
163 }
164 #[doc = "Bit 31 - No IBI byte"]
165 #[inline(always)]
166 pub fn nobyte(&self) -> NobyteR {
167 NobyteR::new(((self.bits >> 31) & 1) != 0)
168 }
169}
170#[cfg(feature = "debug")]
171impl core::fmt::Debug for R {
172 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
173 f.debug_struct("MIBIRULES")
174 .field("addr0", &self.addr0())
175 .field("addr1", &self.addr1())
176 .field("addr2", &self.addr2())
177 .field("addr3", &self.addr3())
178 .field("addr4", &self.addr4())
179 .field("msb0", &self.msb0())
180 .field("nobyte", &self.nobyte())
181 .finish()
182 }
183}
184impl W {
185 #[doc = "Bits 0:5 - ADDR0"]
186 #[inline(always)]
187 pub fn addr0(&mut self) -> Addr0W<'_, MibirulesSpec> {
188 Addr0W::new(self, 0)
189 }
190 #[doc = "Bits 6:11 - ADDR1"]
191 #[inline(always)]
192 pub fn addr1(&mut self) -> Addr1W<'_, MibirulesSpec> {
193 Addr1W::new(self, 6)
194 }
195 #[doc = "Bits 12:17 - ADDR2"]
196 #[inline(always)]
197 pub fn addr2(&mut self) -> Addr2W<'_, MibirulesSpec> {
198 Addr2W::new(self, 12)
199 }
200 #[doc = "Bits 18:23 - ADDR3"]
201 #[inline(always)]
202 pub fn addr3(&mut self) -> Addr3W<'_, MibirulesSpec> {
203 Addr3W::new(self, 18)
204 }
205 #[doc = "Bits 24:29 - ADDR4"]
206 #[inline(always)]
207 pub fn addr4(&mut self) -> Addr4W<'_, MibirulesSpec> {
208 Addr4W::new(self, 24)
209 }
210 #[doc = "Bit 30 - Most Significant Address Bit is 0"]
211 #[inline(always)]
212 pub fn msb0(&mut self) -> Msb0W<'_, MibirulesSpec> {
213 Msb0W::new(self, 30)
214 }
215 #[doc = "Bit 31 - No IBI byte"]
216 #[inline(always)]
217 pub fn nobyte(&mut self) -> NobyteW<'_, MibirulesSpec> {
218 NobyteW::new(self, 31)
219 }
220}
221#[doc = "Controller In-band Interrupt Registry and Rules\n\nYou can [`read`](crate::Reg::read) this register and get [`mibirules::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mibirules::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct MibirulesSpec;
223impl crate::RegisterSpec for MibirulesSpec {
224 type Ux = u32;
225}
226#[doc = "`read()` method returns [`mibirules::R`](R) reader structure"]
227impl crate::Readable for MibirulesSpec {}
228#[doc = "`write(|w| ..)` method takes [`mibirules::W`](W) writer structure"]
229impl crate::Writable for MibirulesSpec {
230 type Safety = crate::Unsafe;
231}
232#[doc = "`reset()` method sets MIBIRULES to value 0"]
233impl crate::Resettable for MibirulesSpec {}