mcxa_pac/gpio0/
pddr.rs

1#[doc = "Register `PDDR` reader"]
2pub type R = crate::R<PddrSpec>;
3#[doc = "Register `PDDR` writer"]
4pub type W = crate::W<PddrSpec>;
5#[doc = "Port Data Direction\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Pdd {
9    #[doc = "0: Input"]
10    Pdd0 = 0,
11    #[doc = "1: Output"]
12    Pdd1 = 1,
13}
14impl From<Pdd> for bool {
15    #[inline(always)]
16    fn from(variant: Pdd) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `PDD(0-31)` reader - Port Data Direction"]
21pub type PddR = crate::BitReader<Pdd>;
22impl PddR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Pdd {
26        match self.bits {
27            false => Pdd::Pdd0,
28            true => Pdd::Pdd1,
29        }
30    }
31    #[doc = "Input"]
32    #[inline(always)]
33    pub fn is_pdd0(&self) -> bool {
34        *self == Pdd::Pdd0
35    }
36    #[doc = "Output"]
37    #[inline(always)]
38    pub fn is_pdd1(&self) -> bool {
39        *self == Pdd::Pdd1
40    }
41}
42#[doc = "Field `PDD(0-31)` writer - Port Data Direction"]
43pub type PddW<'a, REG> = crate::BitWriter<'a, REG, Pdd>;
44impl<'a, REG> PddW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Input"]
49    #[inline(always)]
50    pub fn pdd0(self) -> &'a mut crate::W<REG> {
51        self.variant(Pdd::Pdd0)
52    }
53    #[doc = "Output"]
54    #[inline(always)]
55    pub fn pdd1(self) -> &'a mut crate::W<REG> {
56        self.variant(Pdd::Pdd1)
57    }
58}
59impl R {
60    #[doc = "Port Data Direction"]
61    #[doc = ""]
62    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `PDD0` field.</div>"]
63    #[inline(always)]
64    pub fn pdd(&self, n: u8) -> PddR {
65        #[allow(clippy::no_effect)]
66        [(); 32][n as usize];
67        PddR::new(((self.bits >> n) & 1) != 0)
68    }
69    #[doc = "Iterator for array of:"]
70    #[doc = "Port Data Direction"]
71    #[inline(always)]
72    pub fn pdd_iter(&self) -> impl Iterator<Item = PddR> + '_ {
73        (0..32).map(move |n| PddR::new(((self.bits >> n) & 1) != 0))
74    }
75    #[doc = "Bit 0 - Port Data Direction"]
76    #[inline(always)]
77    pub fn pdd0(&self) -> PddR {
78        PddR::new((self.bits & 1) != 0)
79    }
80    #[doc = "Bit 1 - Port Data Direction"]
81    #[inline(always)]
82    pub fn pdd1(&self) -> PddR {
83        PddR::new(((self.bits >> 1) & 1) != 0)
84    }
85    #[doc = "Bit 2 - Port Data Direction"]
86    #[inline(always)]
87    pub fn pdd2(&self) -> PddR {
88        PddR::new(((self.bits >> 2) & 1) != 0)
89    }
90    #[doc = "Bit 3 - Port Data Direction"]
91    #[inline(always)]
92    pub fn pdd3(&self) -> PddR {
93        PddR::new(((self.bits >> 3) & 1) != 0)
94    }
95    #[doc = "Bit 4 - Port Data Direction"]
96    #[inline(always)]
97    pub fn pdd4(&self) -> PddR {
98        PddR::new(((self.bits >> 4) & 1) != 0)
99    }
100    #[doc = "Bit 5 - Port Data Direction"]
101    #[inline(always)]
102    pub fn pdd5(&self) -> PddR {
103        PddR::new(((self.bits >> 5) & 1) != 0)
104    }
105    #[doc = "Bit 6 - Port Data Direction"]
106    #[inline(always)]
107    pub fn pdd6(&self) -> PddR {
108        PddR::new(((self.bits >> 6) & 1) != 0)
109    }
110    #[doc = "Bit 7 - Port Data Direction"]
111    #[inline(always)]
112    pub fn pdd7(&self) -> PddR {
113        PddR::new(((self.bits >> 7) & 1) != 0)
114    }
115    #[doc = "Bit 8 - Port Data Direction"]
116    #[inline(always)]
117    pub fn pdd8(&self) -> PddR {
118        PddR::new(((self.bits >> 8) & 1) != 0)
119    }
120    #[doc = "Bit 9 - Port Data Direction"]
121    #[inline(always)]
122    pub fn pdd9(&self) -> PddR {
123        PddR::new(((self.bits >> 9) & 1) != 0)
124    }
125    #[doc = "Bit 10 - Port Data Direction"]
126    #[inline(always)]
127    pub fn pdd10(&self) -> PddR {
128        PddR::new(((self.bits >> 10) & 1) != 0)
129    }
130    #[doc = "Bit 11 - Port Data Direction"]
131    #[inline(always)]
132    pub fn pdd11(&self) -> PddR {
133        PddR::new(((self.bits >> 11) & 1) != 0)
134    }
135    #[doc = "Bit 12 - Port Data Direction"]
136    #[inline(always)]
137    pub fn pdd12(&self) -> PddR {
138        PddR::new(((self.bits >> 12) & 1) != 0)
139    }
140    #[doc = "Bit 13 - Port Data Direction"]
141    #[inline(always)]
142    pub fn pdd13(&self) -> PddR {
143        PddR::new(((self.bits >> 13) & 1) != 0)
144    }
145    #[doc = "Bit 14 - Port Data Direction"]
146    #[inline(always)]
147    pub fn pdd14(&self) -> PddR {
148        PddR::new(((self.bits >> 14) & 1) != 0)
149    }
150    #[doc = "Bit 15 - Port Data Direction"]
151    #[inline(always)]
152    pub fn pdd15(&self) -> PddR {
153        PddR::new(((self.bits >> 15) & 1) != 0)
154    }
155    #[doc = "Bit 16 - Port Data Direction"]
156    #[inline(always)]
157    pub fn pdd16(&self) -> PddR {
158        PddR::new(((self.bits >> 16) & 1) != 0)
159    }
160    #[doc = "Bit 17 - Port Data Direction"]
161    #[inline(always)]
162    pub fn pdd17(&self) -> PddR {
163        PddR::new(((self.bits >> 17) & 1) != 0)
164    }
165    #[doc = "Bit 18 - Port Data Direction"]
166    #[inline(always)]
167    pub fn pdd18(&self) -> PddR {
168        PddR::new(((self.bits >> 18) & 1) != 0)
169    }
170    #[doc = "Bit 19 - Port Data Direction"]
171    #[inline(always)]
172    pub fn pdd19(&self) -> PddR {
173        PddR::new(((self.bits >> 19) & 1) != 0)
174    }
175    #[doc = "Bit 20 - Port Data Direction"]
176    #[inline(always)]
177    pub fn pdd20(&self) -> PddR {
178        PddR::new(((self.bits >> 20) & 1) != 0)
179    }
180    #[doc = "Bit 21 - Port Data Direction"]
181    #[inline(always)]
182    pub fn pdd21(&self) -> PddR {
183        PddR::new(((self.bits >> 21) & 1) != 0)
184    }
185    #[doc = "Bit 22 - Port Data Direction"]
186    #[inline(always)]
187    pub fn pdd22(&self) -> PddR {
188        PddR::new(((self.bits >> 22) & 1) != 0)
189    }
190    #[doc = "Bit 23 - Port Data Direction"]
191    #[inline(always)]
192    pub fn pdd23(&self) -> PddR {
193        PddR::new(((self.bits >> 23) & 1) != 0)
194    }
195    #[doc = "Bit 24 - Port Data Direction"]
196    #[inline(always)]
197    pub fn pdd24(&self) -> PddR {
198        PddR::new(((self.bits >> 24) & 1) != 0)
199    }
200    #[doc = "Bit 25 - Port Data Direction"]
201    #[inline(always)]
202    pub fn pdd25(&self) -> PddR {
203        PddR::new(((self.bits >> 25) & 1) != 0)
204    }
205    #[doc = "Bit 26 - Port Data Direction"]
206    #[inline(always)]
207    pub fn pdd26(&self) -> PddR {
208        PddR::new(((self.bits >> 26) & 1) != 0)
209    }
210    #[doc = "Bit 27 - Port Data Direction"]
211    #[inline(always)]
212    pub fn pdd27(&self) -> PddR {
213        PddR::new(((self.bits >> 27) & 1) != 0)
214    }
215    #[doc = "Bit 28 - Port Data Direction"]
216    #[inline(always)]
217    pub fn pdd28(&self) -> PddR {
218        PddR::new(((self.bits >> 28) & 1) != 0)
219    }
220    #[doc = "Bit 29 - Port Data Direction"]
221    #[inline(always)]
222    pub fn pdd29(&self) -> PddR {
223        PddR::new(((self.bits >> 29) & 1) != 0)
224    }
225    #[doc = "Bit 30 - Port Data Direction"]
226    #[inline(always)]
227    pub fn pdd30(&self) -> PddR {
228        PddR::new(((self.bits >> 30) & 1) != 0)
229    }
230    #[doc = "Bit 31 - Port Data Direction"]
231    #[inline(always)]
232    pub fn pdd31(&self) -> PddR {
233        PddR::new(((self.bits >> 31) & 1) != 0)
234    }
235}
236#[cfg(feature = "debug")]
237impl core::fmt::Debug for R {
238    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
239        f.debug_struct("PDDR")
240            .field("pdd0", &self.pdd0())
241            .field("pdd1", &self.pdd1())
242            .field("pdd2", &self.pdd2())
243            .field("pdd3", &self.pdd3())
244            .field("pdd4", &self.pdd4())
245            .field("pdd5", &self.pdd5())
246            .field("pdd6", &self.pdd6())
247            .field("pdd7", &self.pdd7())
248            .field("pdd8", &self.pdd8())
249            .field("pdd9", &self.pdd9())
250            .field("pdd10", &self.pdd10())
251            .field("pdd11", &self.pdd11())
252            .field("pdd12", &self.pdd12())
253            .field("pdd13", &self.pdd13())
254            .field("pdd14", &self.pdd14())
255            .field("pdd15", &self.pdd15())
256            .field("pdd16", &self.pdd16())
257            .field("pdd17", &self.pdd17())
258            .field("pdd18", &self.pdd18())
259            .field("pdd19", &self.pdd19())
260            .field("pdd20", &self.pdd20())
261            .field("pdd21", &self.pdd21())
262            .field("pdd22", &self.pdd22())
263            .field("pdd23", &self.pdd23())
264            .field("pdd24", &self.pdd24())
265            .field("pdd25", &self.pdd25())
266            .field("pdd26", &self.pdd26())
267            .field("pdd27", &self.pdd27())
268            .field("pdd28", &self.pdd28())
269            .field("pdd29", &self.pdd29())
270            .field("pdd30", &self.pdd30())
271            .field("pdd31", &self.pdd31())
272            .finish()
273    }
274}
275impl W {
276    #[doc = "Port Data Direction"]
277    #[doc = ""]
278    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `PDD0` field.</div>"]
279    #[inline(always)]
280    pub fn pdd(&mut self, n: u8) -> PddW<'_, PddrSpec> {
281        #[allow(clippy::no_effect)]
282        [(); 32][n as usize];
283        PddW::new(self, n)
284    }
285    #[doc = "Bit 0 - Port Data Direction"]
286    #[inline(always)]
287    pub fn pdd0(&mut self) -> PddW<'_, PddrSpec> {
288        PddW::new(self, 0)
289    }
290    #[doc = "Bit 1 - Port Data Direction"]
291    #[inline(always)]
292    pub fn pdd1(&mut self) -> PddW<'_, PddrSpec> {
293        PddW::new(self, 1)
294    }
295    #[doc = "Bit 2 - Port Data Direction"]
296    #[inline(always)]
297    pub fn pdd2(&mut self) -> PddW<'_, PddrSpec> {
298        PddW::new(self, 2)
299    }
300    #[doc = "Bit 3 - Port Data Direction"]
301    #[inline(always)]
302    pub fn pdd3(&mut self) -> PddW<'_, PddrSpec> {
303        PddW::new(self, 3)
304    }
305    #[doc = "Bit 4 - Port Data Direction"]
306    #[inline(always)]
307    pub fn pdd4(&mut self) -> PddW<'_, PddrSpec> {
308        PddW::new(self, 4)
309    }
310    #[doc = "Bit 5 - Port Data Direction"]
311    #[inline(always)]
312    pub fn pdd5(&mut self) -> PddW<'_, PddrSpec> {
313        PddW::new(self, 5)
314    }
315    #[doc = "Bit 6 - Port Data Direction"]
316    #[inline(always)]
317    pub fn pdd6(&mut self) -> PddW<'_, PddrSpec> {
318        PddW::new(self, 6)
319    }
320    #[doc = "Bit 7 - Port Data Direction"]
321    #[inline(always)]
322    pub fn pdd7(&mut self) -> PddW<'_, PddrSpec> {
323        PddW::new(self, 7)
324    }
325    #[doc = "Bit 8 - Port Data Direction"]
326    #[inline(always)]
327    pub fn pdd8(&mut self) -> PddW<'_, PddrSpec> {
328        PddW::new(self, 8)
329    }
330    #[doc = "Bit 9 - Port Data Direction"]
331    #[inline(always)]
332    pub fn pdd9(&mut self) -> PddW<'_, PddrSpec> {
333        PddW::new(self, 9)
334    }
335    #[doc = "Bit 10 - Port Data Direction"]
336    #[inline(always)]
337    pub fn pdd10(&mut self) -> PddW<'_, PddrSpec> {
338        PddW::new(self, 10)
339    }
340    #[doc = "Bit 11 - Port Data Direction"]
341    #[inline(always)]
342    pub fn pdd11(&mut self) -> PddW<'_, PddrSpec> {
343        PddW::new(self, 11)
344    }
345    #[doc = "Bit 12 - Port Data Direction"]
346    #[inline(always)]
347    pub fn pdd12(&mut self) -> PddW<'_, PddrSpec> {
348        PddW::new(self, 12)
349    }
350    #[doc = "Bit 13 - Port Data Direction"]
351    #[inline(always)]
352    pub fn pdd13(&mut self) -> PddW<'_, PddrSpec> {
353        PddW::new(self, 13)
354    }
355    #[doc = "Bit 14 - Port Data Direction"]
356    #[inline(always)]
357    pub fn pdd14(&mut self) -> PddW<'_, PddrSpec> {
358        PddW::new(self, 14)
359    }
360    #[doc = "Bit 15 - Port Data Direction"]
361    #[inline(always)]
362    pub fn pdd15(&mut self) -> PddW<'_, PddrSpec> {
363        PddW::new(self, 15)
364    }
365    #[doc = "Bit 16 - Port Data Direction"]
366    #[inline(always)]
367    pub fn pdd16(&mut self) -> PddW<'_, PddrSpec> {
368        PddW::new(self, 16)
369    }
370    #[doc = "Bit 17 - Port Data Direction"]
371    #[inline(always)]
372    pub fn pdd17(&mut self) -> PddW<'_, PddrSpec> {
373        PddW::new(self, 17)
374    }
375    #[doc = "Bit 18 - Port Data Direction"]
376    #[inline(always)]
377    pub fn pdd18(&mut self) -> PddW<'_, PddrSpec> {
378        PddW::new(self, 18)
379    }
380    #[doc = "Bit 19 - Port Data Direction"]
381    #[inline(always)]
382    pub fn pdd19(&mut self) -> PddW<'_, PddrSpec> {
383        PddW::new(self, 19)
384    }
385    #[doc = "Bit 20 - Port Data Direction"]
386    #[inline(always)]
387    pub fn pdd20(&mut self) -> PddW<'_, PddrSpec> {
388        PddW::new(self, 20)
389    }
390    #[doc = "Bit 21 - Port Data Direction"]
391    #[inline(always)]
392    pub fn pdd21(&mut self) -> PddW<'_, PddrSpec> {
393        PddW::new(self, 21)
394    }
395    #[doc = "Bit 22 - Port Data Direction"]
396    #[inline(always)]
397    pub fn pdd22(&mut self) -> PddW<'_, PddrSpec> {
398        PddW::new(self, 22)
399    }
400    #[doc = "Bit 23 - Port Data Direction"]
401    #[inline(always)]
402    pub fn pdd23(&mut self) -> PddW<'_, PddrSpec> {
403        PddW::new(self, 23)
404    }
405    #[doc = "Bit 24 - Port Data Direction"]
406    #[inline(always)]
407    pub fn pdd24(&mut self) -> PddW<'_, PddrSpec> {
408        PddW::new(self, 24)
409    }
410    #[doc = "Bit 25 - Port Data Direction"]
411    #[inline(always)]
412    pub fn pdd25(&mut self) -> PddW<'_, PddrSpec> {
413        PddW::new(self, 25)
414    }
415    #[doc = "Bit 26 - Port Data Direction"]
416    #[inline(always)]
417    pub fn pdd26(&mut self) -> PddW<'_, PddrSpec> {
418        PddW::new(self, 26)
419    }
420    #[doc = "Bit 27 - Port Data Direction"]
421    #[inline(always)]
422    pub fn pdd27(&mut self) -> PddW<'_, PddrSpec> {
423        PddW::new(self, 27)
424    }
425    #[doc = "Bit 28 - Port Data Direction"]
426    #[inline(always)]
427    pub fn pdd28(&mut self) -> PddW<'_, PddrSpec> {
428        PddW::new(self, 28)
429    }
430    #[doc = "Bit 29 - Port Data Direction"]
431    #[inline(always)]
432    pub fn pdd29(&mut self) -> PddW<'_, PddrSpec> {
433        PddW::new(self, 29)
434    }
435    #[doc = "Bit 30 - Port Data Direction"]
436    #[inline(always)]
437    pub fn pdd30(&mut self) -> PddW<'_, PddrSpec> {
438        PddW::new(self, 30)
439    }
440    #[doc = "Bit 31 - Port Data Direction"]
441    #[inline(always)]
442    pub fn pdd31(&mut self) -> PddW<'_, PddrSpec> {
443        PddW::new(self, 31)
444    }
445}
446#[doc = "Port Data Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
447pub struct PddrSpec;
448impl crate::RegisterSpec for PddrSpec {
449    type Ux = u32;
450}
451#[doc = "`read()` method returns [`pddr::R`](R) reader structure"]
452impl crate::Readable for PddrSpec {}
453#[doc = "`write(|w| ..)` method takes [`pddr::W`](W) writer structure"]
454impl crate::Writable for PddrSpec {
455    type Safety = crate::Unsafe;
456}
457#[doc = "`reset()` method sets PDDR to value 0"]
458impl crate::Resettable for PddrSpec {}
mcxa_pac/gpio0/pddr.rs

mcxa_pac/gpio0/
pddr.rs
