mcxa_pac/erm0/
cr0.rs

1#[doc = "Register `CR0` reader"]
2pub type R = crate::R<Cr0Spec>;
3#[doc = "Register `CR0` writer"]
4pub type W = crate::W<Cr0Spec>;
5#[doc = "ENCIE1\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Encie1 {
9    #[doc = "0: Interrupt notification of Memory 1 non-correctable error events is disabled."]
10    Disable = 0,
11    #[doc = "1: Interrupt notification of Memory 1 non-correctable error events is enabled."]
12    Enable = 1,
13}
14impl From<Encie1> for bool {
15    #[inline(always)]
16    fn from(variant: Encie1) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `ENCIE1` reader - ENCIE1"]
21pub type Encie1R = crate::BitReader<Encie1>;
22impl Encie1R {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Encie1 {
26        match self.bits {
27            false => Encie1::Disable,
28            true => Encie1::Enable,
29        }
30    }
31    #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Encie1::Disable
35    }
36    #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Encie1::Enable
40    }
41}
42#[doc = "Field `ENCIE1` writer - ENCIE1"]
43pub type Encie1W<'a, REG> = crate::BitWriter<'a, REG, Encie1>;
44impl<'a, REG> Encie1W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Interrupt notification of Memory 1 non-correctable error events is disabled."]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Encie1::Disable)
52    }
53    #[doc = "Interrupt notification of Memory 1 non-correctable error events is enabled."]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Encie1::Enable)
57    }
58}
59#[doc = "ESCIE1\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Escie1 {
63    #[doc = "0: Interrupt notification of Memory 1 single-bit correction events is disabled."]
64    Disable = 0,
65    #[doc = "1: Interrupt notification of Memory 1 single-bit correction events is enabled."]
66    Enable = 1,
67}
68impl From<Escie1> for bool {
69    #[inline(always)]
70    fn from(variant: Escie1) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ESCIE1` reader - ESCIE1"]
75pub type Escie1R = crate::BitReader<Escie1>;
76impl Escie1R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Escie1 {
80        match self.bits {
81            false => Escie1::Disable,
82            true => Escie1::Enable,
83        }
84    }
85    #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Escie1::Disable
89    }
90    #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Escie1::Enable
94    }
95}
96#[doc = "Field `ESCIE1` writer - ESCIE1"]
97pub type Escie1W<'a, REG> = crate::BitWriter<'a, REG, Escie1>;
98impl<'a, REG> Escie1W<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Interrupt notification of Memory 1 single-bit correction events is disabled."]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Escie1::Disable)
106    }
107    #[doc = "Interrupt notification of Memory 1 single-bit correction events is enabled."]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Escie1::Enable)
111    }
112}
113#[doc = "ENCIE0\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Encie0 {
117    #[doc = "0: Interrupt notification of Memory 0 non-correctable error events is disabled."]
118    Disable = 0,
119    #[doc = "1: Interrupt notification of Memory 0 non-correctable error events is enabled."]
120    Enable = 1,
121}
122impl From<Encie0> for bool {
123    #[inline(always)]
124    fn from(variant: Encie0) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `ENCIE0` reader - ENCIE0"]
129pub type Encie0R = crate::BitReader<Encie0>;
130impl Encie0R {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Encie0 {
134        match self.bits {
135            false => Encie0::Disable,
136            true => Encie0::Enable,
137        }
138    }
139    #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Encie0::Disable
143    }
144    #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Encie0::Enable
148    }
149}
150#[doc = "Field `ENCIE0` writer - ENCIE0"]
151pub type Encie0W<'a, REG> = crate::BitWriter<'a, REG, Encie0>;
152impl<'a, REG> Encie0W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Interrupt notification of Memory 0 non-correctable error events is disabled."]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Encie0::Disable)
160    }
161    #[doc = "Interrupt notification of Memory 0 non-correctable error events is enabled."]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Encie0::Enable)
165    }
166}
167#[doc = "ESCIE0\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Escie0 {
171    #[doc = "0: Interrupt notification of Memory 0 single-bit correction events is disabled."]
172    Disable = 0,
173    #[doc = "1: Interrupt notification of Memory 0 single-bit correction events is enabled."]
174    Enable = 1,
175}
176impl From<Escie0> for bool {
177    #[inline(always)]
178    fn from(variant: Escie0) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `ESCIE0` reader - ESCIE0"]
183pub type Escie0R = crate::BitReader<Escie0>;
184impl Escie0R {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Escie0 {
188        match self.bits {
189            false => Escie0::Disable,
190            true => Escie0::Enable,
191        }
192    }
193    #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Escie0::Disable
197    }
198    #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Escie0::Enable
202    }
203}
204#[doc = "Field `ESCIE0` writer - ESCIE0"]
205pub type Escie0W<'a, REG> = crate::BitWriter<'a, REG, Escie0>;
206impl<'a, REG> Escie0W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Interrupt notification of Memory 0 single-bit correction events is disabled."]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Escie0::Disable)
214    }
215    #[doc = "Interrupt notification of Memory 0 single-bit correction events is enabled."]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Escie0::Enable)
219    }
220}
221impl R {
222    #[doc = "Bit 26 - ENCIE1"]
223    #[inline(always)]
224    pub fn encie1(&self) -> Encie1R {
225        Encie1R::new(((self.bits >> 26) & 1) != 0)
226    }
227    #[doc = "Bit 27 - ESCIE1"]
228    #[inline(always)]
229    pub fn escie1(&self) -> Escie1R {
230        Escie1R::new(((self.bits >> 27) & 1) != 0)
231    }
232    #[doc = "Bit 30 - ENCIE0"]
233    #[inline(always)]
234    pub fn encie0(&self) -> Encie0R {
235        Encie0R::new(((self.bits >> 30) & 1) != 0)
236    }
237    #[doc = "Bit 31 - ESCIE0"]
238    #[inline(always)]
239    pub fn escie0(&self) -> Escie0R {
240        Escie0R::new(((self.bits >> 31) & 1) != 0)
241    }
242}
243#[cfg(feature = "debug")]
244impl core::fmt::Debug for R {
245    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
246        f.debug_struct("CR0")
247            .field("encie1", &self.encie1())
248            .field("escie1", &self.escie1())
249            .field("encie0", &self.encie0())
250            .field("escie0", &self.escie0())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bit 26 - ENCIE1"]
256    #[inline(always)]
257    pub fn encie1(&mut self) -> Encie1W<'_, Cr0Spec> {
258        Encie1W::new(self, 26)
259    }
260    #[doc = "Bit 27 - ESCIE1"]
261    #[inline(always)]
262    pub fn escie1(&mut self) -> Escie1W<'_, Cr0Spec> {
263        Escie1W::new(self, 27)
264    }
265    #[doc = "Bit 30 - ENCIE0"]
266    #[inline(always)]
267    pub fn encie0(&mut self) -> Encie0W<'_, Cr0Spec> {
268        Encie0W::new(self, 30)
269    }
270    #[doc = "Bit 31 - ESCIE0"]
271    #[inline(always)]
272    pub fn escie0(&mut self) -> Escie0W<'_, Cr0Spec> {
273        Escie0W::new(self, 31)
274    }
275}
276#[doc = "ERM Configuration Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct Cr0Spec;
278impl crate::RegisterSpec for Cr0Spec {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`cr0::R`](R) reader structure"]
282impl crate::Readable for Cr0Spec {}
283#[doc = "`write(|w| ..)` method takes [`cr0::W`](W) writer structure"]
284impl crate::Writable for Cr0Spec {
285    type Safety = crate::Unsafe;
286}
287#[doc = "`reset()` method sets CR0 to value 0"]
288impl crate::Resettable for Cr0Spec {}
mcxa_pac/erm0/cr0.rs

mcxa_pac/erm0/
cr0.rs
