mcxa_pac/edma_0_tcd0/tcd/
ch_sbr.rs

1#[doc = "Register `CH_SBR` reader"]
2pub type R = crate::R<ChSbrSpec>;
3#[doc = "Register `CH_SBR` writer"]
4pub type W = crate::W<ChSbrSpec>;
5#[doc = "Field `MID` reader - Master ID"]
6pub type MidR = crate::FieldReader;
7#[doc = "Privileged Access Level\n\nValue on reset: 0"]
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum Pal {
11    #[doc = "0: User protection level for DMA transfers"]
12    UserProtection = 0,
13    #[doc = "1: Privileged protection level for DMA transfers"]
14    PrivilegedProtection = 1,
15}
16impl From<Pal> for bool {
17    #[inline(always)]
18    fn from(variant: Pal) -> Self {
19        variant as u8 != 0
20    }
21}
22#[doc = "Field `PAL` reader - Privileged Access Level"]
23pub type PalR = crate::BitReader<Pal>;
24impl PalR {
25    #[doc = "Get enumerated values variant"]
26    #[inline(always)]
27    pub const fn variant(&self) -> Pal {
28        match self.bits {
29            false => Pal::UserProtection,
30            true => Pal::PrivilegedProtection,
31        }
32    }
33    #[doc = "User protection level for DMA transfers"]
34    #[inline(always)]
35    pub fn is_user_protection(&self) -> bool {
36        *self == Pal::UserProtection
37    }
38    #[doc = "Privileged protection level for DMA transfers"]
39    #[inline(always)]
40    pub fn is_privileged_protection(&self) -> bool {
41        *self == Pal::PrivilegedProtection
42    }
43}
44#[doc = "Enable Master ID Replication\n\nValue on reset: 0"]
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum Emi {
48    #[doc = "0: Master ID replication is disabled"]
49    Disable = 0,
50    #[doc = "1: Master ID replication is enabled"]
51    Enable = 1,
52}
53impl From<Emi> for bool {
54    #[inline(always)]
55    fn from(variant: Emi) -> Self {
56        variant as u8 != 0
57    }
58}
59#[doc = "Field `EMI` reader - Enable Master ID Replication"]
60pub type EmiR = crate::BitReader<Emi>;
61impl EmiR {
62    #[doc = "Get enumerated values variant"]
63    #[inline(always)]
64    pub const fn variant(&self) -> Emi {
65        match self.bits {
66            false => Emi::Disable,
67            true => Emi::Enable,
68        }
69    }
70    #[doc = "Master ID replication is disabled"]
71    #[inline(always)]
72    pub fn is_disable(&self) -> bool {
73        *self == Emi::Disable
74    }
75    #[doc = "Master ID replication is enabled"]
76    #[inline(always)]
77    pub fn is_enable(&self) -> bool {
78        *self == Emi::Enable
79    }
80}
81#[doc = "Field `EMI` writer - Enable Master ID Replication"]
82pub type EmiW<'a, REG> = crate::BitWriter<'a, REG, Emi>;
83impl<'a, REG> EmiW<'a, REG>
84where
85    REG: crate::Writable + crate::RegisterSpec,
86{
87    #[doc = "Master ID replication is disabled"]
88    #[inline(always)]
89    pub fn disable(self) -> &'a mut crate::W<REG> {
90        self.variant(Emi::Disable)
91    }
92    #[doc = "Master ID replication is enabled"]
93    #[inline(always)]
94    pub fn enable(self) -> &'a mut crate::W<REG> {
95        self.variant(Emi::Enable)
96    }
97}
98impl R {
99    #[doc = "Bits 0:3 - Master ID"]
100    #[inline(always)]
101    pub fn mid(&self) -> MidR {
102        MidR::new((self.bits & 0x0f) as u8)
103    }
104    #[doc = "Bit 15 - Privileged Access Level"]
105    #[inline(always)]
106    pub fn pal(&self) -> PalR {
107        PalR::new(((self.bits >> 15) & 1) != 0)
108    }
109    #[doc = "Bit 16 - Enable Master ID Replication"]
110    #[inline(always)]
111    pub fn emi(&self) -> EmiR {
112        EmiR::new(((self.bits >> 16) & 1) != 0)
113    }
114}
115#[cfg(feature = "debug")]
116impl core::fmt::Debug for R {
117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118        f.debug_struct("CH_SBR")
119            .field("mid", &self.mid())
120            .field("pal", &self.pal())
121            .field("emi", &self.emi())
122            .finish()
123    }
124}
125impl W {
126    #[doc = "Bit 16 - Enable Master ID Replication"]
127    #[inline(always)]
128    pub fn emi(&mut self) -> EmiW<'_, ChSbrSpec> {
129        EmiW::new(self, 16)
130    }
131}
132#[doc = "Channel System Bus\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_sbr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_sbr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
133pub struct ChSbrSpec;
134impl crate::RegisterSpec for ChSbrSpec {
135    type Ux = u32;
136}
137#[doc = "`read()` method returns [`ch_sbr::R`](R) reader structure"]
138impl crate::Readable for ChSbrSpec {}
139#[doc = "`write(|w| ..)` method takes [`ch_sbr::W`](W) writer structure"]
140impl crate::Writable for ChSbrSpec {
141    type Safety = crate::Unsafe;
142}
143#[doc = "`reset()` method sets CH_SBR to value 0x05"]
144impl crate::Resettable for ChSbrSpec {
145    const RESET_VALUE: u32 = 0x05;
146}
mcxa_pac/edma_0_tcd0/tcd/ch_sbr.rs

mcxa_pac/edma_0_tcd0/tcd/
ch_sbr.rs
