mcxa_pac/dma0/
mp_csr.rs

1#[doc = "Register `MP_CSR` reader"]
2pub type R = crate::R<MpCsrSpec>;
3#[doc = "Register `MP_CSR` writer"]
4pub type W = crate::W<MpCsrSpec>;
5#[doc = "Enable Debug\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Edbg {
9    #[doc = "0: Debug mode disabled"]
10    Disable = 0,
11    #[doc = "1: Debug mode is enabled."]
12    Enable = 1,
13}
14impl From<Edbg> for bool {
15    #[inline(always)]
16    fn from(variant: Edbg) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `EDBG` reader - Enable Debug"]
21pub type EdbgR = crate::BitReader<Edbg>;
22impl EdbgR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Edbg {
26        match self.bits {
27            false => Edbg::Disable,
28            true => Edbg::Enable,
29        }
30    }
31    #[doc = "Debug mode disabled"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Edbg::Disable
35    }
36    #[doc = "Debug mode is enabled."]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Edbg::Enable
40    }
41}
42#[doc = "Field `EDBG` writer - Enable Debug"]
43pub type EdbgW<'a, REG> = crate::BitWriter<'a, REG, Edbg>;
44impl<'a, REG> EdbgW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Debug mode disabled"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Edbg::Disable)
52    }
53    #[doc = "Debug mode is enabled."]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Edbg::Enable)
57    }
58}
59#[doc = "Enable Round Robin Channel Arbitration\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Erca {
63    #[doc = "0: Round-robin channel arbitration disabled"]
64    Disable = 0,
65    #[doc = "1: Round-robin channel arbitration enabled"]
66    Enable = 1,
67}
68impl From<Erca> for bool {
69    #[inline(always)]
70    fn from(variant: Erca) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ERCA` reader - Enable Round Robin Channel Arbitration"]
75pub type ErcaR = crate::BitReader<Erca>;
76impl ErcaR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Erca {
80        match self.bits {
81            false => Erca::Disable,
82            true => Erca::Enable,
83        }
84    }
85    #[doc = "Round-robin channel arbitration disabled"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Erca::Disable
89    }
90    #[doc = "Round-robin channel arbitration enabled"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Erca::Enable
94    }
95}
96#[doc = "Field `ERCA` writer - Enable Round Robin Channel Arbitration"]
97pub type ErcaW<'a, REG> = crate::BitWriter<'a, REG, Erca>;
98impl<'a, REG> ErcaW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Round-robin channel arbitration disabled"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Erca::Disable)
106    }
107    #[doc = "Round-robin channel arbitration enabled"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Erca::Enable)
111    }
112}
113#[doc = "Halt After Error\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Hae {
117    #[doc = "0: Normal operation"]
118    NormalOperation = 0,
119    #[doc = "1: Any error causes the HALT field to be set to 1"]
120    Halt = 1,
121}
122impl From<Hae> for bool {
123    #[inline(always)]
124    fn from(variant: Hae) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `HAE` reader - Halt After Error"]
129pub type HaeR = crate::BitReader<Hae>;
130impl HaeR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Hae {
134        match self.bits {
135            false => Hae::NormalOperation,
136            true => Hae::Halt,
137        }
138    }
139    #[doc = "Normal operation"]
140    #[inline(always)]
141    pub fn is_normal_operation(&self) -> bool {
142        *self == Hae::NormalOperation
143    }
144    #[doc = "Any error causes the HALT field to be set to 1"]
145    #[inline(always)]
146    pub fn is_halt(&self) -> bool {
147        *self == Hae::Halt
148    }
149}
150#[doc = "Field `HAE` writer - Halt After Error"]
151pub type HaeW<'a, REG> = crate::BitWriter<'a, REG, Hae>;
152impl<'a, REG> HaeW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Normal operation"]
157    #[inline(always)]
158    pub fn normal_operation(self) -> &'a mut crate::W<REG> {
159        self.variant(Hae::NormalOperation)
160    }
161    #[doc = "Any error causes the HALT field to be set to 1"]
162    #[inline(always)]
163    pub fn halt(self) -> &'a mut crate::W<REG> {
164        self.variant(Hae::Halt)
165    }
166}
167#[doc = "Halt DMA Operations\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Halt {
171    #[doc = "0: Normal operation"]
172    NormalOperation = 0,
173    #[doc = "1: Stall the start of any new channels"]
174    Stall = 1,
175}
176impl From<Halt> for bool {
177    #[inline(always)]
178    fn from(variant: Halt) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `HALT` reader - Halt DMA Operations"]
183pub type HaltR = crate::BitReader<Halt>;
184impl HaltR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Halt {
188        match self.bits {
189            false => Halt::NormalOperation,
190            true => Halt::Stall,
191        }
192    }
193    #[doc = "Normal operation"]
194    #[inline(always)]
195    pub fn is_normal_operation(&self) -> bool {
196        *self == Halt::NormalOperation
197    }
198    #[doc = "Stall the start of any new channels"]
199    #[inline(always)]
200    pub fn is_stall(&self) -> bool {
201        *self == Halt::Stall
202    }
203}
204#[doc = "Field `HALT` writer - Halt DMA Operations"]
205pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>;
206impl<'a, REG> HaltW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Normal operation"]
211    #[inline(always)]
212    pub fn normal_operation(self) -> &'a mut crate::W<REG> {
213        self.variant(Halt::NormalOperation)
214    }
215    #[doc = "Stall the start of any new channels"]
216    #[inline(always)]
217    pub fn stall(self) -> &'a mut crate::W<REG> {
218        self.variant(Halt::Stall)
219    }
220}
221#[doc = "Global Channel Linking Control\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Gclc {
225    #[doc = "0: Channel linking disabled for all channels"]
226    Disable = 0,
227    #[doc = "1: Channel linking available and controlled by each channel's link settings"]
228    Available = 1,
229}
230impl From<Gclc> for bool {
231    #[inline(always)]
232    fn from(variant: Gclc) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `GCLC` reader - Global Channel Linking Control"]
237pub type GclcR = crate::BitReader<Gclc>;
238impl GclcR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Gclc {
242        match self.bits {
243            false => Gclc::Disable,
244            true => Gclc::Available,
245        }
246    }
247    #[doc = "Channel linking disabled for all channels"]
248    #[inline(always)]
249    pub fn is_disable(&self) -> bool {
250        *self == Gclc::Disable
251    }
252    #[doc = "Channel linking available and controlled by each channel's link settings"]
253    #[inline(always)]
254    pub fn is_available(&self) -> bool {
255        *self == Gclc::Available
256    }
257}
258#[doc = "Field `GCLC` writer - Global Channel Linking Control"]
259pub type GclcW<'a, REG> = crate::BitWriter<'a, REG, Gclc>;
260impl<'a, REG> GclcW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Channel linking disabled for all channels"]
265    #[inline(always)]
266    pub fn disable(self) -> &'a mut crate::W<REG> {
267        self.variant(Gclc::Disable)
268    }
269    #[doc = "Channel linking available and controlled by each channel's link settings"]
270    #[inline(always)]
271    pub fn available(self) -> &'a mut crate::W<REG> {
272        self.variant(Gclc::Available)
273    }
274}
275#[doc = "Global Master ID Replication Control\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Gmrc {
279    #[doc = "0: Master ID replication disabled for all channels"]
280    Disable = 0,
281    #[doc = "1: Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"]
282    Available = 1,
283}
284impl From<Gmrc> for bool {
285    #[inline(always)]
286    fn from(variant: Gmrc) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `GMRC` reader - Global Master ID Replication Control"]
291pub type GmrcR = crate::BitReader<Gmrc>;
292impl GmrcR {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Gmrc {
296        match self.bits {
297            false => Gmrc::Disable,
298            true => Gmrc::Available,
299        }
300    }
301    #[doc = "Master ID replication disabled for all channels"]
302    #[inline(always)]
303    pub fn is_disable(&self) -> bool {
304        *self == Gmrc::Disable
305    }
306    #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"]
307    #[inline(always)]
308    pub fn is_available(&self) -> bool {
309        *self == Gmrc::Available
310    }
311}
312#[doc = "Field `GMRC` writer - Global Master ID Replication Control"]
313pub type GmrcW<'a, REG> = crate::BitWriter<'a, REG, Gmrc>;
314impl<'a, REG> GmrcW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Master ID replication disabled for all channels"]
319    #[inline(always)]
320    pub fn disable(self) -> &'a mut crate::W<REG> {
321        self.variant(Gmrc::Disable)
322    }
323    #[doc = "Master ID replication available and controlled by each channel's CHn_SBR\\[EMI\\] setting"]
324    #[inline(always)]
325    pub fn available(self) -> &'a mut crate::W<REG> {
326        self.variant(Gmrc::Available)
327    }
328}
329#[doc = "Cancel Transfer With Error\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Ecx {
333    #[doc = "0: Normal operation"]
334    NormalOperation = 0,
335    #[doc = "1: Cancel the remaining data transfer"]
336    Cancel = 1,
337}
338impl From<Ecx> for bool {
339    #[inline(always)]
340    fn from(variant: Ecx) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `ECX` reader - Cancel Transfer With Error"]
345pub type EcxR = crate::BitReader<Ecx>;
346impl EcxR {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Ecx {
350        match self.bits {
351            false => Ecx::NormalOperation,
352            true => Ecx::Cancel,
353        }
354    }
355    #[doc = "Normal operation"]
356    #[inline(always)]
357    pub fn is_normal_operation(&self) -> bool {
358        *self == Ecx::NormalOperation
359    }
360    #[doc = "Cancel the remaining data transfer"]
361    #[inline(always)]
362    pub fn is_cancel(&self) -> bool {
363        *self == Ecx::Cancel
364    }
365}
366#[doc = "Field `ECX` writer - Cancel Transfer With Error"]
367pub type EcxW<'a, REG> = crate::BitWriter<'a, REG, Ecx>;
368impl<'a, REG> EcxW<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "Normal operation"]
373    #[inline(always)]
374    pub fn normal_operation(self) -> &'a mut crate::W<REG> {
375        self.variant(Ecx::NormalOperation)
376    }
377    #[doc = "Cancel the remaining data transfer"]
378    #[inline(always)]
379    pub fn cancel(self) -> &'a mut crate::W<REG> {
380        self.variant(Ecx::Cancel)
381    }
382}
383#[doc = "Cancel Transfer\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Cx {
387    #[doc = "0: Normal operation"]
388    NormalOperation = 0,
389    #[doc = "1: Cancel the remaining data transfer"]
390    DataTransferCancel = 1,
391}
392impl From<Cx> for bool {
393    #[inline(always)]
394    fn from(variant: Cx) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `CX` reader - Cancel Transfer"]
399pub type CxR = crate::BitReader<Cx>;
400impl CxR {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> Cx {
404        match self.bits {
405            false => Cx::NormalOperation,
406            true => Cx::DataTransferCancel,
407        }
408    }
409    #[doc = "Normal operation"]
410    #[inline(always)]
411    pub fn is_normal_operation(&self) -> bool {
412        *self == Cx::NormalOperation
413    }
414    #[doc = "Cancel the remaining data transfer"]
415    #[inline(always)]
416    pub fn is_data_transfer_cancel(&self) -> bool {
417        *self == Cx::DataTransferCancel
418    }
419}
420#[doc = "Field `CX` writer - Cancel Transfer"]
421pub type CxW<'a, REG> = crate::BitWriter<'a, REG, Cx>;
422impl<'a, REG> CxW<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Normal operation"]
427    #[inline(always)]
428    pub fn normal_operation(self) -> &'a mut crate::W<REG> {
429        self.variant(Cx::NormalOperation)
430    }
431    #[doc = "Cancel the remaining data transfer"]
432    #[inline(always)]
433    pub fn data_transfer_cancel(self) -> &'a mut crate::W<REG> {
434        self.variant(Cx::DataTransferCancel)
435    }
436}
437#[doc = "Field `ACTIVE_ID` reader - Active Channel ID"]
438pub type ActiveIdR = crate::FieldReader;
439#[doc = "DMA Active Status\n\nValue on reset: 0"]
440#[cfg_attr(feature = "defmt", derive(defmt::Format))]
441#[derive(Clone, Copy, Debug, PartialEq, Eq)]
442pub enum Active {
443    #[doc = "0: eDMA is idle"]
444    Idle = 0,
445    #[doc = "1: eDMA is executing a channel"]
446    Execution = 1,
447}
448impl From<Active> for bool {
449    #[inline(always)]
450    fn from(variant: Active) -> Self {
451        variant as u8 != 0
452    }
453}
454#[doc = "Field `ACTIVE` reader - DMA Active Status"]
455pub type ActiveR = crate::BitReader<Active>;
456impl ActiveR {
457    #[doc = "Get enumerated values variant"]
458    #[inline(always)]
459    pub const fn variant(&self) -> Active {
460        match self.bits {
461            false => Active::Idle,
462            true => Active::Execution,
463        }
464    }
465    #[doc = "eDMA is idle"]
466    #[inline(always)]
467    pub fn is_idle(&self) -> bool {
468        *self == Active::Idle
469    }
470    #[doc = "eDMA is executing a channel"]
471    #[inline(always)]
472    pub fn is_execution(&self) -> bool {
473        *self == Active::Execution
474    }
475}
476impl R {
477    #[doc = "Bit 1 - Enable Debug"]
478    #[inline(always)]
479    pub fn edbg(&self) -> EdbgR {
480        EdbgR::new(((self.bits >> 1) & 1) != 0)
481    }
482    #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"]
483    #[inline(always)]
484    pub fn erca(&self) -> ErcaR {
485        ErcaR::new(((self.bits >> 2) & 1) != 0)
486    }
487    #[doc = "Bit 4 - Halt After Error"]
488    #[inline(always)]
489    pub fn hae(&self) -> HaeR {
490        HaeR::new(((self.bits >> 4) & 1) != 0)
491    }
492    #[doc = "Bit 5 - Halt DMA Operations"]
493    #[inline(always)]
494    pub fn halt(&self) -> HaltR {
495        HaltR::new(((self.bits >> 5) & 1) != 0)
496    }
497    #[doc = "Bit 6 - Global Channel Linking Control"]
498    #[inline(always)]
499    pub fn gclc(&self) -> GclcR {
500        GclcR::new(((self.bits >> 6) & 1) != 0)
501    }
502    #[doc = "Bit 7 - Global Master ID Replication Control"]
503    #[inline(always)]
504    pub fn gmrc(&self) -> GmrcR {
505        GmrcR::new(((self.bits >> 7) & 1) != 0)
506    }
507    #[doc = "Bit 8 - Cancel Transfer With Error"]
508    #[inline(always)]
509    pub fn ecx(&self) -> EcxR {
510        EcxR::new(((self.bits >> 8) & 1) != 0)
511    }
512    #[doc = "Bit 9 - Cancel Transfer"]
513    #[inline(always)]
514    pub fn cx(&self) -> CxR {
515        CxR::new(((self.bits >> 9) & 1) != 0)
516    }
517    #[doc = "Bits 24:26 - Active Channel ID"]
518    #[inline(always)]
519    pub fn active_id(&self) -> ActiveIdR {
520        ActiveIdR::new(((self.bits >> 24) & 7) as u8)
521    }
522    #[doc = "Bit 31 - DMA Active Status"]
523    #[inline(always)]
524    pub fn active(&self) -> ActiveR {
525        ActiveR::new(((self.bits >> 31) & 1) != 0)
526    }
527}
528#[cfg(feature = "debug")]
529impl core::fmt::Debug for R {
530    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
531        f.debug_struct("MP_CSR")
532            .field("edbg", &self.edbg())
533            .field("erca", &self.erca())
534            .field("hae", &self.hae())
535            .field("halt", &self.halt())
536            .field("gclc", &self.gclc())
537            .field("gmrc", &self.gmrc())
538            .field("ecx", &self.ecx())
539            .field("cx", &self.cx())
540            .field("active_id", &self.active_id())
541            .field("active", &self.active())
542            .finish()
543    }
544}
545impl W {
546    #[doc = "Bit 1 - Enable Debug"]
547    #[inline(always)]
548    pub fn edbg(&mut self) -> EdbgW<'_, MpCsrSpec> {
549        EdbgW::new(self, 1)
550    }
551    #[doc = "Bit 2 - Enable Round Robin Channel Arbitration"]
552    #[inline(always)]
553    pub fn erca(&mut self) -> ErcaW<'_, MpCsrSpec> {
554        ErcaW::new(self, 2)
555    }
556    #[doc = "Bit 4 - Halt After Error"]
557    #[inline(always)]
558    pub fn hae(&mut self) -> HaeW<'_, MpCsrSpec> {
559        HaeW::new(self, 4)
560    }
561    #[doc = "Bit 5 - Halt DMA Operations"]
562    #[inline(always)]
563    pub fn halt(&mut self) -> HaltW<'_, MpCsrSpec> {
564        HaltW::new(self, 5)
565    }
566    #[doc = "Bit 6 - Global Channel Linking Control"]
567    #[inline(always)]
568    pub fn gclc(&mut self) -> GclcW<'_, MpCsrSpec> {
569        GclcW::new(self, 6)
570    }
571    #[doc = "Bit 7 - Global Master ID Replication Control"]
572    #[inline(always)]
573    pub fn gmrc(&mut self) -> GmrcW<'_, MpCsrSpec> {
574        GmrcW::new(self, 7)
575    }
576    #[doc = "Bit 8 - Cancel Transfer With Error"]
577    #[inline(always)]
578    pub fn ecx(&mut self) -> EcxW<'_, MpCsrSpec> {
579        EcxW::new(self, 8)
580    }
581    #[doc = "Bit 9 - Cancel Transfer"]
582    #[inline(always)]
583    pub fn cx(&mut self) -> CxW<'_, MpCsrSpec> {
584        CxW::new(self, 9)
585    }
586}
587#[doc = "Management Page Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mp_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mp_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
588pub struct MpCsrSpec;
589impl crate::RegisterSpec for MpCsrSpec {
590    type Ux = u32;
591}
592#[doc = "`read()` method returns [`mp_csr::R`](R) reader structure"]
593impl crate::Readable for MpCsrSpec {}
594#[doc = "`write(|w| ..)` method takes [`mp_csr::W`](W) writer structure"]
595impl crate::Writable for MpCsrSpec {
596    type Safety = crate::Unsafe;
597}
598#[doc = "`reset()` method sets MP_CSR to value 0x0031_0000"]
599impl crate::Resettable for MpCsrSpec {
600    const RESET_VALUE: u32 = 0x0031_0000;
601}
mcxa_pac/dma0/mp_csr.rs

mcxa_pac/dma0/
mp_csr.rs
