mcxa_pac/cmp0/
rrcr2.rs

1#[doc = "Register `RRCR2` reader"]
2pub type R = crate::R<Rrcr2Spec>;
3#[doc = "Register `RRCR2` writer"]
4pub type W = crate::W<Rrcr2Spec>;
5#[doc = "Field `RR_TIMER_RELOAD` reader - Number of Sample Clocks"]
6pub type RrTimerReloadR = crate::FieldReader<u32>;
7#[doc = "Field `RR_TIMER_RELOAD` writer - Number of Sample Clocks"]
8pub type RrTimerReloadW<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
9#[doc = "Round-Robin Internal Timer Enable\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum RrTimerEn {
13    #[doc = "0: Disables"]
14    Disable = 0,
15    #[doc = "1: Enables"]
16    Enable = 1,
17}
18impl From<RrTimerEn> for bool {
19    #[inline(always)]
20    fn from(variant: RrTimerEn) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `RR_TIMER_EN` reader - Round-Robin Internal Timer Enable"]
25pub type RrTimerEnR = crate::BitReader<RrTimerEn>;
26impl RrTimerEnR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> RrTimerEn {
30        match self.bits {
31            false => RrTimerEn::Disable,
32            true => RrTimerEn::Enable,
33        }
34    }
35    #[doc = "Disables"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == RrTimerEn::Disable
39    }
40    #[doc = "Enables"]
41    #[inline(always)]
42    pub fn is_enable(&self) -> bool {
43        *self == RrTimerEn::Enable
44    }
45}
46#[doc = "Field `RR_TIMER_EN` writer - Round-Robin Internal Timer Enable"]
47pub type RrTimerEnW<'a, REG> = crate::BitWriter<'a, REG, RrTimerEn>;
48impl<'a, REG> RrTimerEnW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Disables"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(RrTimerEn::Disable)
56    }
57    #[doc = "Enables"]
58    #[inline(always)]
59    pub fn enable(self) -> &'a mut crate::W<REG> {
60        self.variant(RrTimerEn::Enable)
61    }
62}
63impl R {
64    #[doc = "Bits 0:27 - Number of Sample Clocks"]
65    #[inline(always)]
66    pub fn rr_timer_reload(&self) -> RrTimerReloadR {
67        RrTimerReloadR::new(self.bits & 0x0fff_ffff)
68    }
69    #[doc = "Bit 31 - Round-Robin Internal Timer Enable"]
70    #[inline(always)]
71    pub fn rr_timer_en(&self) -> RrTimerEnR {
72        RrTimerEnR::new(((self.bits >> 31) & 1) != 0)
73    }
74}
75#[cfg(feature = "debug")]
76impl core::fmt::Debug for R {
77    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78        f.debug_struct("RRCR2")
79            .field("rr_timer_reload", &self.rr_timer_reload())
80            .field("rr_timer_en", &self.rr_timer_en())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:27 - Number of Sample Clocks"]
86    #[inline(always)]
87    pub fn rr_timer_reload(&mut self) -> RrTimerReloadW<'_, Rrcr2Spec> {
88        RrTimerReloadW::new(self, 0)
89    }
90    #[doc = "Bit 31 - Round-Robin Internal Timer Enable"]
91    #[inline(always)]
92    pub fn rr_timer_en(&mut self) -> RrTimerEnW<'_, Rrcr2Spec> {
93        RrTimerEnW::new(self, 31)
94    }
95}
96#[doc = "Round Robin Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`rrcr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rrcr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct Rrcr2Spec;
98impl crate::RegisterSpec for Rrcr2Spec {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`rrcr2::R`](R) reader structure"]
102impl crate::Readable for Rrcr2Spec {}
103#[doc = "`write(|w| ..)` method takes [`rrcr2::W`](W) writer structure"]
104impl crate::Writable for Rrcr2Spec {
105    type Safety = crate::Unsafe;
106}
107#[doc = "`reset()` method sets RRCR2 to value 0"]
108impl crate::Resettable for Rrcr2Spec {}
mcxa_pac/cmp0/rrcr2.rs

mcxa_pac/cmp0/
rrcr2.rs
