mcxa_pac/cmp0/
ccr2.rs

1#[doc = "Register `CCR2` reader"]
2pub type R = crate::R<Ccr2Spec>;
3#[doc = "Register `CCR2` writer"]
4pub type W = crate::W<Ccr2Spec>;
5#[doc = "CMP High Power Mode Select\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CmpHpmd {
9    #[doc = "0: Low power (speed) comparison mode"]
10    Low = 0,
11    #[doc = "1: High power (speed) comparison mode"]
12    High = 1,
13}
14impl From<CmpHpmd> for bool {
15    #[inline(always)]
16    fn from(variant: CmpHpmd) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `CMP_HPMD` reader - CMP High Power Mode Select"]
21pub type CmpHpmdR = crate::BitReader<CmpHpmd>;
22impl CmpHpmdR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> CmpHpmd {
26        match self.bits {
27            false => CmpHpmd::Low,
28            true => CmpHpmd::High,
29        }
30    }
31    #[doc = "Low power (speed) comparison mode"]
32    #[inline(always)]
33    pub fn is_low(&self) -> bool {
34        *self == CmpHpmd::Low
35    }
36    #[doc = "High power (speed) comparison mode"]
37    #[inline(always)]
38    pub fn is_high(&self) -> bool {
39        *self == CmpHpmd::High
40    }
41}
42#[doc = "Field `CMP_HPMD` writer - CMP High Power Mode Select"]
43pub type CmpHpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpHpmd>;
44impl<'a, REG> CmpHpmdW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Low power (speed) comparison mode"]
49    #[inline(always)]
50    pub fn low(self) -> &'a mut crate::W<REG> {
51        self.variant(CmpHpmd::Low)
52    }
53    #[doc = "High power (speed) comparison mode"]
54    #[inline(always)]
55    pub fn high(self) -> &'a mut crate::W<REG> {
56        self.variant(CmpHpmd::High)
57    }
58}
59#[doc = "CMP Nano Power Mode Select\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CmpNpmd {
63    #[doc = "0: Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."]
64    NoNano = 0,
65    #[doc = "1: Enables CMP Nano power mode."]
66    Nano = 1,
67}
68impl From<CmpNpmd> for bool {
69    #[inline(always)]
70    fn from(variant: CmpNpmd) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `CMP_NPMD` reader - CMP Nano Power Mode Select"]
75pub type CmpNpmdR = crate::BitReader<CmpNpmd>;
76impl CmpNpmdR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> CmpNpmd {
80        match self.bits {
81            false => CmpNpmd::NoNano,
82            true => CmpNpmd::Nano,
83        }
84    }
85    #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."]
86    #[inline(always)]
87    pub fn is_no_nano(&self) -> bool {
88        *self == CmpNpmd::NoNano
89    }
90    #[doc = "Enables CMP Nano power mode."]
91    #[inline(always)]
92    pub fn is_nano(&self) -> bool {
93        *self == CmpNpmd::Nano
94    }
95}
96#[doc = "Field `CMP_NPMD` writer - CMP Nano Power Mode Select"]
97pub type CmpNpmdW<'a, REG> = crate::BitWriter<'a, REG, CmpNpmd>;
98impl<'a, REG> CmpNpmdW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disables CMP Nano power mode. CCR2\\[CMP_HPMD\\] determines the mode for the comparator."]
103    #[inline(always)]
104    pub fn no_nano(self) -> &'a mut crate::W<REG> {
105        self.variant(CmpNpmd::NoNano)
106    }
107    #[doc = "Enables CMP Nano power mode."]
108    #[inline(always)]
109    pub fn nano(self) -> &'a mut crate::W<REG> {
110        self.variant(CmpNpmd::Nano)
111    }
112}
113#[doc = "Comparator Hysteresis Control\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116#[repr(u8)]
117pub enum Hystctr {
118    #[doc = "0: Level 0: Analog comparator hysteresis 0 mV."]
119    Level0 = 0,
120    #[doc = "1: Level 1: Analog comparator hysteresis 10 mV."]
121    Level1 = 1,
122    #[doc = "2: Level 2: Analog comparator hysteresis 20 mV."]
123    Level2 = 2,
124    #[doc = "3: Level 3: Analog comparator hysteresis 30 mV."]
125    Level3 = 3,
126}
127impl From<Hystctr> for u8 {
128    #[inline(always)]
129    fn from(variant: Hystctr) -> Self {
130        variant as _
131    }
132}
133impl crate::FieldSpec for Hystctr {
134    type Ux = u8;
135}
136impl crate::IsEnum for Hystctr {}
137#[doc = "Field `HYSTCTR` reader - Comparator Hysteresis Control"]
138pub type HystctrR = crate::FieldReader<Hystctr>;
139impl HystctrR {
140    #[doc = "Get enumerated values variant"]
141    #[inline(always)]
142    pub const fn variant(&self) -> Hystctr {
143        match self.bits {
144            0 => Hystctr::Level0,
145            1 => Hystctr::Level1,
146            2 => Hystctr::Level2,
147            3 => Hystctr::Level3,
148            _ => unreachable!(),
149        }
150    }
151    #[doc = "Level 0: Analog comparator hysteresis 0 mV."]
152    #[inline(always)]
153    pub fn is_level_0(&self) -> bool {
154        *self == Hystctr::Level0
155    }
156    #[doc = "Level 1: Analog comparator hysteresis 10 mV."]
157    #[inline(always)]
158    pub fn is_level_1(&self) -> bool {
159        *self == Hystctr::Level1
160    }
161    #[doc = "Level 2: Analog comparator hysteresis 20 mV."]
162    #[inline(always)]
163    pub fn is_level_2(&self) -> bool {
164        *self == Hystctr::Level2
165    }
166    #[doc = "Level 3: Analog comparator hysteresis 30 mV."]
167    #[inline(always)]
168    pub fn is_level_3(&self) -> bool {
169        *self == Hystctr::Level3
170    }
171}
172#[doc = "Field `HYSTCTR` writer - Comparator Hysteresis Control"]
173pub type HystctrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hystctr, crate::Safe>;
174impl<'a, REG> HystctrW<'a, REG>
175where
176    REG: crate::Writable + crate::RegisterSpec,
177    REG::Ux: From<u8>,
178{
179    #[doc = "Level 0: Analog comparator hysteresis 0 mV."]
180    #[inline(always)]
181    pub fn level_0(self) -> &'a mut crate::W<REG> {
182        self.variant(Hystctr::Level0)
183    }
184    #[doc = "Level 1: Analog comparator hysteresis 10 mV."]
185    #[inline(always)]
186    pub fn level_1(self) -> &'a mut crate::W<REG> {
187        self.variant(Hystctr::Level1)
188    }
189    #[doc = "Level 2: Analog comparator hysteresis 20 mV."]
190    #[inline(always)]
191    pub fn level_2(self) -> &'a mut crate::W<REG> {
192        self.variant(Hystctr::Level2)
193    }
194    #[doc = "Level 3: Analog comparator hysteresis 30 mV."]
195    #[inline(always)]
196    pub fn level_3(self) -> &'a mut crate::W<REG> {
197        self.variant(Hystctr::Level3)
198    }
199}
200#[doc = "Plus Input MUX Select\n\nValue on reset: 0"]
201#[cfg_attr(feature = "defmt", derive(defmt::Format))]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203#[repr(u8)]
204pub enum Psel {
205    #[doc = "0: Input 0p"]
206    Input0 = 0,
207    #[doc = "1: Input 1p"]
208    Input1 = 1,
209    #[doc = "2: Input 2p"]
210    Input2 = 2,
211    #[doc = "3: Input 3p"]
212    Input3 = 3,
213    #[doc = "4: Input 4p"]
214    Input4 = 4,
215    #[doc = "5: Input 5p"]
216    Input5 = 5,
217    #[doc = "7: Internal DAC output"]
218    Input7 = 7,
219}
220impl From<Psel> for u8 {
221    #[inline(always)]
222    fn from(variant: Psel) -> Self {
223        variant as _
224    }
225}
226impl crate::FieldSpec for Psel {
227    type Ux = u8;
228}
229impl crate::IsEnum for Psel {}
230#[doc = "Field `PSEL` reader - Plus Input MUX Select"]
231pub type PselR = crate::FieldReader<Psel>;
232impl PselR {
233    #[doc = "Get enumerated values variant"]
234    #[inline(always)]
235    pub const fn variant(&self) -> Option<Psel> {
236        match self.bits {
237            0 => Some(Psel::Input0),
238            1 => Some(Psel::Input1),
239            2 => Some(Psel::Input2),
240            3 => Some(Psel::Input3),
241            4 => Some(Psel::Input4),
242            5 => Some(Psel::Input5),
243            7 => Some(Psel::Input7),
244            _ => None,
245        }
246    }
247    #[doc = "Input 0p"]
248    #[inline(always)]
249    pub fn is_input_0(&self) -> bool {
250        *self == Psel::Input0
251    }
252    #[doc = "Input 1p"]
253    #[inline(always)]
254    pub fn is_input_1(&self) -> bool {
255        *self == Psel::Input1
256    }
257    #[doc = "Input 2p"]
258    #[inline(always)]
259    pub fn is_input_2(&self) -> bool {
260        *self == Psel::Input2
261    }
262    #[doc = "Input 3p"]
263    #[inline(always)]
264    pub fn is_input_3(&self) -> bool {
265        *self == Psel::Input3
266    }
267    #[doc = "Input 4p"]
268    #[inline(always)]
269    pub fn is_input_4(&self) -> bool {
270        *self == Psel::Input4
271    }
272    #[doc = "Input 5p"]
273    #[inline(always)]
274    pub fn is_input_5(&self) -> bool {
275        *self == Psel::Input5
276    }
277    #[doc = "Internal DAC output"]
278    #[inline(always)]
279    pub fn is_input_7(&self) -> bool {
280        *self == Psel::Input7
281    }
282}
283#[doc = "Field `PSEL` writer - Plus Input MUX Select"]
284pub type PselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Psel>;
285impl<'a, REG> PselW<'a, REG>
286where
287    REG: crate::Writable + crate::RegisterSpec,
288    REG::Ux: From<u8>,
289{
290    #[doc = "Input 0p"]
291    #[inline(always)]
292    pub fn input_0(self) -> &'a mut crate::W<REG> {
293        self.variant(Psel::Input0)
294    }
295    #[doc = "Input 1p"]
296    #[inline(always)]
297    pub fn input_1(self) -> &'a mut crate::W<REG> {
298        self.variant(Psel::Input1)
299    }
300    #[doc = "Input 2p"]
301    #[inline(always)]
302    pub fn input_2(self) -> &'a mut crate::W<REG> {
303        self.variant(Psel::Input2)
304    }
305    #[doc = "Input 3p"]
306    #[inline(always)]
307    pub fn input_3(self) -> &'a mut crate::W<REG> {
308        self.variant(Psel::Input3)
309    }
310    #[doc = "Input 4p"]
311    #[inline(always)]
312    pub fn input_4(self) -> &'a mut crate::W<REG> {
313        self.variant(Psel::Input4)
314    }
315    #[doc = "Input 5p"]
316    #[inline(always)]
317    pub fn input_5(self) -> &'a mut crate::W<REG> {
318        self.variant(Psel::Input5)
319    }
320    #[doc = "Internal DAC output"]
321    #[inline(always)]
322    pub fn input_7(self) -> &'a mut crate::W<REG> {
323        self.variant(Psel::Input7)
324    }
325}
326#[doc = "Minus Input MUX Select\n\nValue on reset: 0"]
327#[cfg_attr(feature = "defmt", derive(defmt::Format))]
328#[derive(Clone, Copy, Debug, PartialEq, Eq)]
329#[repr(u8)]
330pub enum Msel {
331    #[doc = "0: Input 0m"]
332    Input0 = 0,
333    #[doc = "1: Input 1m"]
334    Input1 = 1,
335    #[doc = "2: Input 2m"]
336    Input2 = 2,
337    #[doc = "3: Input 3m"]
338    Input3 = 3,
339    #[doc = "4: Input 4m"]
340    Input4 = 4,
341    #[doc = "5: Input 5m"]
342    Input5 = 5,
343    #[doc = "7: Internal DAC output"]
344    Input7 = 7,
345}
346impl From<Msel> for u8 {
347    #[inline(always)]
348    fn from(variant: Msel) -> Self {
349        variant as _
350    }
351}
352impl crate::FieldSpec for Msel {
353    type Ux = u8;
354}
355impl crate::IsEnum for Msel {}
356#[doc = "Field `MSEL` reader - Minus Input MUX Select"]
357pub type MselR = crate::FieldReader<Msel>;
358impl MselR {
359    #[doc = "Get enumerated values variant"]
360    #[inline(always)]
361    pub const fn variant(&self) -> Option<Msel> {
362        match self.bits {
363            0 => Some(Msel::Input0),
364            1 => Some(Msel::Input1),
365            2 => Some(Msel::Input2),
366            3 => Some(Msel::Input3),
367            4 => Some(Msel::Input4),
368            5 => Some(Msel::Input5),
369            7 => Some(Msel::Input7),
370            _ => None,
371        }
372    }
373    #[doc = "Input 0m"]
374    #[inline(always)]
375    pub fn is_input_0(&self) -> bool {
376        *self == Msel::Input0
377    }
378    #[doc = "Input 1m"]
379    #[inline(always)]
380    pub fn is_input_1(&self) -> bool {
381        *self == Msel::Input1
382    }
383    #[doc = "Input 2m"]
384    #[inline(always)]
385    pub fn is_input_2(&self) -> bool {
386        *self == Msel::Input2
387    }
388    #[doc = "Input 3m"]
389    #[inline(always)]
390    pub fn is_input_3(&self) -> bool {
391        *self == Msel::Input3
392    }
393    #[doc = "Input 4m"]
394    #[inline(always)]
395    pub fn is_input_4(&self) -> bool {
396        *self == Msel::Input4
397    }
398    #[doc = "Input 5m"]
399    #[inline(always)]
400    pub fn is_input_5(&self) -> bool {
401        *self == Msel::Input5
402    }
403    #[doc = "Internal DAC output"]
404    #[inline(always)]
405    pub fn is_input_7(&self) -> bool {
406        *self == Msel::Input7
407    }
408}
409#[doc = "Field `MSEL` writer - Minus Input MUX Select"]
410pub type MselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Msel>;
411impl<'a, REG> MselW<'a, REG>
412where
413    REG: crate::Writable + crate::RegisterSpec,
414    REG::Ux: From<u8>,
415{
416    #[doc = "Input 0m"]
417    #[inline(always)]
418    pub fn input_0(self) -> &'a mut crate::W<REG> {
419        self.variant(Msel::Input0)
420    }
421    #[doc = "Input 1m"]
422    #[inline(always)]
423    pub fn input_1(self) -> &'a mut crate::W<REG> {
424        self.variant(Msel::Input1)
425    }
426    #[doc = "Input 2m"]
427    #[inline(always)]
428    pub fn input_2(self) -> &'a mut crate::W<REG> {
429        self.variant(Msel::Input2)
430    }
431    #[doc = "Input 3m"]
432    #[inline(always)]
433    pub fn input_3(self) -> &'a mut crate::W<REG> {
434        self.variant(Msel::Input3)
435    }
436    #[doc = "Input 4m"]
437    #[inline(always)]
438    pub fn input_4(self) -> &'a mut crate::W<REG> {
439        self.variant(Msel::Input4)
440    }
441    #[doc = "Input 5m"]
442    #[inline(always)]
443    pub fn input_5(self) -> &'a mut crate::W<REG> {
444        self.variant(Msel::Input5)
445    }
446    #[doc = "Internal DAC output"]
447    #[inline(always)]
448    pub fn input_7(self) -> &'a mut crate::W<REG> {
449        self.variant(Msel::Input7)
450    }
451}
452impl R {
453    #[doc = "Bit 0 - CMP High Power Mode Select"]
454    #[inline(always)]
455    pub fn cmp_hpmd(&self) -> CmpHpmdR {
456        CmpHpmdR::new((self.bits & 1) != 0)
457    }
458    #[doc = "Bit 1 - CMP Nano Power Mode Select"]
459    #[inline(always)]
460    pub fn cmp_npmd(&self) -> CmpNpmdR {
461        CmpNpmdR::new(((self.bits >> 1) & 1) != 0)
462    }
463    #[doc = "Bits 4:5 - Comparator Hysteresis Control"]
464    #[inline(always)]
465    pub fn hystctr(&self) -> HystctrR {
466        HystctrR::new(((self.bits >> 4) & 3) as u8)
467    }
468    #[doc = "Bits 16:18 - Plus Input MUX Select"]
469    #[inline(always)]
470    pub fn psel(&self) -> PselR {
471        PselR::new(((self.bits >> 16) & 7) as u8)
472    }
473    #[doc = "Bits 20:22 - Minus Input MUX Select"]
474    #[inline(always)]
475    pub fn msel(&self) -> MselR {
476        MselR::new(((self.bits >> 20) & 7) as u8)
477    }
478}
479#[cfg(feature = "debug")]
480impl core::fmt::Debug for R {
481    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
482        f.debug_struct("CCR2")
483            .field("cmp_hpmd", &self.cmp_hpmd())
484            .field("cmp_npmd", &self.cmp_npmd())
485            .field("hystctr", &self.hystctr())
486            .field("psel", &self.psel())
487            .field("msel", &self.msel())
488            .finish()
489    }
490}
491impl W {
492    #[doc = "Bit 0 - CMP High Power Mode Select"]
493    #[inline(always)]
494    pub fn cmp_hpmd(&mut self) -> CmpHpmdW<'_, Ccr2Spec> {
495        CmpHpmdW::new(self, 0)
496    }
497    #[doc = "Bit 1 - CMP Nano Power Mode Select"]
498    #[inline(always)]
499    pub fn cmp_npmd(&mut self) -> CmpNpmdW<'_, Ccr2Spec> {
500        CmpNpmdW::new(self, 1)
501    }
502    #[doc = "Bits 4:5 - Comparator Hysteresis Control"]
503    #[inline(always)]
504    pub fn hystctr(&mut self) -> HystctrW<'_, Ccr2Spec> {
505        HystctrW::new(self, 4)
506    }
507    #[doc = "Bits 16:18 - Plus Input MUX Select"]
508    #[inline(always)]
509    pub fn psel(&mut self) -> PselW<'_, Ccr2Spec> {
510        PselW::new(self, 16)
511    }
512    #[doc = "Bits 20:22 - Minus Input MUX Select"]
513    #[inline(always)]
514    pub fn msel(&mut self) -> MselW<'_, Ccr2Spec> {
515        MselW::new(self, 20)
516    }
517}
518#[doc = "Comparator Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
519pub struct Ccr2Spec;
520impl crate::RegisterSpec for Ccr2Spec {
521    type Ux = u32;
522}
523#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
524impl crate::Readable for Ccr2Spec {}
525#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
526impl crate::Writable for Ccr2Spec {
527    type Safety = crate::Unsafe;
528}
529#[doc = "`reset()` method sets CCR2 to value 0"]
530impl crate::Resettable for Ccr2Spec {}
mcxa_pac/cmp0/ccr2.rs

mcxa_pac/cmp0/
ccr2.rs
