mcxa_pac/can0/
edcbt.rs

1#[doc = "Register `EDCBT` reader"]
2pub type R = crate::R<EdcbtSpec>;
3#[doc = "Register `EDCBT` writer"]
4pub type W = crate::W<EdcbtSpec>;
5#[doc = "Field `DTSEG1` reader - Data Phase Segment 1"]
6pub type Dtseg1R = crate::FieldReader;
7#[doc = "Field `DTSEG1` writer - Data Phase Segment 1"]
8pub type Dtseg1W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `DTSEG2` reader - Data Phase Time Segment 2"]
10pub type Dtseg2R = crate::FieldReader;
11#[doc = "Field `DTSEG2` writer - Data Phase Time Segment 2"]
12pub type Dtseg2W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `DRJW` reader - Data Phase Resynchronization Jump Width"]
14pub type DrjwR = crate::FieldReader;
15#[doc = "Field `DRJW` writer - Data Phase Resynchronization Jump Width"]
16pub type DrjwW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17impl R {
18    #[doc = "Bits 0:4 - Data Phase Segment 1"]
19    #[inline(always)]
20    pub fn dtseg1(&self) -> Dtseg1R {
21        Dtseg1R::new((self.bits & 0x1f) as u8)
22    }
23    #[doc = "Bits 12:15 - Data Phase Time Segment 2"]
24    #[inline(always)]
25    pub fn dtseg2(&self) -> Dtseg2R {
26        Dtseg2R::new(((self.bits >> 12) & 0x0f) as u8)
27    }
28    #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"]
29    #[inline(always)]
30    pub fn drjw(&self) -> DrjwR {
31        DrjwR::new(((self.bits >> 22) & 0x0f) as u8)
32    }
33}
34#[cfg(feature = "debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("EDCBT")
38            .field("dtseg1", &self.dtseg1())
39            .field("dtseg2", &self.dtseg2())
40            .field("drjw", &self.drjw())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:4 - Data Phase Segment 1"]
46    #[inline(always)]
47    pub fn dtseg1(&mut self) -> Dtseg1W<'_, EdcbtSpec> {
48        Dtseg1W::new(self, 0)
49    }
50    #[doc = "Bits 12:15 - Data Phase Time Segment 2"]
51    #[inline(always)]
52    pub fn dtseg2(&mut self) -> Dtseg2W<'_, EdcbtSpec> {
53        Dtseg2W::new(self, 12)
54    }
55    #[doc = "Bits 22:25 - Data Phase Resynchronization Jump Width"]
56    #[inline(always)]
57    pub fn drjw(&mut self) -> DrjwW<'_, EdcbtSpec> {
58        DrjwW::new(self, 22)
59    }
60}
61#[doc = "Enhanced Data Phase CAN Bit Timing\n\nYou can [`read`](crate::Reg::read) this register and get [`edcbt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edcbt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct EdcbtSpec;
63impl crate::RegisterSpec for EdcbtSpec {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`edcbt::R`](R) reader structure"]
67impl crate::Readable for EdcbtSpec {}
68#[doc = "`write(|w| ..)` method takes [`edcbt::W`](W) writer structure"]
69impl crate::Writable for EdcbtSpec {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets EDCBT to value 0"]
73impl crate::Resettable for EdcbtSpec {}
mcxa_pac/can0/edcbt.rs

mcxa_pac/can0/
edcbt.rs
