mcxa_pac/usb0/
otgctl.rs

1#[doc = "Register `OTGCTL` reader"]
2pub type R = crate::R<OtgctlSpec>;
3#[doc = "Register `OTGCTL` writer"]
4pub type W = crate::W<OtgctlSpec>;
5#[doc = "On-The-Go Pullup and Pulldown Resistor Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Otgen {
9    #[doc = "0: If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."]
10    ConfigResistorsCtl = 0,
11    #[doc = "1: Uses the pullup and pulldown controls in this register."]
12    ConfigResistorsHere = 1,
13}
14impl From<Otgen> for bool {
15    #[inline(always)]
16    fn from(variant: Otgen) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `OTGEN` reader - On-The-Go Pullup and Pulldown Resistor Enable"]
21pub type OtgenR = crate::BitReader<Otgen>;
22impl OtgenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Otgen {
26        match self.bits {
27            false => Otgen::ConfigResistorsCtl,
28            true => Otgen::ConfigResistorsHere,
29        }
30    }
31    #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."]
32    #[inline(always)]
33    pub fn is_config_resistors_ctl(&self) -> bool {
34        *self == Otgen::ConfigResistorsCtl
35    }
36    #[doc = "Uses the pullup and pulldown controls in this register."]
37    #[inline(always)]
38    pub fn is_config_resistors_here(&self) -> bool {
39        *self == Otgen::ConfigResistorsHere
40    }
41}
42#[doc = "Field `OTGEN` writer - On-The-Go Pullup and Pulldown Resistor Enable"]
43pub type OtgenW<'a, REG> = crate::BitWriter<'a, REG, Otgen>;
44impl<'a, REG> OtgenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "If USBENSOFEN is 1 and HOSTMODEEN is 0 in the Control Register (CTL), then the D+ Data line pullup resistors are enabled. If HOSTMODEEN is 1, then the D+ and D- Data line pulldown resistors are engaged."]
49    #[inline(always)]
50    pub fn config_resistors_ctl(self) -> &'a mut crate::W<REG> {
51        self.variant(Otgen::ConfigResistorsCtl)
52    }
53    #[doc = "Uses the pullup and pulldown controls in this register."]
54    #[inline(always)]
55    pub fn config_resistors_here(self) -> &'a mut crate::W<REG> {
56        self.variant(Otgen::ConfigResistorsHere)
57    }
58}
59#[doc = "D- Data Line Pulldown Resistor Enable\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Dmlow {
63    #[doc = "0: Disable"]
64    DisDmPulldown = 0,
65    #[doc = "1: Enable"]
66    EnDmPulldown = 1,
67}
68impl From<Dmlow> for bool {
69    #[inline(always)]
70    fn from(variant: Dmlow) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `DMLOW` reader - D- Data Line Pulldown Resistor Enable"]
75pub type DmlowR = crate::BitReader<Dmlow>;
76impl DmlowR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Dmlow {
80        match self.bits {
81            false => Dmlow::DisDmPulldown,
82            true => Dmlow::EnDmPulldown,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_dis_dm_pulldown(&self) -> bool {
88        *self == Dmlow::DisDmPulldown
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_en_dm_pulldown(&self) -> bool {
93        *self == Dmlow::EnDmPulldown
94    }
95}
96#[doc = "Field `DMLOW` writer - D- Data Line Pulldown Resistor Enable"]
97pub type DmlowW<'a, REG> = crate::BitWriter<'a, REG, Dmlow>;
98impl<'a, REG> DmlowW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn dis_dm_pulldown(self) -> &'a mut crate::W<REG> {
105        self.variant(Dmlow::DisDmPulldown)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn en_dm_pulldown(self) -> &'a mut crate::W<REG> {
110        self.variant(Dmlow::EnDmPulldown)
111    }
112}
113#[doc = "D+ Data Line pulldown Resistor Enable\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Dplow {
117    #[doc = "0: Disable"]
118    DisDpPulldown = 0,
119    #[doc = "1: Enable"]
120    EnDpPulldown = 1,
121}
122impl From<Dplow> for bool {
123    #[inline(always)]
124    fn from(variant: Dplow) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `DPLOW` reader - D+ Data Line pulldown Resistor Enable"]
129pub type DplowR = crate::BitReader<Dplow>;
130impl DplowR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Dplow {
134        match self.bits {
135            false => Dplow::DisDpPulldown,
136            true => Dplow::EnDpPulldown,
137        }
138    }
139    #[doc = "Disable"]
140    #[inline(always)]
141    pub fn is_dis_dp_pulldown(&self) -> bool {
142        *self == Dplow::DisDpPulldown
143    }
144    #[doc = "Enable"]
145    #[inline(always)]
146    pub fn is_en_dp_pulldown(&self) -> bool {
147        *self == Dplow::EnDpPulldown
148    }
149}
150#[doc = "Field `DPLOW` writer - D+ Data Line pulldown Resistor Enable"]
151pub type DplowW<'a, REG> = crate::BitWriter<'a, REG, Dplow>;
152impl<'a, REG> DplowW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disable"]
157    #[inline(always)]
158    pub fn dis_dp_pulldown(self) -> &'a mut crate::W<REG> {
159        self.variant(Dplow::DisDpPulldown)
160    }
161    #[doc = "Enable"]
162    #[inline(always)]
163    pub fn en_dp_pulldown(self) -> &'a mut crate::W<REG> {
164        self.variant(Dplow::EnDpPulldown)
165    }
166}
167#[doc = "D+ Data Line Pullup Resistor Enable\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Dphigh {
171    #[doc = "0: Disable"]
172    DisDpPullup = 0,
173    #[doc = "1: Enable"]
174    EnDpPullup = 1,
175}
176impl From<Dphigh> for bool {
177    #[inline(always)]
178    fn from(variant: Dphigh) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `DPHIGH` reader - D+ Data Line Pullup Resistor Enable"]
183pub type DphighR = crate::BitReader<Dphigh>;
184impl DphighR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Dphigh {
188        match self.bits {
189            false => Dphigh::DisDpPullup,
190            true => Dphigh::EnDpPullup,
191        }
192    }
193    #[doc = "Disable"]
194    #[inline(always)]
195    pub fn is_dis_dp_pullup(&self) -> bool {
196        *self == Dphigh::DisDpPullup
197    }
198    #[doc = "Enable"]
199    #[inline(always)]
200    pub fn is_en_dp_pullup(&self) -> bool {
201        *self == Dphigh::EnDpPullup
202    }
203}
204#[doc = "Field `DPHIGH` writer - D+ Data Line Pullup Resistor Enable"]
205pub type DphighW<'a, REG> = crate::BitWriter<'a, REG, Dphigh>;
206impl<'a, REG> DphighW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disable"]
211    #[inline(always)]
212    pub fn dis_dp_pullup(self) -> &'a mut crate::W<REG> {
213        self.variant(Dphigh::DisDpPullup)
214    }
215    #[doc = "Enable"]
216    #[inline(always)]
217    pub fn en_dp_pullup(self) -> &'a mut crate::W<REG> {
218        self.variant(Dphigh::EnDpPullup)
219    }
220}
221impl R {
222    #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"]
223    #[inline(always)]
224    pub fn otgen(&self) -> OtgenR {
225        OtgenR::new(((self.bits >> 2) & 1) != 0)
226    }
227    #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"]
228    #[inline(always)]
229    pub fn dmlow(&self) -> DmlowR {
230        DmlowR::new(((self.bits >> 4) & 1) != 0)
231    }
232    #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"]
233    #[inline(always)]
234    pub fn dplow(&self) -> DplowR {
235        DplowR::new(((self.bits >> 5) & 1) != 0)
236    }
237    #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"]
238    #[inline(always)]
239    pub fn dphigh(&self) -> DphighR {
240        DphighR::new(((self.bits >> 7) & 1) != 0)
241    }
242}
243#[cfg(feature = "debug")]
244impl core::fmt::Debug for R {
245    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
246        f.debug_struct("OTGCTL")
247            .field("otgen", &self.otgen())
248            .field("dmlow", &self.dmlow())
249            .field("dplow", &self.dplow())
250            .field("dphigh", &self.dphigh())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bit 2 - On-The-Go Pullup and Pulldown Resistor Enable"]
256    #[inline(always)]
257    pub fn otgen(&mut self) -> OtgenW<'_, OtgctlSpec> {
258        OtgenW::new(self, 2)
259    }
260    #[doc = "Bit 4 - D- Data Line Pulldown Resistor Enable"]
261    #[inline(always)]
262    pub fn dmlow(&mut self) -> DmlowW<'_, OtgctlSpec> {
263        DmlowW::new(self, 4)
264    }
265    #[doc = "Bit 5 - D+ Data Line pulldown Resistor Enable"]
266    #[inline(always)]
267    pub fn dplow(&mut self) -> DplowW<'_, OtgctlSpec> {
268        DplowW::new(self, 5)
269    }
270    #[doc = "Bit 7 - D+ Data Line Pullup Resistor Enable"]
271    #[inline(always)]
272    pub fn dphigh(&mut self) -> DphighW<'_, OtgctlSpec> {
273        DphighW::new(self, 7)
274    }
275}
276#[doc = "OTG Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct OtgctlSpec;
278impl crate::RegisterSpec for OtgctlSpec {
279    type Ux = u8;
280}
281#[doc = "`read()` method returns [`otgctl::R`](R) reader structure"]
282impl crate::Readable for OtgctlSpec {}
283#[doc = "`write(|w| ..)` method takes [`otgctl::W`](W) writer structure"]
284impl crate::Writable for OtgctlSpec {
285    type Safety = crate::Unsafe;
286}
287#[doc = "`reset()` method sets OTGCTL to value 0"]
288impl crate::Resettable for OtgctlSpec {}
mcxa_pac/usb0/otgctl.rs

mcxa_pac/usb0/
otgctl.rs
