mcxa_pac/syscon/
ram_ctrl.rs

1#[doc = "Register `RAM_CTRL` reader"]
2pub type R = crate::R<RamCtrlSpec>;
3#[doc = "Register `RAM_CTRL` writer"]
4pub type W = crate::W<RamCtrlSpec>;
5#[doc = "RAMA ECC enable\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum RamaEccEnable {
9    #[doc = "0: ECC is disabled"]
10    Disable = 0,
11    #[doc = "1: ECC is enabled"]
12    Enable = 1,
13}
14impl From<RamaEccEnable> for bool {
15    #[inline(always)]
16    fn from(variant: RamaEccEnable) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `RAMA_ECC_ENABLE` reader - RAMA ECC enable"]
21pub type RamaEccEnableR = crate::BitReader<RamaEccEnable>;
22impl RamaEccEnableR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> RamaEccEnable {
26        match self.bits {
27            false => RamaEccEnable::Disable,
28            true => RamaEccEnable::Enable,
29        }
30    }
31    #[doc = "ECC is disabled"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == RamaEccEnable::Disable
35    }
36    #[doc = "ECC is enabled"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == RamaEccEnable::Enable
40    }
41}
42#[doc = "Field `RAMA_ECC_ENABLE` writer - RAMA ECC enable"]
43pub type RamaEccEnableW<'a, REG> = crate::BitWriter<'a, REG, RamaEccEnable>;
44impl<'a, REG> RamaEccEnableW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "ECC is disabled"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(RamaEccEnable::Disable)
52    }
53    #[doc = "ECC is enabled"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(RamaEccEnable::Enable)
57    }
58}
59#[doc = "RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum RamaCgOverride {
63    #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"]
64    Disable = 0,
65    #[doc = "1: Auto clock gating feature is disabled"]
66    Enable = 1,
67}
68impl From<RamaCgOverride> for bool {
69    #[inline(always)]
70    fn from(variant: RamaCgOverride) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `RAMA_CG_OVERRIDE` reader - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."]
75pub type RamaCgOverrideR = crate::BitReader<RamaCgOverride>;
76impl RamaCgOverrideR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> RamaCgOverride {
80        match self.bits {
81            false => RamaCgOverride::Disable,
82            true => RamaCgOverride::Enable,
83        }
84    }
85    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == RamaCgOverride::Disable
89    }
90    #[doc = "Auto clock gating feature is disabled"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == RamaCgOverride::Enable
94    }
95}
96#[doc = "Field `RAMA_CG_OVERRIDE` writer - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."]
97pub type RamaCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamaCgOverride>;
98impl<'a, REG> RamaCgOverrideW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(RamaCgOverride::Disable)
106    }
107    #[doc = "Auto clock gating feature is disabled"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(RamaCgOverride::Enable)
111    }
112}
113#[doc = "RAMX bank clock gating control\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum RamxCgOverride {
117    #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"]
118    Disable = 0,
119    #[doc = "1: Auto clock gating feature is disabled"]
120    Enable = 1,
121}
122impl From<RamxCgOverride> for bool {
123    #[inline(always)]
124    fn from(variant: RamxCgOverride) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `RAMX_CG_OVERRIDE` reader - RAMX bank clock gating control"]
129pub type RamxCgOverrideR = crate::BitReader<RamxCgOverride>;
130impl RamxCgOverrideR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> RamxCgOverride {
134        match self.bits {
135            false => RamxCgOverride::Disable,
136            true => RamxCgOverride::Enable,
137        }
138    }
139    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == RamxCgOverride::Disable
143    }
144    #[doc = "Auto clock gating feature is disabled"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == RamxCgOverride::Enable
148    }
149}
150#[doc = "Field `RAMX_CG_OVERRIDE` writer - RAMX bank clock gating control"]
151pub type RamxCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamxCgOverride>;
152impl<'a, REG> RamxCgOverrideW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(RamxCgOverride::Disable)
160    }
161    #[doc = "Auto clock gating feature is disabled"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(RamxCgOverride::Enable)
165    }
166}
167#[doc = "RAMB bank clock gating control\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum RambCgOverride {
171    #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"]
172    Disable = 0,
173    #[doc = "1: Auto clock gating feature is disabled"]
174    Enable = 1,
175}
176impl From<RambCgOverride> for bool {
177    #[inline(always)]
178    fn from(variant: RambCgOverride) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `RAMB_CG_OVERRIDE` reader - RAMB bank clock gating control"]
183pub type RambCgOverrideR = crate::BitReader<RambCgOverride>;
184impl RambCgOverrideR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> RambCgOverride {
188        match self.bits {
189            false => RambCgOverride::Disable,
190            true => RambCgOverride::Enable,
191        }
192    }
193    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == RambCgOverride::Disable
197    }
198    #[doc = "Auto clock gating feature is disabled"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == RambCgOverride::Enable
202    }
203}
204#[doc = "Field `RAMB_CG_OVERRIDE` writer - RAMB bank clock gating control"]
205pub type RambCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RambCgOverride>;
206impl<'a, REG> RambCgOverrideW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(RambCgOverride::Disable)
214    }
215    #[doc = "Auto clock gating feature is disabled"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(RambCgOverride::Enable)
219    }
220}
221#[doc = "RAMC bank clock gating control\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum RamcCgOverride {
225    #[doc = "0: Memory bank clock is gated automatically if no access more than 16 clock cycles"]
226    Disable = 0,
227    #[doc = "1: Auto clock gating feature is disabled"]
228    Enable = 1,
229}
230impl From<RamcCgOverride> for bool {
231    #[inline(always)]
232    fn from(variant: RamcCgOverride) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `RAMC_CG_OVERRIDE` reader - RAMC bank clock gating control"]
237pub type RamcCgOverrideR = crate::BitReader<RamcCgOverride>;
238impl RamcCgOverrideR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> RamcCgOverride {
242        match self.bits {
243            false => RamcCgOverride::Disable,
244            true => RamcCgOverride::Enable,
245        }
246    }
247    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
248    #[inline(always)]
249    pub fn is_disable(&self) -> bool {
250        *self == RamcCgOverride::Disable
251    }
252    #[doc = "Auto clock gating feature is disabled"]
253    #[inline(always)]
254    pub fn is_enable(&self) -> bool {
255        *self == RamcCgOverride::Enable
256    }
257}
258#[doc = "Field `RAMC_CG_OVERRIDE` writer - RAMC bank clock gating control"]
259pub type RamcCgOverrideW<'a, REG> = crate::BitWriter<'a, REG, RamcCgOverride>;
260impl<'a, REG> RamcCgOverrideW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Memory bank clock is gated automatically if no access more than 16 clock cycles"]
265    #[inline(always)]
266    pub fn disable(self) -> &'a mut crate::W<REG> {
267        self.variant(RamcCgOverride::Disable)
268    }
269    #[doc = "Auto clock gating feature is disabled"]
270    #[inline(always)]
271    pub fn enable(self) -> &'a mut crate::W<REG> {
272        self.variant(RamcCgOverride::Enable)
273    }
274}
275impl R {
276    #[doc = "Bit 0 - RAMA ECC enable"]
277    #[inline(always)]
278    pub fn rama_ecc_enable(&self) -> RamaEccEnableR {
279        RamaEccEnableR::new((self.bits & 1) != 0)
280    }
281    #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."]
282    #[inline(always)]
283    pub fn rama_cg_override(&self) -> RamaCgOverrideR {
284        RamaCgOverrideR::new(((self.bits >> 16) & 1) != 0)
285    }
286    #[doc = "Bit 17 - RAMX bank clock gating control"]
287    #[inline(always)]
288    pub fn ramx_cg_override(&self) -> RamxCgOverrideR {
289        RamxCgOverrideR::new(((self.bits >> 17) & 1) != 0)
290    }
291    #[doc = "Bit 18 - RAMB bank clock gating control"]
292    #[inline(always)]
293    pub fn ramb_cg_override(&self) -> RambCgOverrideR {
294        RambCgOverrideR::new(((self.bits >> 18) & 1) != 0)
295    }
296    #[doc = "Bit 19 - RAMC bank clock gating control"]
297    #[inline(always)]
298    pub fn ramc_cg_override(&self) -> RamcCgOverrideR {
299        RamcCgOverrideR::new(((self.bits >> 19) & 1) != 0)
300    }
301}
302#[cfg(feature = "debug")]
303impl core::fmt::Debug for R {
304    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
305        f.debug_struct("RAM_CTRL")
306            .field("rama_ecc_enable", &self.rama_ecc_enable())
307            .field("rama_cg_override", &self.rama_cg_override())
308            .field("ramx_cg_override", &self.ramx_cg_override())
309            .field("ramb_cg_override", &self.ramb_cg_override())
310            .field("ramc_cg_override", &self.ramc_cg_override())
311            .finish()
312    }
313}
314impl W {
315    #[doc = "Bit 0 - RAMA ECC enable"]
316    #[inline(always)]
317    pub fn rama_ecc_enable(&mut self) -> RamaEccEnableW<'_, RamCtrlSpec> {
318        RamaEccEnableW::new(self, 0)
319    }
320    #[doc = "Bit 16 - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0."]
321    #[inline(always)]
322    pub fn rama_cg_override(&mut self) -> RamaCgOverrideW<'_, RamCtrlSpec> {
323        RamaCgOverrideW::new(self, 16)
324    }
325    #[doc = "Bit 17 - RAMX bank clock gating control"]
326    #[inline(always)]
327    pub fn ramx_cg_override(&mut self) -> RamxCgOverrideW<'_, RamCtrlSpec> {
328        RamxCgOverrideW::new(self, 17)
329    }
330    #[doc = "Bit 18 - RAMB bank clock gating control"]
331    #[inline(always)]
332    pub fn ramb_cg_override(&mut self) -> RambCgOverrideW<'_, RamCtrlSpec> {
333        RambCgOverrideW::new(self, 18)
334    }
335    #[doc = "Bit 19 - RAMC bank clock gating control"]
336    #[inline(always)]
337    pub fn ramc_cg_override(&mut self) -> RamcCgOverrideW<'_, RamCtrlSpec> {
338        RamcCgOverrideW::new(self, 19)
339    }
340}
341#[doc = "RAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
342pub struct RamCtrlSpec;
343impl crate::RegisterSpec for RamCtrlSpec {
344    type Ux = u32;
345}
346#[doc = "`read()` method returns [`ram_ctrl::R`](R) reader structure"]
347impl crate::Readable for RamCtrlSpec {}
348#[doc = "`write(|w| ..)` method takes [`ram_ctrl::W`](W) writer structure"]
349impl crate::Writable for RamCtrlSpec {
350    type Safety = crate::Unsafe;
351}
352#[doc = "`reset()` method sets RAM_CTRL to value 0x01"]
353impl crate::Resettable for RamCtrlSpec {
354    const RESET_VALUE: u32 = 0x01;
355}
mcxa_pac/syscon/ram_ctrl.rs

mcxa_pac/syscon/
ram_ctrl.rs
