mcxa_pac/syscon/
pwm1subctl.rs

1#[doc = "Register `PWM1SUBCTL` reader"]
2pub type R = crate::R<Pwm1subctlSpec>;
3#[doc = "Register `PWM1SUBCTL` writer"]
4pub type W = crate::W<Pwm1subctlSpec>;
5#[doc = "Enables PWM1 SUB Clock0\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Clk0En {
9    #[doc = "0: Disable"]
10    Disable = 0,
11    #[doc = "1: Enable"]
12    Enable = 1,
13}
14impl From<Clk0En> for bool {
15    #[inline(always)]
16    fn from(variant: Clk0En) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `CLK0_EN` reader - Enables PWM1 SUB Clock0"]
21pub type Clk0EnR = crate::BitReader<Clk0En>;
22impl Clk0EnR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Clk0En {
26        match self.bits {
27            false => Clk0En::Disable,
28            true => Clk0En::Enable,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Clk0En::Disable
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Clk0En::Enable
40    }
41}
42#[doc = "Field `CLK0_EN` writer - Enables PWM1 SUB Clock0"]
43pub type Clk0EnW<'a, REG> = crate::BitWriter<'a, REG, Clk0En>;
44impl<'a, REG> Clk0EnW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Clk0En::Disable)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Clk0En::Enable)
57    }
58}
59#[doc = "Enables PWM1 SUB Clock1\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Clk1En {
63    #[doc = "0: Disable"]
64    Disable = 0,
65    #[doc = "1: Enable"]
66    Enable = 1,
67}
68impl From<Clk1En> for bool {
69    #[inline(always)]
70    fn from(variant: Clk1En) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `CLK1_EN` reader - Enables PWM1 SUB Clock1"]
75pub type Clk1EnR = crate::BitReader<Clk1En>;
76impl Clk1EnR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Clk1En {
80        match self.bits {
81            false => Clk1En::Disable,
82            true => Clk1En::Enable,
83        }
84    }
85    #[doc = "Disable"]
86    #[inline(always)]
87    pub fn is_disable(&self) -> bool {
88        *self == Clk1En::Disable
89    }
90    #[doc = "Enable"]
91    #[inline(always)]
92    pub fn is_enable(&self) -> bool {
93        *self == Clk1En::Enable
94    }
95}
96#[doc = "Field `CLK1_EN` writer - Enables PWM1 SUB Clock1"]
97pub type Clk1EnW<'a, REG> = crate::BitWriter<'a, REG, Clk1En>;
98impl<'a, REG> Clk1EnW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Disable"]
103    #[inline(always)]
104    pub fn disable(self) -> &'a mut crate::W<REG> {
105        self.variant(Clk1En::Disable)
106    }
107    #[doc = "Enable"]
108    #[inline(always)]
109    pub fn enable(self) -> &'a mut crate::W<REG> {
110        self.variant(Clk1En::Enable)
111    }
112}
113#[doc = "Enables PWM1 SUB Clock2\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Clk2En {
117    #[doc = "0: Disable"]
118    Disable = 0,
119    #[doc = "1: Enable"]
120    Enable = 1,
121}
122impl From<Clk2En> for bool {
123    #[inline(always)]
124    fn from(variant: Clk2En) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `CLK2_EN` reader - Enables PWM1 SUB Clock2"]
129pub type Clk2EnR = crate::BitReader<Clk2En>;
130impl Clk2EnR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Clk2En {
134        match self.bits {
135            false => Clk2En::Disable,
136            true => Clk2En::Enable,
137        }
138    }
139    #[doc = "Disable"]
140    #[inline(always)]
141    pub fn is_disable(&self) -> bool {
142        *self == Clk2En::Disable
143    }
144    #[doc = "Enable"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == Clk2En::Enable
148    }
149}
150#[doc = "Field `CLK2_EN` writer - Enables PWM1 SUB Clock2"]
151pub type Clk2EnW<'a, REG> = crate::BitWriter<'a, REG, Clk2En>;
152impl<'a, REG> Clk2EnW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disable"]
157    #[inline(always)]
158    pub fn disable(self) -> &'a mut crate::W<REG> {
159        self.variant(Clk2En::Disable)
160    }
161    #[doc = "Enable"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(Clk2En::Enable)
165    }
166}
167#[doc = "Enables PWM1 SUB Clock3\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Clk3En {
171    #[doc = "0: Disable"]
172    Disable = 0,
173    #[doc = "1: Enable"]
174    Enable = 1,
175}
176impl From<Clk3En> for bool {
177    #[inline(always)]
178    fn from(variant: Clk3En) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `CLK3_EN` reader - Enables PWM1 SUB Clock3"]
183pub type Clk3EnR = crate::BitReader<Clk3En>;
184impl Clk3EnR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Clk3En {
188        match self.bits {
189            false => Clk3En::Disable,
190            true => Clk3En::Enable,
191        }
192    }
193    #[doc = "Disable"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Clk3En::Disable
197    }
198    #[doc = "Enable"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Clk3En::Enable
202    }
203}
204#[doc = "Field `CLK3_EN` writer - Enables PWM1 SUB Clock3"]
205pub type Clk3EnW<'a, REG> = crate::BitWriter<'a, REG, Clk3En>;
206impl<'a, REG> Clk3EnW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disable"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Clk3En::Disable)
214    }
215    #[doc = "Enable"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Clk3En::Enable)
219    }
220}
221impl R {
222    #[doc = "Bit 0 - Enables PWM1 SUB Clock0"]
223    #[inline(always)]
224    pub fn clk0_en(&self) -> Clk0EnR {
225        Clk0EnR::new((self.bits & 1) != 0)
226    }
227    #[doc = "Bit 1 - Enables PWM1 SUB Clock1"]
228    #[inline(always)]
229    pub fn clk1_en(&self) -> Clk1EnR {
230        Clk1EnR::new(((self.bits >> 1) & 1) != 0)
231    }
232    #[doc = "Bit 2 - Enables PWM1 SUB Clock2"]
233    #[inline(always)]
234    pub fn clk2_en(&self) -> Clk2EnR {
235        Clk2EnR::new(((self.bits >> 2) & 1) != 0)
236    }
237    #[doc = "Bit 3 - Enables PWM1 SUB Clock3"]
238    #[inline(always)]
239    pub fn clk3_en(&self) -> Clk3EnR {
240        Clk3EnR::new(((self.bits >> 3) & 1) != 0)
241    }
242}
243#[cfg(feature = "debug")]
244impl core::fmt::Debug for R {
245    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
246        f.debug_struct("PWM1SUBCTL")
247            .field("clk0_en", &self.clk0_en())
248            .field("clk1_en", &self.clk1_en())
249            .field("clk2_en", &self.clk2_en())
250            .field("clk3_en", &self.clk3_en())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bit 0 - Enables PWM1 SUB Clock0"]
256    #[inline(always)]
257    pub fn clk0_en(&mut self) -> Clk0EnW<'_, Pwm1subctlSpec> {
258        Clk0EnW::new(self, 0)
259    }
260    #[doc = "Bit 1 - Enables PWM1 SUB Clock1"]
261    #[inline(always)]
262    pub fn clk1_en(&mut self) -> Clk1EnW<'_, Pwm1subctlSpec> {
263        Clk1EnW::new(self, 1)
264    }
265    #[doc = "Bit 2 - Enables PWM1 SUB Clock2"]
266    #[inline(always)]
267    pub fn clk2_en(&mut self) -> Clk2EnW<'_, Pwm1subctlSpec> {
268        Clk2EnW::new(self, 2)
269    }
270    #[doc = "Bit 3 - Enables PWM1 SUB Clock3"]
271    #[inline(always)]
272    pub fn clk3_en(&mut self) -> Clk3EnW<'_, Pwm1subctlSpec> {
273        Clk3EnW::new(self, 3)
274    }
275}
276#[doc = "PWM1 Submodule Control\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1subctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1subctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct Pwm1subctlSpec;
278impl crate::RegisterSpec for Pwm1subctlSpec {
279    type Ux = u32;
280}
281#[doc = "`read()` method returns [`pwm1subctl::R`](R) reader structure"]
282impl crate::Readable for Pwm1subctlSpec {}
283#[doc = "`write(|w| ..)` method takes [`pwm1subctl::W`](W) writer structure"]
284impl crate::Writable for Pwm1subctlSpec {
285    type Safety = crate::Unsafe;
286}
287#[doc = "`reset()` method sets PWM1SUBCTL to value 0"]
288impl crate::Resettable for Pwm1subctlSpec {}
mcxa_pac/syscon/pwm1subctl.rs

mcxa_pac/syscon/
pwm1subctl.rs
