mcxa_pac/syscon/
nmisrc.rs

1#[doc = "Register `NMISRC` reader"]
2pub type R = crate::R<NmisrcSpec>;
3#[doc = "Register `NMISRC` writer"]
4pub type W = crate::W<NmisrcSpec>;
5#[doc = "Field `IRQCPU0` reader - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."]
6pub type Irqcpu0R = crate::FieldReader;
7#[doc = "Field `IRQCPU0` writer - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."]
8pub type Irqcpu0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Nmiencpu0 {
13    #[doc = "0: Disable."]
14    Disable = 0,
15    #[doc = "1: Enable."]
16    Enable = 1,
17}
18impl From<Nmiencpu0> for bool {
19    #[inline(always)]
20    fn from(variant: Nmiencpu0) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `NMIENCPU0` reader - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."]
25pub type Nmiencpu0R = crate::BitReader<Nmiencpu0>;
26impl Nmiencpu0R {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Nmiencpu0 {
30        match self.bits {
31            false => Nmiencpu0::Disable,
32            true => Nmiencpu0::Enable,
33        }
34    }
35    #[doc = "Disable."]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == Nmiencpu0::Disable
39    }
40    #[doc = "Enable."]
41    #[inline(always)]
42    pub fn is_enable(&self) -> bool {
43        *self == Nmiencpu0::Enable
44    }
45}
46#[doc = "Field `NMIENCPU0` writer - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."]
47pub type Nmiencpu0W<'a, REG> = crate::BitWriter<'a, REG, Nmiencpu0>;
48impl<'a, REG> Nmiencpu0W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Disable."]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(Nmiencpu0::Disable)
56    }
57    #[doc = "Enable."]
58    #[inline(always)]
59    pub fn enable(self) -> &'a mut crate::W<REG> {
60        self.variant(Nmiencpu0::Enable)
61    }
62}
63impl R {
64    #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."]
65    #[inline(always)]
66    pub fn irqcpu0(&self) -> Irqcpu0R {
67        Irqcpu0R::new((self.bits & 0xff) as u8)
68    }
69    #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."]
70    #[inline(always)]
71    pub fn nmiencpu0(&self) -> Nmiencpu0R {
72        Nmiencpu0R::new(((self.bits >> 31) & 1) != 0)
73    }
74}
75#[cfg(feature = "debug")]
76impl core::fmt::Debug for R {
77    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78        f.debug_struct("NMISRC")
79            .field("irqcpu0", &self.irqcpu0())
80            .field("nmiencpu0", &self.nmiencpu0())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:7 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0."]
86    #[inline(always)]
87    pub fn irqcpu0(&mut self) -> Irqcpu0W<'_, NmisrcSpec> {
88        Irqcpu0W::new(self, 0)
89    }
90    #[doc = "Bit 31 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0."]
91    #[inline(always)]
92    pub fn nmiencpu0(&mut self) -> Nmiencpu0W<'_, NmisrcSpec> {
93        Nmiencpu0W::new(self, 31)
94    }
95}
96#[doc = "NMI Source Select\n\nYou can [`read`](crate::Reg::read) this register and get [`nmisrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmisrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct NmisrcSpec;
98impl crate::RegisterSpec for NmisrcSpec {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`nmisrc::R`](R) reader structure"]
102impl crate::Readable for NmisrcSpec {}
103#[doc = "`write(|w| ..)` method takes [`nmisrc::W`](W) writer structure"]
104impl crate::Writable for NmisrcSpec {
105    type Safety = crate::Unsafe;
106}
107#[doc = "`reset()` method sets NMISRC to value 0"]
108impl crate::Resettable for NmisrcSpec {}
mcxa_pac/syscon/nmisrc.rs

mcxa_pac/syscon/
nmisrc.rs
