Skip to main content

mcxa_pac/spc0/
sramctl.rs

1#[doc = "Register `SRAMCTL` reader"]
2pub type R = crate::R<SramctlSpec>;
3#[doc = "Register `SRAMCTL` writer"]
4pub type W = crate::W<SramctlSpec>;
5#[doc = "Voltage Select Margin\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Vsm {
10    #[doc = "1: SRAM configured for 1.0v"]
11    Sram1v0 = 1,
12    #[doc = "3: SRAM configured for 1.2v"]
13    Sram1v2 = 3,
14}
15impl From<Vsm> for u8 {
16    #[inline(always)]
17    fn from(variant: Vsm) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Vsm {
22    type Ux = u8;
23}
24impl crate::IsEnum for Vsm {}
25#[doc = "Field `VSM` reader - Voltage Select Margin"]
26pub type VsmR = crate::FieldReader<Vsm>;
27impl VsmR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Vsm> {
31        match self.bits {
32            1 => Some(Vsm::Sram1v0),
33            3 => Some(Vsm::Sram1v2),
34            _ => None,
35        }
36    }
37    #[doc = "SRAM configured for 1.0v"]
38    #[inline(always)]
39    pub fn is_sram1v0(&self) -> bool {
40        *self == Vsm::Sram1v0
41    }
42    #[doc = "SRAM configured for 1.2v"]
43    #[inline(always)]
44    pub fn is_sram1v2(&self) -> bool {
45        *self == Vsm::Sram1v2
46    }
47}
48#[doc = "Field `VSM` writer - Voltage Select Margin"]
49pub type VsmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Vsm>;
50impl<'a, REG> VsmW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "SRAM configured for 1.0v"]
56    #[inline(always)]
57    pub fn sram1v0(self) -> &'a mut crate::W<REG> {
58        self.variant(Vsm::Sram1v0)
59    }
60    #[doc = "SRAM configured for 1.2v"]
61    #[inline(always)]
62    pub fn sram1v2(self) -> &'a mut crate::W<REG> {
63        self.variant(Vsm::Sram1v2)
64    }
65}
66#[doc = "SRAM Voltage Update Request\n\nValue on reset: 0"]
67#[cfg_attr(feature = "defmt", derive(defmt::Format))]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69pub enum Req {
70    #[doc = "0: Do not request"]
71    ReqNo = 0,
72    #[doc = "1: Request"]
73    ReqYes = 1,
74}
75impl From<Req> for bool {
76    #[inline(always)]
77    fn from(variant: Req) -> Self {
78        variant as u8 != 0
79    }
80}
81#[doc = "Field `REQ` reader - SRAM Voltage Update Request"]
82pub type ReqR = crate::BitReader<Req>;
83impl ReqR {
84    #[doc = "Get enumerated values variant"]
85    #[inline(always)]
86    pub const fn variant(&self) -> Req {
87        match self.bits {
88            false => Req::ReqNo,
89            true => Req::ReqYes,
90        }
91    }
92    #[doc = "Do not request"]
93    #[inline(always)]
94    pub fn is_req_no(&self) -> bool {
95        *self == Req::ReqNo
96    }
97    #[doc = "Request"]
98    #[inline(always)]
99    pub fn is_req_yes(&self) -> bool {
100        *self == Req::ReqYes
101    }
102}
103#[doc = "Field `REQ` writer - SRAM Voltage Update Request"]
104pub type ReqW<'a, REG> = crate::BitWriter<'a, REG, Req>;
105impl<'a, REG> ReqW<'a, REG>
106where
107    REG: crate::Writable + crate::RegisterSpec,
108{
109    #[doc = "Do not request"]
110    #[inline(always)]
111    pub fn req_no(self) -> &'a mut crate::W<REG> {
112        self.variant(Req::ReqNo)
113    }
114    #[doc = "Request"]
115    #[inline(always)]
116    pub fn req_yes(self) -> &'a mut crate::W<REG> {
117        self.variant(Req::ReqYes)
118    }
119}
120#[doc = "SRAM Voltage Update Request Acknowledge\n\nValue on reset: 0"]
121#[cfg_attr(feature = "defmt", derive(defmt::Format))]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123pub enum Ack {
124    #[doc = "0: Not acknowledged"]
125    AckNo = 0,
126    #[doc = "1: Acknowledged"]
127    AckYes = 1,
128}
129impl From<Ack> for bool {
130    #[inline(always)]
131    fn from(variant: Ack) -> Self {
132        variant as u8 != 0
133    }
134}
135#[doc = "Field `ACK` reader - SRAM Voltage Update Request Acknowledge"]
136pub type AckR = crate::BitReader<Ack>;
137impl AckR {
138    #[doc = "Get enumerated values variant"]
139    #[inline(always)]
140    pub const fn variant(&self) -> Ack {
141        match self.bits {
142            false => Ack::AckNo,
143            true => Ack::AckYes,
144        }
145    }
146    #[doc = "Not acknowledged"]
147    #[inline(always)]
148    pub fn is_ack_no(&self) -> bool {
149        *self == Ack::AckNo
150    }
151    #[doc = "Acknowledged"]
152    #[inline(always)]
153    pub fn is_ack_yes(&self) -> bool {
154        *self == Ack::AckYes
155    }
156}
157impl R {
158    #[doc = "Bits 0:1 - Voltage Select Margin"]
159    #[inline(always)]
160    pub fn vsm(&self) -> VsmR {
161        VsmR::new((self.bits & 3) as u8)
162    }
163    #[doc = "Bit 30 - SRAM Voltage Update Request"]
164    #[inline(always)]
165    pub fn req(&self) -> ReqR {
166        ReqR::new(((self.bits >> 30) & 1) != 0)
167    }
168    #[doc = "Bit 31 - SRAM Voltage Update Request Acknowledge"]
169    #[inline(always)]
170    pub fn ack(&self) -> AckR {
171        AckR::new(((self.bits >> 31) & 1) != 0)
172    }
173}
174#[cfg(feature = "debug")]
175impl core::fmt::Debug for R {
176    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
177        f.debug_struct("SRAMCTL")
178            .field("vsm", &self.vsm())
179            .field("req", &self.req())
180            .field("ack", &self.ack())
181            .finish()
182    }
183}
184impl W {
185    #[doc = "Bits 0:1 - Voltage Select Margin"]
186    #[inline(always)]
187    pub fn vsm(&mut self) -> VsmW<'_, SramctlSpec> {
188        VsmW::new(self, 0)
189    }
190    #[doc = "Bit 30 - SRAM Voltage Update Request"]
191    #[inline(always)]
192    pub fn req(&mut self) -> ReqW<'_, SramctlSpec> {
193        ReqW::new(self, 30)
194    }
195}
196#[doc = "SRAM Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sramctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sramctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct SramctlSpec;
198impl crate::RegisterSpec for SramctlSpec {
199    type Ux = u32;
200}
201#[doc = "`read()` method returns [`sramctl::R`](R) reader structure"]
202impl crate::Readable for SramctlSpec {}
203#[doc = "`write(|w| ..)` method takes [`sramctl::W`](W) writer structure"]
204impl crate::Writable for SramctlSpec {
205    type Safety = crate::Unsafe;
206}
207#[doc = "`reset()` method sets SRAMCTL to value 0x01"]
208impl crate::Resettable for SramctlSpec {
209    const RESET_VALUE: u32 = 0x01;
210}